Commit | Line | Data |
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975fd0f6 GD |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | ||
98a29533 | 5 | #include <dt-bindings/clock/qcom,gcc-apq8084.h> |
66c04e30 | 6 | #include <dt-bindings/gpio/gpio.h> |
98a29533 | 7 | |
975fd0f6 GD |
8 | / { |
9 | model = "Qualcomm APQ 8084"; | |
10 | compatible = "qcom,apq8084"; | |
11 | interrupt-parent = <&intc>; | |
12 | ||
13 | cpus { | |
14 | #address-cells = <1>; | |
15 | #size-cells = <0>; | |
16 | ||
17 | cpu@0 { | |
18 | device_type = "cpu"; | |
19 | compatible = "qcom,krait"; | |
20 | reg = <0>; | |
21 | enable-method = "qcom,kpss-acc-v2"; | |
22 | next-level-cache = <&L2>; | |
23 | qcom,acc = <&acc0>; | |
24 | }; | |
25 | ||
26 | cpu@1 { | |
27 | device_type = "cpu"; | |
28 | compatible = "qcom,krait"; | |
29 | reg = <1>; | |
30 | enable-method = "qcom,kpss-acc-v2"; | |
31 | next-level-cache = <&L2>; | |
32 | qcom,acc = <&acc1>; | |
33 | }; | |
34 | ||
35 | cpu@2 { | |
36 | device_type = "cpu"; | |
37 | compatible = "qcom,krait"; | |
38 | reg = <2>; | |
39 | enable-method = "qcom,kpss-acc-v2"; | |
40 | next-level-cache = <&L2>; | |
41 | qcom,acc = <&acc2>; | |
42 | }; | |
43 | ||
44 | cpu@3 { | |
45 | device_type = "cpu"; | |
46 | compatible = "qcom,krait"; | |
47 | reg = <3>; | |
48 | enable-method = "qcom,kpss-acc-v2"; | |
49 | next-level-cache = <&L2>; | |
50 | qcom,acc = <&acc3>; | |
51 | }; | |
52 | ||
53 | L2: l2-cache { | |
54 | compatible = "qcom,arch-cache"; | |
55 | cache-level = <2>; | |
56 | qcom,saw = <&saw_l2>; | |
57 | }; | |
58 | }; | |
59 | ||
60 | cpu-pmu { | |
61 | compatible = "qcom,krait-pmu"; | |
62 | interrupts = <1 7 0xf04>; | |
63 | }; | |
64 | ||
65 | timer { | |
66 | compatible = "arm,armv7-timer"; | |
67 | interrupts = <1 2 0xf08>, | |
68 | <1 3 0xf08>, | |
69 | <1 4 0xf08>, | |
70 | <1 1 0xf08>; | |
71 | clock-frequency = <19200000>; | |
72 | }; | |
73 | ||
74 | soc: soc { | |
75 | #address-cells = <1>; | |
76 | #size-cells = <1>; | |
77 | ranges; | |
78 | compatible = "simple-bus"; | |
79 | ||
80 | intc: interrupt-controller@f9000000 { | |
81 | compatible = "qcom,msm-qgic2"; | |
82 | interrupt-controller; | |
83 | #interrupt-cells = <3>; | |
84 | reg = <0xf9000000 0x1000>, | |
85 | <0xf9002000 0x1000>; | |
86 | }; | |
87 | ||
88 | timer@f9020000 { | |
89 | #address-cells = <1>; | |
90 | #size-cells = <1>; | |
91 | ranges; | |
92 | compatible = "arm,armv7-timer-mem"; | |
93 | reg = <0xf9020000 0x1000>; | |
94 | clock-frequency = <19200000>; | |
95 | ||
96 | frame@f9021000 { | |
97 | frame-number = <0>; | |
98 | interrupts = <0 8 0x4>, | |
99 | <0 7 0x4>; | |
100 | reg = <0xf9021000 0x1000>, | |
101 | <0xf9022000 0x1000>; | |
102 | }; | |
103 | ||
104 | frame@f9023000 { | |
105 | frame-number = <1>; | |
106 | interrupts = <0 9 0x4>; | |
107 | reg = <0xf9023000 0x1000>; | |
108 | status = "disabled"; | |
109 | }; | |
110 | ||
111 | frame@f9024000 { | |
112 | frame-number = <2>; | |
113 | interrupts = <0 10 0x4>; | |
114 | reg = <0xf9024000 0x1000>; | |
115 | status = "disabled"; | |
116 | }; | |
117 | ||
118 | frame@f9025000 { | |
119 | frame-number = <3>; | |
120 | interrupts = <0 11 0x4>; | |
121 | reg = <0xf9025000 0x1000>; | |
122 | status = "disabled"; | |
123 | }; | |
124 | ||
125 | frame@f9026000 { | |
126 | frame-number = <4>; | |
127 | interrupts = <0 12 0x4>; | |
128 | reg = <0xf9026000 0x1000>; | |
129 | status = "disabled"; | |
130 | }; | |
131 | ||
132 | frame@f9027000 { | |
133 | frame-number = <5>; | |
134 | interrupts = <0 13 0x4>; | |
135 | reg = <0xf9027000 0x1000>; | |
136 | status = "disabled"; | |
137 | }; | |
138 | ||
139 | frame@f9028000 { | |
140 | frame-number = <6>; | |
141 | interrupts = <0 14 0x4>; | |
142 | reg = <0xf9028000 0x1000>; | |
143 | status = "disabled"; | |
144 | }; | |
145 | }; | |
146 | ||
147 | saw_l2: regulator@f9012000 { | |
148 | compatible = "qcom,saw2"; | |
149 | reg = <0xf9012000 0x1000>; | |
150 | regulator; | |
151 | }; | |
152 | ||
153 | acc0: clock-controller@f9088000 { | |
154 | compatible = "qcom,kpss-acc-v2"; | |
155 | reg = <0xf9088000 0x1000>, | |
156 | <0xf9008000 0x1000>; | |
157 | }; | |
158 | ||
159 | acc1: clock-controller@f9098000 { | |
160 | compatible = "qcom,kpss-acc-v2"; | |
161 | reg = <0xf9098000 0x1000>, | |
162 | <0xf9008000 0x1000>; | |
163 | }; | |
164 | ||
165 | acc2: clock-controller@f90a8000 { | |
166 | compatible = "qcom,kpss-acc-v2"; | |
167 | reg = <0xf90a8000 0x1000>, | |
168 | <0xf9008000 0x1000>; | |
169 | }; | |
170 | ||
171 | acc3: clock-controller@f90b8000 { | |
172 | compatible = "qcom,kpss-acc-v2"; | |
173 | reg = <0xf90b8000 0x1000>, | |
174 | <0xf9008000 0x1000>; | |
175 | }; | |
176 | ||
177 | restart@fc4ab000 { | |
178 | compatible = "qcom,pshold"; | |
179 | reg = <0xfc4ab000 0x4>; | |
180 | }; | |
98a29533 GD |
181 | |
182 | gcc: clock-controller@fc400000 { | |
183 | compatible = "qcom,gcc-apq8084"; | |
184 | #clock-cells = <1>; | |
185 | #reset-cells = <1>; | |
186 | reg = <0xfc400000 0x4000>; | |
187 | }; | |
188 | ||
44980b28 GD |
189 | tlmm: pinctrl@fd510000 { |
190 | compatible = "qcom,apq8084-pinctrl"; | |
191 | reg = <0xfd510000 0x4000>; | |
192 | gpio-controller; | |
193 | #gpio-cells = <2>; | |
194 | interrupt-controller; | |
195 | #interrupt-cells = <2>; | |
196 | interrupts = <0 208 0>; | |
197 | }; | |
198 | ||
14ff1c43 GD |
199 | serial@f995e000 { |
200 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
201 | reg = <0xf995e000 0x1000>; | |
202 | interrupts = <0 114 0x0>; | |
203 | clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; | |
204 | clock-names = "core", "iface"; | |
205 | status = "disabled"; | |
206 | }; | |
66c04e30 GD |
207 | |
208 | sdhci@f9824900 { | |
209 | compatible = "qcom,sdhci-msm-v4"; | |
210 | reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; | |
211 | reg-names = "hc_mem", "core_mem"; | |
212 | interrupts = <0 123 0>, <0 138 0>; | |
213 | interrupt-names = "hc_irq", "pwr_irq"; | |
214 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; | |
215 | clock-names = "core", "iface"; | |
216 | status = "disabled"; | |
217 | }; | |
218 | ||
219 | sdhci@f98a4900 { | |
220 | compatible = "qcom,sdhci-msm-v4"; | |
221 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; | |
222 | reg-names = "hc_mem", "core_mem"; | |
223 | interrupts = <0 125 0>, <0 221 0>; | |
224 | interrupt-names = "hc_irq", "pwr_irq"; | |
225 | clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; | |
226 | clock-names = "core", "iface"; | |
227 | status = "disabled"; | |
228 | }; | |
975fd0f6 GD |
229 | }; |
230 | }; |