[deliverable/linux.git] / arch / arm / boot / dts / qcom-apq8084.dtsi

/dts-v1/;

#include "skeleton.dtsi"

#include <dt-bindings/clock/qcom,gcc-apq8084.h>
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Qualcomm APQ 8084";
	compatible = "qcom,apq8084";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <0>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <1>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <2>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc2>;
			qcom,saw = <&saw2>;
			cpu-idle-states = <&CPU_SPC>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "qcom,krait";
			reg = <3>;
			enable-method = "qcom,kpss-acc-v2";
			next-level-cache = <&L2>;
			qcom,acc = <&acc3>;
			qcom,saw = <&saw3>;
			cpu-idle-states = <&CPU_SPC>;
		};

		L2: l2-cache {
			compatible = "qcom,arch-cache";
			cache-level = <2>;
			qcom,saw = <&saw_l2>;
		};

		idle-states {
			CPU_SPC: spc {
				compatible = "qcom,idle-state-spc",
						"arm,idle-state";
				entry-latency-us = <150>;
				exit-latency-us = <200>;
				min-residency-us = <2000>;
			};
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 7 0xf04>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 2 0xf08>,
			     <1 3 0xf08>,
			     <1 4 0xf08>,
			     <1 1 0xf08>;
		clock-frequency = <19200000>;
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@f9000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0xf9000000 0x1000>,
			      <0xf9002000 0x1000>;
		};

		timer@f9020000 {
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			compatible = "arm,armv7-timer-mem";
			reg = <0xf9020000 0x1000>;
			clock-frequency = <19200000>;

			frame@f9021000 {
				frame-number = <0>;
				interrupts = <0 8 0x4>,
					     <0 7 0x4>;
				reg = <0xf9021000 0x1000>,
				      <0xf9022000 0x1000>;
			};

			frame@f9023000 {
				frame-number = <1>;
				interrupts = <0 9 0x4>;
				reg = <0xf9023000 0x1000>;
				status = "disabled";
			};

			frame@f9024000 {
				frame-number = <2>;
				interrupts = <0 10 0x4>;
				reg = <0xf9024000 0x1000>;
				status = "disabled";
			};

			frame@f9025000 {
				frame-number = <3>;
				interrupts = <0 11 0x4>;
				reg = <0xf9025000 0x1000>;
				status = "disabled";
			};

			frame@f9026000 {
				frame-number = <4>;
				interrupts = <0 12 0x4>;
				reg = <0xf9026000 0x1000>;
				status = "disabled";
			};

			frame@f9027000 {
				frame-number = <5>;
				interrupts = <0 13 0x4>;
				reg = <0xf9027000 0x1000>;
				status = "disabled";
			};

			frame@f9028000 {
				frame-number = <6>;
				interrupts = <0 14 0x4>;
				reg = <0xf9028000 0x1000>;
				status = "disabled";
			};
		};

		saw0: power-controller@f9089000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
		};

		saw1: power-controller@f9099000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
		};

		saw2: power-controller@f90a9000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw3: power-controller@f90b9000 {
			compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
			reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
		};

		saw_l2: power-controller@f9012000 {
			compatible = "qcom,saw2";
			reg = <0xf9012000 0x1000>;
			regulator;
		};

		acc0: clock-controller@f9088000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9088000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc1: clock-controller@f9098000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf9098000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc2: clock-controller@f90a8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90a8000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		acc3: clock-controller@f90b8000 {
			compatible = "qcom,kpss-acc-v2";
			reg = <0xf90b8000 0x1000>,
			      <0xf9008000 0x1000>;
		};

		restart@fc4ab000 {
			compatible = "qcom,pshold";
			reg = <0xfc4ab000 0x4>;
		};

		gcc: clock-controller@fc400000 {
			compatible = "qcom,gcc-apq8084";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0xfc400000 0x4000>;
		};

		tlmm: pinctrl@fd510000 {
			compatible = "qcom,apq8084-pinctrl";
			reg = <0xfd510000 0x4000>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			interrupts = <0 208 0>;
		};

		serial@f995e000 {
			compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
			reg = <0xf995e000 0x1000>;
			interrupts = <0 114 0x0>;
			clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f9824900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 123 0>, <0 138 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		sdhci@f98a4900 {
			compatible = "qcom,sdhci-msm-v4";
			reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
			reg-names = "hc_mem", "core_mem";
			interrupts = <0 125 0>, <0 221 0>;
			interrupt-names = "hc_irq", "pwr_irq";
			clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
			clock-names = "core", "iface";
			status = "disabled";
		};

		spmi_bus: spmi@fc4cf000 {
			compatible = "qcom,spmi-pmic-arb";
			reg-names = "core", "intr", "cnfg";
			reg = <0xfc4cf000 0x1000>,
			      <0xfc4cb000 0x1000>,
			      <0xfc4ca000 0x1000>;
			interrupt-names = "periph_irq";
			interrupts = <0 190 0>;
			qcom,ee = <0>;
			qcom,channel = <0>;
			#address-cells = <2>;
			#size-cells = <0>;
			interrupt-controller;
			#interrupt-cells = <4>;
		};
	};
};
Commit	Line	Data
975fd0f6 GD	1	/dts-v1/;
	2
	3	#include "skeleton.dtsi"
	4
98a29533	5	#include <dt-bindings/clock/qcom,gcc-apq8084.h>
66c04e30	6	#include <dt-bindings/gpio/gpio.h>
98a29533	7
975fd0f6 GD	8	/ {
	9	model = "Qualcomm APQ 8084";
	10	compatible = "qcom,apq8084";
	11	interrupt-parent = <&intc>;
	12
	13	cpus {
	14	#address-cells = <1>;
	15	#size-cells = <0>;
	16
	17	cpu@0 {
	18	device_type = "cpu";
	19	compatible = "qcom,krait";
	20	reg = <0>;
	21	enable-method = "qcom,kpss-acc-v2";
	22	next-level-cache = <&L2>;
	23	qcom,acc = <&acc0>;
030e27f6	24	qcom,saw = <&saw0>;
d8664979	25	cpu-idle-states = <&CPU_SPC>;
975fd0f6 GD	26	};
	27
	28	cpu@1 {
	29	device_type = "cpu";
	30	compatible = "qcom,krait";
	31	reg = <1>;
	32	enable-method = "qcom,kpss-acc-v2";
	33	next-level-cache = <&L2>;
	34	qcom,acc = <&acc1>;
030e27f6	35	qcom,saw = <&saw1>;
d8664979	36	cpu-idle-states = <&CPU_SPC>;
975fd0f6 GD	37	};
	38
	39	cpu@2 {
	40	device_type = "cpu";
	41	compatible = "qcom,krait";
	42	reg = <2>;
	43	enable-method = "qcom,kpss-acc-v2";
	44	next-level-cache = <&L2>;
	45	qcom,acc = <&acc2>;
030e27f6	46	qcom,saw = <&saw2>;
d8664979	47	cpu-idle-states = <&CPU_SPC>;
975fd0f6 GD	48	};
	49
	50	cpu@3 {
	51	device_type = "cpu";
	52	compatible = "qcom,krait";
	53	reg = <3>;
	54	enable-method = "qcom,kpss-acc-v2";
	55	next-level-cache = <&L2>;
	56	qcom,acc = <&acc3>;
030e27f6	57	qcom,saw = <&saw3>;
d8664979	58	cpu-idle-states = <&CPU_SPC>;
975fd0f6 GD	59	};
	60
	61	L2: l2-cache {
	62	compatible = "qcom,arch-cache";
	63	cache-level = <2>;
	64	qcom,saw = <&saw_l2>;
	65	};
d8664979 LI	66
	67	idle-states {
	68	CPU_SPC: spc {
	69	compatible = "qcom,idle-state-spc",
	70	"arm,idle-state";
	71	entry-latency-us = <150>;
	72	exit-latency-us = <200>;
	73	min-residency-us = <2000>;
	74	};
	75	};
975fd0f6 GD	76	};
	77
	78	cpu-pmu {
	79	compatible = "qcom,krait-pmu";
	80	interrupts = <1 7 0xf04>;
	81	};
	82
	83	timer {
	84	compatible = "arm,armv7-timer";
	85	interrupts = <1 2 0xf08>,
	86	<1 3 0xf08>,
	87	<1 4 0xf08>,
	88	<1 1 0xf08>;
	89	clock-frequency = <19200000>;
	90	};
	91
	92	soc: soc {
	93	#address-cells = <1>;
	94	#size-cells = <1>;
	95	ranges;
	96	compatible = "simple-bus";
	97
	98	intc: interrupt-controller@f9000000 {
	99	compatible = "qcom,msm-qgic2";
	100	interrupt-controller;
	101	#interrupt-cells = <3>;
	102	reg = <0xf9000000 0x1000>,
	103	<0xf9002000 0x1000>;
	104	};
	105
	106	timer@f9020000 {
	107	#address-cells = <1>;
	108	#size-cells = <1>;
	109	ranges;
	110	compatible = "arm,armv7-timer-mem";
	111	reg = <0xf9020000 0x1000>;
	112	clock-frequency = <19200000>;
	113
	114	frame@f9021000 {
	115	frame-number = <0>;
	116	interrupts = <0 8 0x4>,
	117	<0 7 0x4>;
	118	reg = <0xf9021000 0x1000>,
	119	<0xf9022000 0x1000>;
	120	};
	121
	122	frame@f9023000 {
	123	frame-number = <1>;
	124	interrupts = <0 9 0x4>;
	125	reg = <0xf9023000 0x1000>;
	126	status = "disabled";
	127	};
	128
	129	frame@f9024000 {
	130	frame-number = <2>;
	131	interrupts = <0 10 0x4>;
	132	reg = <0xf9024000 0x1000>;
	133	status = "disabled";
	134	};
	135
	136	frame@f9025000 {
	137	frame-number = <3>;
	138	interrupts = <0 11 0x4>;
	139	reg = <0xf9025000 0x1000>;
140	status = "disabled";
141	};
142
143	frame@f9026000 {
144	frame-number = <4>;
145	interrupts = <0 12 0x4>;
146	reg = <0xf9026000 0x1000>;
147	status = "disabled";
148	};
149
150	frame@f9027000 {
151	frame-number = <5>;
152	interrupts = <0 13 0x4>;
153	reg = <0xf9027000 0x1000>;
154	status = "disabled";
155	};
156
157	frame@f9028000 {
158	frame-number = <6>;
159	interrupts = <0 14 0x4>;
160	reg = <0xf9028000 0x1000>;
161	status = "disabled";
162	};
163	};
164
030e27f6 LI	165	saw0: power-controller@f9089000 {
	166	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	167	reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>;
	168	};
	169
	170	saw1: power-controller@f9099000 {
	171	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	172	reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>;
	173	};
	174
	175	saw2: power-controller@f90a9000 {
	176	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	177	reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>;
	178	};
	179
	180	saw3: power-controller@f90b9000 {
	181	compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2";
	182	reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>;
	183	};
	184
	185	saw_l2: power-controller@f9012000 {
975fd0f6 GD	186	compatible = "qcom,saw2";
	187	reg = <0xf9012000 0x1000>;
	188	regulator;
	189	};
	190
	191	acc0: clock-controller@f9088000 {
	192	compatible = "qcom,kpss-acc-v2";
	193	reg = <0xf9088000 0x1000>,
	194	<0xf9008000 0x1000>;
	195	};
	196
	197	acc1: clock-controller@f9098000 {
	198	compatible = "qcom,kpss-acc-v2";
	199	reg = <0xf9098000 0x1000>,
	200	<0xf9008000 0x1000>;
	201	};
	202
	203	acc2: clock-controller@f90a8000 {
	204	compatible = "qcom,kpss-acc-v2";
	205	reg = <0xf90a8000 0x1000>,
	206	<0xf9008000 0x1000>;
	207	};
	208
	209	acc3: clock-controller@f90b8000 {
	210	compatible = "qcom,kpss-acc-v2";
	211	reg = <0xf90b8000 0x1000>,
	212	<0xf9008000 0x1000>;
	213	};
	214
	215	restart@fc4ab000 {
	216	compatible = "qcom,pshold";
	217	reg = <0xfc4ab000 0x4>;
	218	};
98a29533 GD	219
	220	gcc: clock-controller@fc400000 {
	221	compatible = "qcom,gcc-apq8084";
	222	#clock-cells = <1>;
	223	#reset-cells = <1>;
	224	reg = <0xfc400000 0x4000>;
	225	};
	226
44980b28 GD	227	tlmm: pinctrl@fd510000 {
	228	compatible = "qcom,apq8084-pinctrl";
	229	reg = <0xfd510000 0x4000>;
	230	gpio-controller;
	231	#gpio-cells = <2>;
	232	interrupt-controller;
	233	#interrupt-cells = <2>;
	234	interrupts = <0 208 0>;
	235	};
	236
14ff1c43 GD	237	serial@f995e000 {
	238	compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
	239	reg = <0xf995e000 0x1000>;
	240	interrupts = <0 114 0x0>;
	241	clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
	242	clock-names = "core", "iface";
	243	status = "disabled";
	244	};
66c04e30 GD	245
	246	sdhci@f9824900 {
	247	compatible = "qcom,sdhci-msm-v4";
	248	reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
	249	reg-names = "hc_mem", "core_mem";
	250	interrupts = <0 123 0>, <0 138 0>;
	251	interrupt-names = "hc_irq", "pwr_irq";
	252	clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
	253	clock-names = "core", "iface";
	254	status = "disabled";
	255	};
	256
	257	sdhci@f98a4900 {
	258	compatible = "qcom,sdhci-msm-v4";
	259	reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
	260	reg-names = "hc_mem", "core_mem";
	261	interrupts = <0 125 0>, <0 221 0>;
	262	interrupt-names = "hc_irq", "pwr_irq";
	263	clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
	264	clock-names = "core", "iface";
	265	status = "disabled";
	266	};
af22e46d II	267
	268	spmi_bus: spmi@fc4cf000 {
	269	compatible = "qcom,spmi-pmic-arb";
	270	reg-names = "core", "intr", "cnfg";
	271	reg = <0xfc4cf000 0x1000>,
	272	<0xfc4cb000 0x1000>,
	273	<0xfc4ca000 0x1000>;
	274	interrupt-names = "periph_irq";
	275	interrupts = <0 190 0>;
	276	qcom,ee = <0>;
	277	qcom,channel = <0>;
	278	#address-cells = <2>;
	279	#size-cells = <0>;
	280	interrupt-controller;
	281	#interrupt-cells = <4>;
	282	};
975fd0f6 GD	283	};
975fd0f6 GD	284	};