Commit | Line | Data |
---|---|---|
975fd0f6 GD |
1 | /dts-v1/; |
2 | ||
3 | #include "skeleton.dtsi" | |
4 | ||
98a29533 | 5 | #include <dt-bindings/clock/qcom,gcc-apq8084.h> |
66c04e30 | 6 | #include <dt-bindings/gpio/gpio.h> |
98a29533 | 7 | |
975fd0f6 GD |
8 | / { |
9 | model = "Qualcomm APQ 8084"; | |
10 | compatible = "qcom,apq8084"; | |
11 | interrupt-parent = <&intc>; | |
12 | ||
64ab8863 AG |
13 | reserved-memory { |
14 | #address-cells = <1>; | |
15 | #size-cells = <1>; | |
16 | ranges; | |
17 | ||
18 | smem_mem: smem_region@fa00000 { | |
19 | reg = <0xfa00000 0x200000>; | |
20 | no-map; | |
21 | }; | |
22 | }; | |
23 | ||
975fd0f6 GD |
24 | cpus { |
25 | #address-cells = <1>; | |
26 | #size-cells = <0>; | |
27 | ||
28 | cpu@0 { | |
29 | device_type = "cpu"; | |
30 | compatible = "qcom,krait"; | |
31 | reg = <0>; | |
32 | enable-method = "qcom,kpss-acc-v2"; | |
33 | next-level-cache = <&L2>; | |
34 | qcom,acc = <&acc0>; | |
030e27f6 | 35 | qcom,saw = <&saw0>; |
d8664979 | 36 | cpu-idle-states = <&CPU_SPC>; |
975fd0f6 GD |
37 | }; |
38 | ||
39 | cpu@1 { | |
40 | device_type = "cpu"; | |
41 | compatible = "qcom,krait"; | |
42 | reg = <1>; | |
43 | enable-method = "qcom,kpss-acc-v2"; | |
44 | next-level-cache = <&L2>; | |
45 | qcom,acc = <&acc1>; | |
030e27f6 | 46 | qcom,saw = <&saw1>; |
d8664979 | 47 | cpu-idle-states = <&CPU_SPC>; |
975fd0f6 GD |
48 | }; |
49 | ||
50 | cpu@2 { | |
51 | device_type = "cpu"; | |
52 | compatible = "qcom,krait"; | |
53 | reg = <2>; | |
54 | enable-method = "qcom,kpss-acc-v2"; | |
55 | next-level-cache = <&L2>; | |
56 | qcom,acc = <&acc2>; | |
030e27f6 | 57 | qcom,saw = <&saw2>; |
d8664979 | 58 | cpu-idle-states = <&CPU_SPC>; |
975fd0f6 GD |
59 | }; |
60 | ||
61 | cpu@3 { | |
62 | device_type = "cpu"; | |
63 | compatible = "qcom,krait"; | |
64 | reg = <3>; | |
65 | enable-method = "qcom,kpss-acc-v2"; | |
66 | next-level-cache = <&L2>; | |
67 | qcom,acc = <&acc3>; | |
030e27f6 | 68 | qcom,saw = <&saw3>; |
d8664979 | 69 | cpu-idle-states = <&CPU_SPC>; |
975fd0f6 GD |
70 | }; |
71 | ||
72 | L2: l2-cache { | |
73 | compatible = "qcom,arch-cache"; | |
74 | cache-level = <2>; | |
75 | qcom,saw = <&saw_l2>; | |
76 | }; | |
d8664979 LI |
77 | |
78 | idle-states { | |
79 | CPU_SPC: spc { | |
80 | compatible = "qcom,idle-state-spc", | |
81 | "arm,idle-state"; | |
82 | entry-latency-us = <150>; | |
83 | exit-latency-us = <200>; | |
84 | min-residency-us = <2000>; | |
85 | }; | |
86 | }; | |
975fd0f6 GD |
87 | }; |
88 | ||
2b9b5466 AG |
89 | firmware { |
90 | scm { | |
91 | compatible = "qcom,scm"; | |
92 | clocks = <&gcc GCC_CE1_CLK> , <&gcc GCC_CE1_AXI_CLK>, <&gcc GCC_CE1_AHB_CLK>; | |
93 | clock-names = "core", "bus", "iface"; | |
94 | }; | |
95 | }; | |
96 | ||
975fd0f6 GD |
97 | cpu-pmu { |
98 | compatible = "qcom,krait-pmu"; | |
99 | interrupts = <1 7 0xf04>; | |
100 | }; | |
101 | ||
30fc4212 SB |
102 | clocks { |
103 | xo_board { | |
104 | compatible = "fixed-clock"; | |
105 | #clock-cells = <0>; | |
106 | clock-frequency = <19200000>; | |
107 | }; | |
108 | ||
109 | sleep_clk { | |
110 | compatible = "fixed-clock"; | |
111 | #clock-cells = <0>; | |
112 | clock-frequency = <32768>; | |
113 | }; | |
114 | }; | |
115 | ||
975fd0f6 GD |
116 | timer { |
117 | compatible = "arm,armv7-timer"; | |
118 | interrupts = <1 2 0xf08>, | |
119 | <1 3 0xf08>, | |
120 | <1 4 0xf08>, | |
121 | <1 1 0xf08>; | |
122 | clock-frequency = <19200000>; | |
123 | }; | |
124 | ||
64ab8863 AG |
125 | smem { |
126 | compatible = "qcom,smem"; | |
127 | ||
128 | qcom,rpm-msg-ram = <&rpm_msg_ram>; | |
129 | memory-region = <&smem_mem>; | |
130 | ||
131 | hwlocks = <&tcsr_mutex 3>; | |
132 | }; | |
133 | ||
975fd0f6 GD |
134 | soc: soc { |
135 | #address-cells = <1>; | |
136 | #size-cells = <1>; | |
137 | ranges; | |
138 | compatible = "simple-bus"; | |
139 | ||
140 | intc: interrupt-controller@f9000000 { | |
141 | compatible = "qcom,msm-qgic2"; | |
142 | interrupt-controller; | |
143 | #interrupt-cells = <3>; | |
144 | reg = <0xf9000000 0x1000>, | |
145 | <0xf9002000 0x1000>; | |
146 | }; | |
147 | ||
53ced99d AG |
148 | apcs: syscon@f9011000 { |
149 | compatible = "syscon"; | |
150 | reg = <0xf9011000 0x1000>; | |
151 | }; | |
152 | ||
975fd0f6 GD |
153 | timer@f9020000 { |
154 | #address-cells = <1>; | |
155 | #size-cells = <1>; | |
156 | ranges; | |
157 | compatible = "arm,armv7-timer-mem"; | |
158 | reg = <0xf9020000 0x1000>; | |
159 | clock-frequency = <19200000>; | |
160 | ||
161 | frame@f9021000 { | |
162 | frame-number = <0>; | |
163 | interrupts = <0 8 0x4>, | |
164 | <0 7 0x4>; | |
165 | reg = <0xf9021000 0x1000>, | |
166 | <0xf9022000 0x1000>; | |
167 | }; | |
168 | ||
169 | frame@f9023000 { | |
170 | frame-number = <1>; | |
171 | interrupts = <0 9 0x4>; | |
172 | reg = <0xf9023000 0x1000>; | |
173 | status = "disabled"; | |
174 | }; | |
175 | ||
176 | frame@f9024000 { | |
177 | frame-number = <2>; | |
178 | interrupts = <0 10 0x4>; | |
179 | reg = <0xf9024000 0x1000>; | |
180 | status = "disabled"; | |
181 | }; | |
182 | ||
183 | frame@f9025000 { | |
184 | frame-number = <3>; | |
185 | interrupts = <0 11 0x4>; | |
186 | reg = <0xf9025000 0x1000>; | |
187 | status = "disabled"; | |
188 | }; | |
189 | ||
190 | frame@f9026000 { | |
191 | frame-number = <4>; | |
192 | interrupts = <0 12 0x4>; | |
193 | reg = <0xf9026000 0x1000>; | |
194 | status = "disabled"; | |
195 | }; | |
196 | ||
197 | frame@f9027000 { | |
198 | frame-number = <5>; | |
199 | interrupts = <0 13 0x4>; | |
200 | reg = <0xf9027000 0x1000>; | |
201 | status = "disabled"; | |
202 | }; | |
203 | ||
204 | frame@f9028000 { | |
205 | frame-number = <6>; | |
206 | interrupts = <0 14 0x4>; | |
207 | reg = <0xf9028000 0x1000>; | |
208 | status = "disabled"; | |
209 | }; | |
210 | }; | |
211 | ||
030e27f6 LI |
212 | saw0: power-controller@f9089000 { |
213 | compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; | |
214 | reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; | |
215 | }; | |
216 | ||
217 | saw1: power-controller@f9099000 { | |
218 | compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; | |
219 | reg = <0xf9099000 0x1000>, <0xf9009000 0x1000>; | |
220 | }; | |
221 | ||
222 | saw2: power-controller@f90a9000 { | |
223 | compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; | |
224 | reg = <0xf90a9000 0x1000>, <0xf9009000 0x1000>; | |
225 | }; | |
226 | ||
227 | saw3: power-controller@f90b9000 { | |
228 | compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; | |
229 | reg = <0xf90b9000 0x1000>, <0xf9009000 0x1000>; | |
230 | }; | |
231 | ||
232 | saw_l2: power-controller@f9012000 { | |
975fd0f6 GD |
233 | compatible = "qcom,saw2"; |
234 | reg = <0xf9012000 0x1000>; | |
235 | regulator; | |
236 | }; | |
237 | ||
238 | acc0: clock-controller@f9088000 { | |
239 | compatible = "qcom,kpss-acc-v2"; | |
240 | reg = <0xf9088000 0x1000>, | |
241 | <0xf9008000 0x1000>; | |
242 | }; | |
243 | ||
244 | acc1: clock-controller@f9098000 { | |
245 | compatible = "qcom,kpss-acc-v2"; | |
246 | reg = <0xf9098000 0x1000>, | |
247 | <0xf9008000 0x1000>; | |
248 | }; | |
249 | ||
250 | acc2: clock-controller@f90a8000 { | |
251 | compatible = "qcom,kpss-acc-v2"; | |
252 | reg = <0xf90a8000 0x1000>, | |
253 | <0xf9008000 0x1000>; | |
254 | }; | |
255 | ||
256 | acc3: clock-controller@f90b8000 { | |
257 | compatible = "qcom,kpss-acc-v2"; | |
258 | reg = <0xf90b8000 0x1000>, | |
259 | <0xf9008000 0x1000>; | |
260 | }; | |
261 | ||
262 | restart@fc4ab000 { | |
263 | compatible = "qcom,pshold"; | |
264 | reg = <0xfc4ab000 0x4>; | |
265 | }; | |
98a29533 GD |
266 | |
267 | gcc: clock-controller@fc400000 { | |
268 | compatible = "qcom,gcc-apq8084"; | |
269 | #clock-cells = <1>; | |
270 | #reset-cells = <1>; | |
89c7e671 | 271 | #power-domain-cells = <1>; |
98a29533 GD |
272 | reg = <0xfc400000 0x4000>; |
273 | }; | |
274 | ||
64ab8863 AG |
275 | tcsr_mutex_regs: syscon@fd484000 { |
276 | compatible = "syscon"; | |
277 | reg = <0xfd484000 0x2000>; | |
278 | }; | |
279 | ||
280 | tcsr_mutex: hwlock { | |
281 | compatible = "qcom,tcsr-mutex"; | |
282 | syscon = <&tcsr_mutex_regs 0 0x80>; | |
283 | #hwlock-cells = <1>; | |
284 | }; | |
285 | ||
286 | rpm_msg_ram: memory@fc428000 { | |
287 | compatible = "qcom,rpm-msg-ram"; | |
288 | reg = <0xfc428000 0x4000>; | |
289 | }; | |
290 | ||
44980b28 GD |
291 | tlmm: pinctrl@fd510000 { |
292 | compatible = "qcom,apq8084-pinctrl"; | |
293 | reg = <0xfd510000 0x4000>; | |
294 | gpio-controller; | |
295 | #gpio-cells = <2>; | |
296 | interrupt-controller; | |
297 | #interrupt-cells = <2>; | |
298 | interrupts = <0 208 0>; | |
299 | }; | |
300 | ||
10bfcfea | 301 | blsp2_uart2: serial@f995e000 { |
14ff1c43 GD |
302 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; |
303 | reg = <0xf995e000 0x1000>; | |
304 | interrupts = <0 114 0x0>; | |
305 | clocks = <&gcc GCC_BLSP2_UART2_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>; | |
306 | clock-names = "core", "iface"; | |
307 | status = "disabled"; | |
308 | }; | |
66c04e30 GD |
309 | |
310 | sdhci@f9824900 { | |
311 | compatible = "qcom,sdhci-msm-v4"; | |
312 | reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; | |
313 | reg-names = "hc_mem", "core_mem"; | |
314 | interrupts = <0 123 0>, <0 138 0>; | |
315 | interrupt-names = "hc_irq", "pwr_irq"; | |
316 | clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>; | |
317 | clock-names = "core", "iface"; | |
318 | status = "disabled"; | |
319 | }; | |
320 | ||
321 | sdhci@f98a4900 { | |
322 | compatible = "qcom,sdhci-msm-v4"; | |
323 | reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; | |
324 | reg-names = "hc_mem", "core_mem"; | |
325 | interrupts = <0 125 0>, <0 221 0>; | |
326 | interrupt-names = "hc_irq", "pwr_irq"; | |
327 | clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>; | |
328 | clock-names = "core", "iface"; | |
329 | status = "disabled"; | |
330 | }; | |
af22e46d II |
331 | |
332 | spmi_bus: spmi@fc4cf000 { | |
333 | compatible = "qcom,spmi-pmic-arb"; | |
334 | reg-names = "core", "intr", "cnfg"; | |
335 | reg = <0xfc4cf000 0x1000>, | |
336 | <0xfc4cb000 0x1000>, | |
337 | <0xfc4ca000 0x1000>; | |
338 | interrupt-names = "periph_irq"; | |
339 | interrupts = <0 190 0>; | |
340 | qcom,ee = <0>; | |
341 | qcom,channel = <0>; | |
342 | #address-cells = <2>; | |
343 | #size-cells = <0>; | |
344 | interrupt-controller; | |
345 | #interrupt-cells = <4>; | |
346 | }; | |
975fd0f6 | 347 | }; |
53ced99d AG |
348 | |
349 | smd { | |
350 | compatible = "qcom,smd"; | |
351 | ||
352 | rpm { | |
353 | interrupts = <0 168 1>; | |
354 | qcom,ipc = <&apcs 8 0>; | |
355 | qcom,smd-edge = <15>; | |
356 | ||
357 | rpm_requests { | |
358 | compatible = "qcom,rpm-apq8084"; | |
359 | qcom,smd-channels = "rpm_requests"; | |
4add1074 AG |
360 | |
361 | pma8084-regulators { | |
362 | compatible = "qcom,rpm-pma8084-regulators"; | |
363 | ||
364 | pma8084_s1: s1 {}; | |
365 | pma8084_s2: s2 {}; | |
366 | pma8084_s3: s3 {}; | |
367 | pma8084_s4: s4 {}; | |
368 | pma8084_s5: s5 {}; | |
369 | pma8084_s6: s6 {}; | |
370 | pma8084_s7: s7 {}; | |
371 | pma8084_s8: s8 {}; | |
372 | pma8084_s9: s9 {}; | |
373 | pma8084_s10: s10 {}; | |
374 | pma8084_s11: s11 {}; | |
375 | pma8084_s12: s12 {}; | |
376 | ||
377 | pma8084_l1: l1 {}; | |
378 | pma8084_l2: l2 {}; | |
379 | pma8084_l3: l3 {}; | |
380 | pma8084_l4: l4 {}; | |
381 | pma8084_l5: l5 {}; | |
382 | pma8084_l6: l6 {}; | |
383 | pma8084_l7: l7 {}; | |
384 | pma8084_l8: l8 {}; | |
385 | pma8084_l9: l9 {}; | |
386 | pma8084_l10: l10 {}; | |
387 | pma8084_l11: l11 {}; | |
388 | pma8084_l12: l12 {}; | |
389 | pma8084_l13: l13 {}; | |
390 | pma8084_l14: l14 {}; | |
391 | pma8084_l15: l15 {}; | |
392 | pma8084_l16: l16 {}; | |
393 | pma8084_l17: l17 {}; | |
394 | pma8084_l18: l18 {}; | |
395 | pma8084_l19: l19 {}; | |
396 | pma8084_l20: l20 {}; | |
397 | pma8084_l21: l21 {}; | |
398 | pma8084_l22: l22 {}; | |
399 | pma8084_l23: l23 {}; | |
400 | pma8084_l24: l24 {}; | |
401 | pma8084_l25: l25 {}; | |
402 | pma8084_l26: l26 {}; | |
403 | pma8084_l27: l27 {}; | |
404 | ||
405 | pma8084_lvs1: lvs1 {}; | |
406 | pma8084_lvs2: lvs2 {}; | |
407 | pma8084_lvs3: lvs3 {}; | |
408 | pma8084_lvs4: lvs4 {}; | |
409 | ||
410 | pma8084_5vs1: 5vs1 {}; | |
411 | }; | |
53ced99d AG |
412 | }; |
413 | }; | |
414 | }; | |
975fd0f6 | 415 | }; |