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cc60a1a4 KG |
1 | /dts-v1/; |
2 | ||
3 | /include/ "skeleton.dtsi" | |
4 | ||
5 | #include <dt-bindings/clock/qcom,gcc-msm8660.h> | |
66a6c317 | 6 | #include <dt-bindings/soc/qcom,gsbi.h> |
cc60a1a4 KG |
7 | |
8 | / { | |
9 | model = "Qualcomm MSM8660"; | |
10 | compatible = "qcom,msm8660"; | |
11 | interrupt-parent = <&intc>; | |
12 | ||
2ab27991 RV |
13 | cpus { |
14 | #address-cells = <1>; | |
15 | #size-cells = <0>; | |
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16 | |
17 | cpu@0 { | |
66a6c317 KG |
18 | compatible = "qcom,scorpion"; |
19 | enable-method = "qcom,gcc-msm8660"; | |
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20 | device_type = "cpu"; |
21 | reg = <0>; | |
22 | next-level-cache = <&L2>; | |
23 | }; | |
24 | ||
25 | cpu@1 { | |
66a6c317 KG |
26 | compatible = "qcom,scorpion"; |
27 | enable-method = "qcom,gcc-msm8660"; | |
2ab27991 RV |
28 | device_type = "cpu"; |
29 | reg = <1>; | |
30 | next-level-cache = <&L2>; | |
31 | }; | |
32 | ||
33 | L2: l2-cache { | |
34 | compatible = "cache"; | |
35 | cache-level = <2>; | |
36 | }; | |
37 | }; | |
38 | ||
66a6c317 KG |
39 | soc: soc { |
40 | #address-cells = <1>; | |
41 | #size-cells = <1>; | |
42 | ranges; | |
43 | compatible = "simple-bus"; | |
cc60a1a4 | 44 | |
66a6c317 KG |
45 | intc: interrupt-controller@2080000 { |
46 | compatible = "qcom,msm-8660-qgic"; | |
47 | interrupt-controller; | |
48 | #interrupt-cells = <3>; | |
49 | reg = < 0x02080000 0x1000 >, | |
50 | < 0x02081000 0x1000 >; | |
51 | }; | |
cc60a1a4 | 52 | |
66a6c317 KG |
53 | timer@2000000 { |
54 | compatible = "qcom,scss-timer", "qcom,msm-timer"; | |
55 | interrupts = <1 0 0x301>, | |
56 | <1 1 0x301>, | |
57 | <1 2 0x301>; | |
58 | reg = <0x02000000 0x100>; | |
59 | clock-frequency = <27000000>, | |
60 | <32768>; | |
61 | cpu-offset = <0x40000>; | |
62 | }; | |
cc60a1a4 | 63 | |
66a6c317 KG |
64 | msmgpio: gpio@800000 { |
65 | compatible = "qcom,msm-gpio"; | |
66 | reg = <0x00800000 0x4000>; | |
67 | gpio-controller; | |
68 | #gpio-cells = <2>; | |
69 | ngpio = <173>; | |
70 | interrupts = <0 16 0x4>; | |
71 | interrupt-controller; | |
72 | #interrupt-cells = <2>; | |
73 | }; | |
cc60a1a4 | 74 | |
66a6c317 KG |
75 | gcc: clock-controller@900000 { |
76 | compatible = "qcom,gcc-msm8660"; | |
77 | #clock-cells = <1>; | |
78 | #reset-cells = <1>; | |
79 | reg = <0x900000 0x4000>; | |
80 | }; | |
81 | ||
82 | gsbi12: gsbi@19c00000 { | |
83 | compatible = "qcom,gsbi-v1.0.0"; | |
84 | reg = <0x19c00000 0x100>; | |
85 | clocks = <&gcc GSBI12_H_CLK>; | |
86 | clock-names = "iface"; | |
87 | #address-cells = <1>; | |
88 | #size-cells = <1>; | |
89 | ranges; | |
cc60a1a4 | 90 | |
66a6c317 KG |
91 | serial@19c40000 { |
92 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
93 | reg = <0x19c40000 0x1000>, | |
94 | <0x19c00000 0x1000>; | |
95 | interrupts = <0 195 0x0>; | |
96 | clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>; | |
97 | clock-names = "core", "iface"; | |
98 | status = "disabled"; | |
99 | }; | |
100 | }; | |
101 | ||
102 | qcom,ssbi@500000 { | |
103 | compatible = "qcom,ssbi"; | |
104 | reg = <0x500000 0x1000>; | |
105 | qcom,controller-type = "pmic-arbiter"; | |
106 | }; | |
cc60a1a4 KG |
107 | }; |
108 | }; |