projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| cc60a1a4 KG |
1 | /dts-v1/; |
| 2 | ||
| 3 | /include/ "skeleton.dtsi" | |
| 4 | ||
| 5 | #include <dt-bindings/clock/qcom,gcc-msm8960.h> | |
| 665c9c03 | 6 | #include <dt-bindings/soc/qcom,gsbi.h> |
| cc60a1a4 KG |
7 | |
| 8 | / { | |
| 9 | model = "Qualcomm MSM8960"; | |
| 10 | compatible = "qcom,msm8960"; | |
| 11 | interrupt-parent = <&intc>; | |
| 12 | ||
| 2ab27991 RV |
13 | cpus { |
| 14 | #address-cells = <1>; | |
| 15 | #size-cells = <0>; | |
| 16 | interrupts = <1 14 0x304>; | |
| 2ab27991 RV |
17 | |
| 18 | cpu@0 { | |
| 665c9c03 KG |
19 | compatible = "qcom,krait"; |
| 20 | enable-method = "qcom,kpss-acc-v1"; | |
| 2ab27991 RV |
21 | device_type = "cpu"; |
| 22 | reg = <0>; | |
| 23 | next-level-cache = <&L2>; | |
| 24 | qcom,acc = <&acc0>; | |
| 25 | qcom,saw = <&saw0>; | |
| 26 | }; | |
| 27 | ||
| 28 | cpu@1 { | |
| 665c9c03 KG |
29 | compatible = "qcom,krait"; |
| 30 | enable-method = "qcom,kpss-acc-v1"; | |
| 2ab27991 RV |
31 | device_type = "cpu"; |
| 32 | reg = <1>; | |
| 33 | next-level-cache = <&L2>; | |
| 34 | qcom,acc = <&acc1>; | |
| 35 | qcom,saw = <&saw1>; | |
| 36 | }; | |
| 37 | ||
| 38 | L2: l2-cache { | |
| 39 | compatible = "cache"; | |
| 40 | cache-level = <2>; | |
| 2ab27991 RV |
41 | }; |
| 42 | }; | |
| 43 | ||
| 3bff5474 SB |
44 | cpu-pmu { |
| 45 | compatible = "qcom,krait-pmu"; | |
| 46 | interrupts = <1 10 0x304>; | |
| 47 | qcom,no-pc-write; | |
| 48 | }; | |
| 49 | ||
| 665c9c03 KG |
50 | soc: soc { |
| 51 | #address-cells = <1>; | |
| 52 | #size-cells = <1>; | |
| 53 | ranges; | |
| 54 | compatible = "simple-bus"; | |
| 55 | ||
| 56 | intc: interrupt-controller@2000000 { | |
| 57 | compatible = "qcom,msm-qgic2"; | |
| 58 | interrupt-controller; | |
| 59 | #interrupt-cells = <3>; | |
| 60 | reg = <0x02000000 0x1000>, | |
| 61 | <0x02002000 0x1000>; | |
| 62 | }; | |
| cc60a1a4 | 63 | |
| 665c9c03 KG |
64 | timer@200a000 { |
| 65 | compatible = "qcom,kpss-timer", "qcom,msm-timer"; | |
| 66 | interrupts = <1 1 0x301>, | |
| 67 | <1 2 0x301>, | |
| 68 | <1 3 0x301>; | |
| 69 | reg = <0x0200a000 0x100>; | |
| 70 | clock-frequency = <27000000>, | |
| 71 | <32768>; | |
| 72 | cpu-offset = <0x80000>; | |
| 73 | }; | |
| cc60a1a4 | 74 | |
| 665c9c03 KG |
75 | msmgpio: gpio@800000 { |
| 76 | compatible = "qcom,msm-gpio"; | |
| 77 | gpio-controller; | |
| 78 | #gpio-cells = <2>; | |
| 79 | ngpio = <150>; | |
| 80 | interrupts = <0 16 0x4>; | |
| 81 | interrupt-controller; | |
| 82 | #interrupt-cells = <2>; | |
| 83 | reg = <0x800000 0x4000>; | |
| 84 | }; | |
| cc60a1a4 | 85 | |
| 665c9c03 KG |
86 | gcc: clock-controller@900000 { |
| 87 | compatible = "qcom,gcc-msm8960"; | |
| 88 | #clock-cells = <1>; | |
| 89 | #reset-cells = <1>; | |
| 90 | reg = <0x900000 0x4000>; | |
| 91 | }; | |
| cc60a1a4 | 92 | |
| 665c9c03 KG |
93 | clock-controller@4000000 { |
| 94 | compatible = "qcom,mmcc-msm8960"; | |
| 95 | reg = <0x4000000 0x1000>; | |
| 96 | #clock-cells = <1>; | |
| 97 | #reset-cells = <1>; | |
| 98 | }; | |
| cc60a1a4 | 99 | |
| 665c9c03 KG |
100 | acc0: clock-controller@2088000 { |
| 101 | compatible = "qcom,kpss-acc-v1"; | |
| 102 | reg = <0x02088000 0x1000>, <0x02008000 0x1000>; | |
| 103 | }; | |
| 2ab27991 | 104 | |
| 665c9c03 KG |
105 | acc1: clock-controller@2098000 { |
| 106 | compatible = "qcom,kpss-acc-v1"; | |
| 107 | reg = <0x02098000 0x1000>, <0x02008000 0x1000>; | |
| 108 | }; | |
| 2ab27991 | 109 | |
| 665c9c03 KG |
110 | saw0: regulator@2089000 { |
| 111 | compatible = "qcom,saw2"; | |
| 112 | reg = <0x02089000 0x1000>, <0x02009000 0x1000>; | |
| 113 | regulator; | |
| 114 | }; | |
| 2ab27991 | 115 | |
| 665c9c03 KG |
116 | saw1: regulator@2099000 { |
| 117 | compatible = "qcom,saw2"; | |
| 118 | reg = <0x02099000 0x1000>, <0x02009000 0x1000>; | |
| 119 | regulator; | |
| 120 | }; | |
| 2ab27991 | 121 | |
| 665c9c03 KG |
122 | gsbi5: gsbi@16400000 { |
| 123 | compatible = "qcom,gsbi-v1.0.0"; | |
| 124 | reg = <0x16400000 0x100>; | |
| 125 | clocks = <&gcc GSBI5_H_CLK>; | |
| 126 | clock-names = "iface"; | |
| 127 | #address-cells = <1>; | |
| 128 | #size-cells = <1>; | |
| 129 | ranges; | |
| 130 | ||
| 131 | serial@16440000 { | |
| 132 | compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; | |
| 133 | reg = <0x16440000 0x1000>, | |
| 134 | <0x16400000 0x1000>; | |
| 135 | interrupts = <0 154 0x0>; | |
| 136 | clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>; | |
| 137 | clock-names = "core", "iface"; | |
| 138 | status = "disabled"; | |
| 139 | }; | |
| 140 | }; | |
| cc60a1a4 | 141 | |
| 665c9c03 KG |
142 | qcom,ssbi@500000 { |
| 143 | compatible = "qcom,ssbi"; | |
| 144 | reg = <0x500000 0x1000>; | |
| 145 | qcom,controller-type = "pmic-arbiter"; | |
| 146 | }; | |
| 5a229c2a | 147 | |
| 665c9c03 KG |
148 | rng@1a500000 { |
| 149 | compatible = "qcom,prng"; | |
| 150 | reg = <0x1a500000 0x200>; | |
| 151 | clocks = <&gcc PRNG_CLK>; | |
| 152 | clock-names = "core"; | |
| 153 | }; | |
| 5a229c2a | 154 | }; |
| cc60a1a4 | 155 | }; |