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eccf0607 MD |
1 | /* |
2 | * Device Tree Source for the r8a73a4 SoC | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * Copyright (C) 2013 Magnus Damm | |
6 | * | |
7 | * This file is licensed under the terms of the GNU General Public License | |
8 | * version 2. This program is licensed "as is" without any warranty of any | |
9 | * kind, whether express or implied. | |
10 | */ | |
11 | ||
a76809a3 | 12 | #include <dt-bindings/clock/r8a73a4-clock.h> |
5f75e73c LP |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
14 | #include <dt-bindings/interrupt-controller/irq.h> | |
15 | ||
eccf0607 MD |
16 | / { |
17 | compatible = "renesas,r8a73a4"; | |
18 | interrupt-parent = <&gic>; | |
26a0d2d4 TY |
19 | #address-cells = <2>; |
20 | #size-cells = <2>; | |
eccf0607 MD |
21 | |
22 | cpus { | |
23 | #address-cells = <1>; | |
24 | #size-cells = <0>; | |
25 | ||
26 | cpu0: cpu@0 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a15"; | |
29 | reg = <0>; | |
30 | clock-frequency = <1500000000>; | |
7b9ad9a0 | 31 | power-domains = <&pd_a2sl>; |
c86a4b62 | 32 | next-level-cache = <&L2_CA15>; |
eccf0607 | 33 | }; |
b0da45c6 GU |
34 | |
35 | L2_CA15: cache-controller@0 { | |
36 | compatible = "cache"; | |
37 | reg = <0>; | |
38 | clocks = <&cpg_clocks R8A73A4_CLK_Z>; | |
39 | power-domains = <&pd_a3sm>; | |
40 | cache-unified; | |
41 | cache-level = <2>; | |
42 | }; | |
43 | ||
44 | L2_CA7: cache-controller@100 { | |
45 | compatible = "cache"; | |
46 | reg = <0x100>; | |
47 | clocks = <&cpg_clocks R8A73A4_CLK_Z2>; | |
48 | power-domains = <&pd_a3km>; | |
49 | cache-unified; | |
50 | cache-level = <2>; | |
51 | }; | |
eccf0607 MD |
52 | }; |
53 | ||
7b9ad9a0 GU |
54 | ptm { |
55 | compatible = "arm,coresight-etm3x"; | |
56 | power-domains = <&pd_d4>; | |
57 | }; | |
58 | ||
eccf0607 MD |
59 | timer { |
60 | compatible = "arm,armv7-timer"; | |
4d5746a3 SH |
61 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
62 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
63 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
64 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
eccf0607 | 65 | }; |
984ca295 | 66 | |
35dd549c GU |
67 | dbsc1: memory-controller@e6790000 { |
68 | compatible = "renesas,dbsc-r8a73a4"; | |
69 | reg = <0 0xe6790000 0 0x10000>; | |
7b9ad9a0 | 70 | power-domains = <&pd_a3bc>; |
35dd549c GU |
71 | }; |
72 | ||
73 | dbsc2: memory-controller@e67a0000 { | |
74 | compatible = "renesas,dbsc-r8a73a4"; | |
75 | reg = <0 0xe67a0000 0 0x10000>; | |
7b9ad9a0 | 76 | power-domains = <&pd_a3bc>; |
35dd549c GU |
77 | }; |
78 | ||
7300505a UH |
79 | dmac: dma-multiplexer { |
80 | compatible = "renesas,shdma-mux"; | |
81 | #dma-cells = <1>; | |
82 | dma-channels = <20>; | |
83 | dma-requests = <256>; | |
84 | #address-cells = <2>; | |
85 | #size-cells = <2>; | |
86 | ranges; | |
87 | ||
88 | dma0: dma-controller@e6700020 { | |
89 | compatible = "renesas,shdma-r8a73a4"; | |
90 | reg = <0 0xe6700020 0 0x89e0>; | |
4d5746a3 SH |
91 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
92 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
93 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
94 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
95 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
96 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
97 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
98 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
99 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
100 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
101 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
102 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
103 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
104 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
105 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
106 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH | |
107 | GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH | |
108 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
109 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
110 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
111 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; | |
7300505a UH |
112 | interrupt-names = "error", |
113 | "ch0", "ch1", "ch2", "ch3", | |
114 | "ch4", "ch5", "ch6", "ch7", | |
115 | "ch8", "ch9", "ch10", "ch11", | |
116 | "ch12", "ch13", "ch14", "ch15", | |
117 | "ch16", "ch17", "ch18", "ch19"; | |
662dd64f | 118 | clocks = <&mstp2_clks R8A73A4_CLK_DMAC>; |
7b9ad9a0 | 119 | power-domains = <&pd_a3sp>; |
7300505a UH |
120 | }; |
121 | }; | |
122 | ||
7300505a UH |
123 | i2c5: i2c@e60b0000 { |
124 | #address-cells = <1>; | |
125 | #size-cells = <0>; | |
7e9ad4d0 | 126 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
7300505a | 127 | reg = <0 0xe60b0000 0 0x428>; |
4d5746a3 | 128 | interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 129 | clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; |
7b9ad9a0 | 130 | power-domains = <&pd_a3sp>; |
f7b65230 SH |
131 | |
132 | status = "disabled"; | |
133 | }; | |
134 | ||
135 | cmt1: timer@e6130000 { | |
2cd823fc | 136 | compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2"; |
f7b65230 | 137 | reg = <0 0xe6130000 0 0x1004>; |
4d5746a3 | 138 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f UH |
139 | clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; |
140 | clock-names = "fck"; | |
7b9ad9a0 | 141 | power-domains = <&pd_c5>; |
f7b65230 SH |
142 | |
143 | renesas,channels-mask = <0xff>; | |
144 | ||
7300505a UH |
145 | status = "disabled"; |
146 | }; | |
147 | ||
984ca295 | 148 | irqc0: interrupt-controller@e61c0000 { |
34abee39 | 149 | compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; |
984ca295 MD |
150 | #interrupt-cells = <2>; |
151 | interrupt-controller; | |
26a0d2d4 | 152 | reg = <0 0xe61c0000 0 0x200>; |
4d5746a3 SH |
153 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
154 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
155 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
156 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
157 | <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, | |
158 | <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, | |
159 | <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, | |
160 | <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, | |
161 | <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, | |
162 | <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, | |
163 | <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, | |
164 | <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, | |
165 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
166 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
167 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
168 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
169 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
170 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, | |
171 | <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, | |
172 | <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, | |
173 | <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, | |
174 | <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, | |
175 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, | |
176 | <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, | |
177 | <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, | |
178 | <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, | |
179 | <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, | |
180 | <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, | |
181 | <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, | |
182 | <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, | |
183 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, | |
184 | <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
1c2a7eb7 | 185 | clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; |
7b9ad9a0 | 186 | power-domains = <&pd_c4>; |
984ca295 MD |
187 | }; |
188 | ||
189 | irqc1: interrupt-controller@e61c0200 { | |
34abee39 | 190 | compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; |
984ca295 MD |
191 | #interrupt-cells = <2>; |
192 | interrupt-controller; | |
26a0d2d4 | 193 | reg = <0 0xe61c0200 0 0x200>; |
4d5746a3 SH |
194 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
195 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
196 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
197 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
198 | <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, | |
199 | <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, | |
200 | <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, | |
201 | <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, | |
202 | <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, | |
203 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
204 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
205 | <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, | |
206 | <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, | |
207 | <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, | |
208 | <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, | |
209 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, | |
210 | <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, | |
211 | <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
212 | <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, | |
213 | <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, | |
214 | <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, | |
215 | <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, | |
216 | <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
217 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
218 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, | |
219 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
1c2a7eb7 | 220 | clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; |
7b9ad9a0 | 221 | power-domains = <&pd_c4>; |
984ca295 MD |
222 | }; |
223 | ||
e4ba0a9b GU |
224 | pfc: pfc@e6050000 { |
225 | compatible = "renesas,pfc-r8a73a4"; | |
226 | reg = <0 0xe6050000 0 0x9000>; | |
227 | gpio-controller; | |
228 | #gpio-cells = <2>; | |
17ccec50 GU |
229 | gpio-ranges = |
230 | <&pfc 0 0 31>, <&pfc 32 32 9>, | |
231 | <&pfc 64 64 22>, <&pfc 96 96 31>, | |
232 | <&pfc 128 128 7>, <&pfc 160 160 19>, | |
233 | <&pfc 192 192 31>, <&pfc 224 224 27>, | |
234 | <&pfc 256 256 28>, <&pfc 288 288 21>, | |
235 | <&pfc 320 320 10>; | |
e4ba0a9b GU |
236 | interrupts-extended = |
237 | <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, | |
238 | <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, | |
239 | <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, | |
240 | <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, | |
241 | <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, | |
242 | <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, | |
243 | <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, | |
244 | <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, | |
245 | <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, | |
246 | <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, | |
247 | <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, | |
248 | <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, | |
249 | <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, | |
250 | <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, | |
251 | <&irqc1 24 0>, <&irqc1 25 0>; | |
7b9ad9a0 | 252 | power-domains = <&pd_c5>; |
e4ba0a9b GU |
253 | }; |
254 | ||
c91cf2fa | 255 | thermal@e61f0000 { |
a2cfaa74 | 256 | compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; |
26a0d2d4 TY |
257 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, |
258 | <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; | |
4d5746a3 | 259 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 260 | clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; |
7b9ad9a0 | 261 | power-domains = <&pd_c5>; |
c91cf2fa | 262 | }; |
f98c1069 GL |
263 | |
264 | i2c0: i2c@e6500000 { | |
265 | #address-cells = <1>; | |
266 | #size-cells = <0>; | |
7e9ad4d0 | 267 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 268 | reg = <0 0xe6500000 0 0x428>; |
4d5746a3 | 269 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 270 | clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; |
7b9ad9a0 | 271 | power-domains = <&pd_a3sp>; |
eda3a4fa | 272 | status = "disabled"; |
f98c1069 GL |
273 | }; |
274 | ||
275 | i2c1: i2c@e6510000 { | |
276 | #address-cells = <1>; | |
277 | #size-cells = <0>; | |
7e9ad4d0 | 278 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 279 | reg = <0 0xe6510000 0 0x428>; |
4d5746a3 | 280 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 281 | clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; |
7b9ad9a0 | 282 | power-domains = <&pd_a3sp>; |
eda3a4fa | 283 | status = "disabled"; |
f98c1069 GL |
284 | }; |
285 | ||
286 | i2c2: i2c@e6520000 { | |
287 | #address-cells = <1>; | |
288 | #size-cells = <0>; | |
7e9ad4d0 | 289 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 290 | reg = <0 0xe6520000 0 0x428>; |
4d5746a3 | 291 | interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 292 | clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; |
7b9ad9a0 | 293 | power-domains = <&pd_a3sp>; |
eda3a4fa | 294 | status = "disabled"; |
f98c1069 GL |
295 | }; |
296 | ||
297 | i2c3: i2c@e6530000 { | |
298 | #address-cells = <1>; | |
299 | #size-cells = <0>; | |
7e9ad4d0 | 300 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 301 | reg = <0 0xe6530000 0 0x428>; |
4d5746a3 | 302 | interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 303 | clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; |
7b9ad9a0 | 304 | power-domains = <&pd_a3sp>; |
eda3a4fa | 305 | status = "disabled"; |
f98c1069 GL |
306 | }; |
307 | ||
308 | i2c4: i2c@e6540000 { | |
309 | #address-cells = <1>; | |
310 | #size-cells = <0>; | |
7e9ad4d0 | 311 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 312 | reg = <0 0xe6540000 0 0x428>; |
4d5746a3 | 313 | interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 314 | clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; |
7b9ad9a0 | 315 | power-domains = <&pd_a3sp>; |
eda3a4fa | 316 | status = "disabled"; |
f98c1069 GL |
317 | }; |
318 | ||
f98c1069 GL |
319 | i2c6: i2c@e6550000 { |
320 | #address-cells = <1>; | |
321 | #size-cells = <0>; | |
7e9ad4d0 | 322 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 323 | reg = <0 0xe6550000 0 0x428>; |
4d5746a3 | 324 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 325 | clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; |
7b9ad9a0 | 326 | power-domains = <&pd_a3sp>; |
eda3a4fa | 327 | status = "disabled"; |
f98c1069 GL |
328 | }; |
329 | ||
330 | i2c7: i2c@e6560000 { | |
331 | #address-cells = <1>; | |
332 | #size-cells = <0>; | |
7e9ad4d0 | 333 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 334 | reg = <0 0xe6560000 0 0x428>; |
4d5746a3 | 335 | interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 336 | clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; |
7b9ad9a0 | 337 | power-domains = <&pd_a3sp>; |
eda3a4fa | 338 | status = "disabled"; |
f98c1069 GL |
339 | }; |
340 | ||
341 | i2c8: i2c@e6570000 { | |
342 | #address-cells = <1>; | |
343 | #size-cells = <0>; | |
7e9ad4d0 | 344 | compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; |
f98c1069 | 345 | reg = <0 0xe6570000 0 0x428>; |
4d5746a3 | 346 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 347 | clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; |
7b9ad9a0 | 348 | power-domains = <&pd_a3sp>; |
94f1a03d SH |
349 | status = "disabled"; |
350 | }; | |
351 | ||
0b3a0ef6 | 352 | scifb0: serial@e6c20000 { |
94f1a03d SH |
353 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
354 | reg = <0 0xe6c20000 0 0x100>; | |
4d5746a3 | 355 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 356 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; |
d4be2f1b | 357 | clock-names = "fck"; |
7b9ad9a0 | 358 | power-domains = <&pd_a3sp>; |
94f1a03d SH |
359 | status = "disabled"; |
360 | }; | |
361 | ||
0b3a0ef6 | 362 | scifb1: serial@e6c30000 { |
94f1a03d SH |
363 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
364 | reg = <0 0xe6c30000 0 0x100>; | |
4d5746a3 | 365 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 366 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; |
d4be2f1b | 367 | clock-names = "fck"; |
7b9ad9a0 | 368 | power-domains = <&pd_a3sp>; |
94f1a03d SH |
369 | status = "disabled"; |
370 | }; | |
371 | ||
7300505a UH |
372 | scifa0: serial@e6c40000 { |
373 | compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; | |
374 | reg = <0 0xe6c40000 0 0x100>; | |
4d5746a3 | 375 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 376 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; |
d4be2f1b | 377 | clock-names = "fck"; |
7b9ad9a0 | 378 | power-domains = <&pd_a3sp>; |
7300505a UH |
379 | status = "disabled"; |
380 | }; | |
381 | ||
382 | scifa1: serial@e6c50000 { | |
383 | compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; | |
384 | reg = <0 0xe6c50000 0 0x100>; | |
4d5746a3 | 385 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 386 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; |
d4be2f1b | 387 | clock-names = "fck"; |
7b9ad9a0 | 388 | power-domains = <&pd_a3sp>; |
7300505a UH |
389 | status = "disabled"; |
390 | }; | |
391 | ||
0b3a0ef6 | 392 | scifb2: serial@e6ce0000 { |
94f1a03d SH |
393 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
394 | reg = <0 0xe6ce0000 0 0x100>; | |
4d5746a3 | 395 | interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 396 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; |
d4be2f1b | 397 | clock-names = "fck"; |
7b9ad9a0 | 398 | power-domains = <&pd_a3sp>; |
94f1a03d SH |
399 | status = "disabled"; |
400 | }; | |
401 | ||
0b3a0ef6 | 402 | scifb3: serial@e6cf0000 { |
94f1a03d SH |
403 | compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; |
404 | reg = <0 0xe6cf0000 0 0x100>; | |
4d5746a3 | 405 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 406 | clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; |
d4be2f1b | 407 | clock-names = "fck"; |
7b9ad9a0 | 408 | power-domains = <&pd_c4>; |
eda3a4fa | 409 | status = "disabled"; |
f98c1069 | 410 | }; |
369ee2db | 411 | |
43304a5f | 412 | sdhi0: sd@ee100000 { |
df1d0584 | 413 | compatible = "renesas,sdhi-r8a73a4"; |
369ee2db | 414 | reg = <0 0xee100000 0 0x100>; |
4d5746a3 | 415 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 416 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; |
7b9ad9a0 | 417 | power-domains = <&pd_a3sp>; |
369ee2db GL |
418 | cap-sd-highspeed; |
419 | status = "disabled"; | |
420 | }; | |
421 | ||
43304a5f | 422 | sdhi1: sd@ee120000 { |
df1d0584 | 423 | compatible = "renesas,sdhi-r8a73a4"; |
369ee2db | 424 | reg = <0 0xee120000 0 0x100>; |
4d5746a3 | 425 | interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 426 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; |
7b9ad9a0 | 427 | power-domains = <&pd_a3sp>; |
369ee2db GL |
428 | cap-sd-highspeed; |
429 | status = "disabled"; | |
430 | }; | |
431 | ||
43304a5f | 432 | sdhi2: sd@ee140000 { |
df1d0584 | 433 | compatible = "renesas,sdhi-r8a73a4"; |
369ee2db | 434 | reg = <0 0xee140000 0 0x100>; |
4d5746a3 | 435 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 436 | clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; |
7b9ad9a0 | 437 | power-domains = <&pd_a3sp>; |
369ee2db GL |
438 | cap-sd-highspeed; |
439 | status = "disabled"; | |
440 | }; | |
7300505a UH |
441 | |
442 | mmcif0: mmc@ee200000 { | |
443 | compatible = "renesas,sh-mmcif"; | |
444 | reg = <0 0xee200000 0 0x80>; | |
4d5746a3 | 445 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 446 | clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; |
7b9ad9a0 | 447 | power-domains = <&pd_a3sp>; |
7300505a UH |
448 | reg-io-width = <4>; |
449 | status = "disabled"; | |
450 | }; | |
451 | ||
452 | mmcif1: mmc@ee220000 { | |
453 | compatible = "renesas,sh-mmcif"; | |
454 | reg = <0 0xee220000 0 0x80>; | |
4d5746a3 | 455 | interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
662dd64f | 456 | clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; |
7b9ad9a0 | 457 | power-domains = <&pd_a3sp>; |
7300505a UH |
458 | reg-io-width = <4>; |
459 | status = "disabled"; | |
460 | }; | |
461 | ||
462 | gic: interrupt-controller@f1001000 { | |
eaec1d67 | 463 | compatible = "arm,gic-400"; |
7300505a UH |
464 | #interrupt-cells = <3>; |
465 | #address-cells = <0>; | |
466 | interrupt-controller; | |
467 | reg = <0 0xf1001000 0 0x1000>, | |
468 | <0 0xf1002000 0 0x1000>, | |
469 | <0 0xf1004000 0 0x2000>, | |
470 | <0 0xf1006000 0 0x2000>; | |
4d5746a3 | 471 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
7300505a | 472 | }; |
a76809a3 | 473 | |
271b3ad2 GU |
474 | bsc: bus@fec10000 { |
475 | compatible = "renesas,bsc-r8a73a4", "renesas,bsc", | |
476 | "simple-pm-bus"; | |
477 | #address-cells = <1>; | |
478 | #size-cells = <1>; | |
479 | ranges = <0 0 0 0x20000000>; | |
480 | reg = <0 0xfec10000 0 0x400>; | |
481 | clocks = <&zb_clk>; | |
7b9ad9a0 | 482 | power-domains = <&pd_c4>; |
271b3ad2 GU |
483 | }; |
484 | ||
a76809a3 UH |
485 | clocks { |
486 | #address-cells = <2>; | |
487 | #size-cells = <2>; | |
488 | ranges; | |
489 | ||
490 | /* External root clocks */ | |
57c75d1e | 491 | extalr_clk: extalr { |
a76809a3 UH |
492 | compatible = "fixed-clock"; |
493 | #clock-cells = <0>; | |
494 | clock-frequency = <32768>; | |
a76809a3 | 495 | }; |
57c75d1e | 496 | extal1_clk: extal1 { |
a76809a3 UH |
497 | compatible = "fixed-clock"; |
498 | #clock-cells = <0>; | |
499 | clock-frequency = <25000000>; | |
a76809a3 | 500 | }; |
57c75d1e | 501 | extal2_clk: extal2 { |
a76809a3 UH |
502 | compatible = "fixed-clock"; |
503 | #clock-cells = <0>; | |
504 | clock-frequency = <48000000>; | |
a76809a3 | 505 | }; |
57c75d1e | 506 | fsiack_clk: fsiack { |
a76809a3 UH |
507 | compatible = "fixed-clock"; |
508 | #clock-cells = <0>; | |
509 | /* This value must be overridden by the board. */ | |
510 | clock-frequency = <0>; | |
a76809a3 | 511 | }; |
57c75d1e | 512 | fsibck_clk: fsibck { |
a76809a3 UH |
513 | compatible = "fixed-clock"; |
514 | #clock-cells = <0>; | |
515 | /* This value must be overridden by the board. */ | |
516 | clock-frequency = <0>; | |
a76809a3 UH |
517 | }; |
518 | ||
519 | /* Special CPG clocks */ | |
520 | cpg_clocks: cpg_clocks@e6150000 { | |
521 | compatible = "renesas,r8a73a4-cpg-clocks"; | |
522 | reg = <0 0xe6150000 0 0x10000>; | |
523 | clocks = <&extal1_clk>, <&extal2_clk>; | |
524 | #clock-cells = <1>; | |
525 | clock-output-names = "main", "pll0", "pll1", "pll2", | |
526 | "pll2s", "pll2h", "z", "z2", | |
527 | "i", "m3", "b", "m1", "m2", | |
528 | "zx", "zs", "hp"; | |
529 | }; | |
530 | ||
531 | /* Variable factor clocks (DIV6) */ | |
532 | zb_clk: zb_clk@e6150010 { | |
533 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; | |
534 | reg = <0 0xe6150010 0 4>; | |
535 | clocks = <&pll1_div2_clk>, <0>, | |
536 | <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; | |
537 | #clock-cells = <0>; | |
538 | clock-output-names = "zb"; | |
539 | }; | |
57c75d1e | 540 | sdhi0_clk: sdhi0ck@e6150074 { |
a76809a3 UH |
541 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
542 | reg = <0 0xe6150074 0 4>; | |
543 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
544 | <0>, <&extal2_clk>; | |
545 | #clock-cells = <0>; | |
a76809a3 | 546 | }; |
57c75d1e | 547 | sdhi1_clk: sdhi1ck@e6150078 { |
a76809a3 UH |
548 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
549 | reg = <0 0xe6150078 0 4>; | |
550 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
551 | <0>, <&extal2_clk>; | |
552 | #clock-cells = <0>; | |
a76809a3 | 553 | }; |
57c75d1e | 554 | sdhi2_clk: sdhi2ck@e615007c { |
a76809a3 UH |
555 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
556 | reg = <0 0xe615007c 0 4>; | |
557 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
558 | <0>, <&extal2_clk>; | |
559 | #clock-cells = <0>; | |
a76809a3 | 560 | }; |
57c75d1e | 561 | mmc0_clk: mmc0@e6150240 { |
a76809a3 UH |
562 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
563 | reg = <0 0xe6150240 0 4>; | |
564 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
565 | <0>, <&extal2_clk>; | |
566 | #clock-cells = <0>; | |
a76809a3 | 567 | }; |
57c75d1e | 568 | mmc1_clk: mmc1@e6150244 { |
a76809a3 UH |
569 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
570 | reg = <0 0xe6150244 0 4>; | |
571 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
572 | <0>, <&extal2_clk>; | |
573 | #clock-cells = <0>; | |
a76809a3 | 574 | }; |
57c75d1e | 575 | vclk1_clk: vclk1@e6150008 { |
a76809a3 UH |
576 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
577 | reg = <0 0xe6150008 0 4>; | |
578 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
579 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
580 | <&extalr_clk>, <0>, <0>; | |
581 | #clock-cells = <0>; | |
a76809a3 | 582 | }; |
57c75d1e | 583 | vclk2_clk: vclk2@e615000c { |
a76809a3 UH |
584 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
585 | reg = <0 0xe615000c 0 4>; | |
586 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
587 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
588 | <&extalr_clk>, <0>, <0>; | |
589 | #clock-cells = <0>; | |
a76809a3 | 590 | }; |
57c75d1e | 591 | vclk3_clk: vclk3@e615001c { |
a76809a3 UH |
592 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
593 | reg = <0 0xe615001c 0 4>; | |
594 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
595 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
596 | <&extalr_clk>, <0>, <0>; | |
597 | #clock-cells = <0>; | |
a76809a3 | 598 | }; |
57c75d1e | 599 | vclk4_clk: vclk4@e6150014 { |
a76809a3 UH |
600 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
601 | reg = <0 0xe6150014 0 4>; | |
602 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
603 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
604 | <&extalr_clk>, <0>, <0>; | |
605 | #clock-cells = <0>; | |
a76809a3 | 606 | }; |
57c75d1e | 607 | vclk5_clk: vclk5@e6150034 { |
a76809a3 UH |
608 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
609 | reg = <0 0xe6150034 0 4>; | |
610 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
611 | <0>, <&extal2_clk>, <&main_div2_clk>, | |
612 | <&extalr_clk>, <0>, <0>; | |
613 | #clock-cells = <0>; | |
a76809a3 | 614 | }; |
57c75d1e | 615 | fsia_clk: fsia@e6150018 { |
a76809a3 UH |
616 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
617 | reg = <0 0xe6150018 0 4>; | |
618 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
619 | <&fsiack_clk>, <0>; | |
620 | #clock-cells = <0>; | |
a76809a3 | 621 | }; |
57c75d1e | 622 | fsib_clk: fsib@e6150090 { |
a76809a3 UH |
623 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
624 | reg = <0 0xe6150090 0 4>; | |
625 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
626 | <&fsibck_clk>, <0>; | |
627 | #clock-cells = <0>; | |
a76809a3 | 628 | }; |
57c75d1e | 629 | mp_clk: mp@e6150080 { |
a76809a3 UH |
630 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
631 | reg = <0 0xe6150080 0 4>; | |
632 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
633 | <&extal2_clk>, <&extal2_clk>; | |
634 | #clock-cells = <0>; | |
a76809a3 | 635 | }; |
57c75d1e | 636 | m4_clk: m4@e6150098 { |
a76809a3 UH |
637 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
638 | reg = <0 0xe6150098 0 4>; | |
639 | clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; | |
640 | #clock-cells = <0>; | |
a76809a3 | 641 | }; |
57c75d1e | 642 | hsi_clk: hsi@e615026c { |
a76809a3 UH |
643 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
644 | reg = <0 0xe615026c 0 4>; | |
645 | clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, | |
646 | <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; | |
647 | #clock-cells = <0>; | |
a76809a3 | 648 | }; |
57c75d1e | 649 | spuv_clk: spuv@e6150094 { |
a76809a3 UH |
650 | compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; |
651 | reg = <0 0xe6150094 0 4>; | |
652 | clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, | |
653 | <&extal2_clk>, <&extal2_clk>; | |
654 | #clock-cells = <0>; | |
a76809a3 UH |
655 | }; |
656 | ||
657 | /* Fixed factor clocks */ | |
57c75d1e | 658 | main_div2_clk: main_div2 { |
a76809a3 UH |
659 | compatible = "fixed-factor-clock"; |
660 | clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; | |
661 | #clock-cells = <0>; | |
662 | clock-div = <2>; | |
663 | clock-mult = <1>; | |
a76809a3 | 664 | }; |
57c75d1e | 665 | pll0_div2_clk: pll0_div2 { |
a76809a3 UH |
666 | compatible = "fixed-factor-clock"; |
667 | clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; | |
668 | #clock-cells = <0>; | |
669 | clock-div = <2>; | |
670 | clock-mult = <1>; | |
a76809a3 | 671 | }; |
57c75d1e | 672 | pll1_div2_clk: pll1_div2 { |
a76809a3 UH |
673 | compatible = "fixed-factor-clock"; |
674 | clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; | |
675 | #clock-cells = <0>; | |
676 | clock-div = <2>; | |
677 | clock-mult = <1>; | |
a76809a3 | 678 | }; |
57c75d1e | 679 | extal1_div2_clk: extal1_div2 { |
a76809a3 UH |
680 | compatible = "fixed-factor-clock"; |
681 | clocks = <&extal1_clk>; | |
682 | #clock-cells = <0>; | |
683 | clock-div = <2>; | |
684 | clock-mult = <1>; | |
a76809a3 UH |
685 | }; |
686 | ||
687 | /* Gate clocks */ | |
688 | mstp2_clks: mstp2_clks@e6150138 { | |
689 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
690 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
691 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
692 | <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; | |
693 | #clock-cells = <1>; | |
694 | clock-indices = < | |
695 | R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 | |
696 | R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 | |
697 | R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 | |
698 | R8A73A4_CLK_DMAC | |
699 | >; | |
700 | clock-output-names = | |
701 | "scifa0", "scifa1", "scifb0", "scifb1", | |
702 | "scifb2", "scifb3", "dmac"; | |
703 | }; | |
704 | mstp3_clks: mstp3_clks@e615013c { | |
705 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
706 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
707 | clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, | |
708 | <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, | |
709 | <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, | |
710 | <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks | |
711 | R8A73A4_CLK_HP>, <&cpg_clocks | |
712 | R8A73A4_CLK_HP>, <&extalr_clk>; | |
713 | #clock-cells = <1>; | |
714 | clock-indices = < | |
715 | R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 | |
716 | R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 | |
717 | R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 | |
718 | R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 | |
719 | R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 | |
720 | R8A73A4_CLK_CMT1 | |
721 | >; | |
722 | clock-output-names = | |
723 | "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", | |
724 | "mmcif0", "iic6", "iic7", "iic0", "iic1", | |
725 | "cmt1"; | |
726 | }; | |
727 | mstp4_clks: mstp4_clks@e6150140 { | |
728 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
729 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
1c2a7eb7 GU |
730 | clocks = <&main_div2_clk>, <&main_div2_clk>, |
731 | <&cpg_clocks R8A73A4_CLK_HP>, | |
a76809a3 UH |
732 | <&cpg_clocks R8A73A4_CLK_HP>; |
733 | #clock-cells = <1>; | |
734 | clock-indices = < | |
1c2a7eb7 GU |
735 | R8A73A4_CLK_IRQC R8A73A4_CLK_IIC5 |
736 | R8A73A4_CLK_IIC4 R8A73A4_CLK_IIC3 | |
a76809a3 UH |
737 | >; |
738 | clock-output-names = | |
1c2a7eb7 | 739 | "irqc", "iic5", "iic4", "iic3"; |
a76809a3 UH |
740 | }; |
741 | mstp5_clks: mstp5_clks@e6150144 { | |
742 | compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
743 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
744 | clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>; | |
745 | #clock-cells = <1>; | |
746 | clock-indices = < | |
747 | R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 | |
748 | >; | |
749 | clock-output-names = | |
750 | "thermal", "iic8"; | |
751 | }; | |
752 | }; | |
7b9ad9a0 GU |
753 | |
754 | sysc: system-controller@e6180000 { | |
755 | compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; | |
756 | reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; | |
757 | ||
758 | pm-domains { | |
759 | pd_c5: c5 { | |
760 | #address-cells = <1>; | |
761 | #size-cells = <0>; | |
762 | #power-domain-cells = <0>; | |
763 | ||
764 | pd_c4: c4@0 { | |
765 | reg = <0>; | |
766 | #address-cells = <1>; | |
767 | #size-cells = <0>; | |
768 | #power-domain-cells = <0>; | |
769 | ||
770 | pd_a3sg: a3sg@16 { | |
771 | reg = <16>; | |
772 | #power-domain-cells = <0>; | |
773 | }; | |
774 | ||
775 | pd_a3ex: a3ex@17 { | |
776 | reg = <17>; | |
777 | #power-domain-cells = <0>; | |
778 | }; | |
779 | ||
780 | pd_a3sp: a3sp@18 { | |
781 | reg = <18>; | |
782 | #address-cells = <1>; | |
783 | #size-cells = <0>; | |
784 | #power-domain-cells = <0>; | |
785 | ||
786 | pd_a2us: a2us@19 { | |
787 | reg = <19>; | |
788 | #power-domain-cells = <0>; | |
789 | }; | |
790 | }; | |
791 | ||
792 | pd_a3sm: a3sm@20 { | |
793 | reg = <20>; | |
794 | #address-cells = <1>; | |
795 | #size-cells = <0>; | |
796 | #power-domain-cells = <0>; | |
797 | ||
798 | pd_a2sl: a2sl@21 { | |
799 | reg = <21>; | |
800 | #power-domain-cells = <0>; | |
801 | }; | |
802 | }; | |
803 | ||
804 | pd_a3km: a3km@22 { | |
805 | reg = <22>; | |
806 | #address-cells = <1>; | |
807 | #size-cells = <0>; | |
808 | #power-domain-cells = <0>; | |
809 | ||
810 | pd_a2kl: a2kl@23 { | |
811 | reg = <23>; | |
812 | #power-domain-cells = <0>; | |
813 | }; | |
814 | }; | |
815 | }; | |
816 | ||
817 | pd_c4ma: c4ma@1 { | |
818 | reg = <1>; | |
819 | #power-domain-cells = <0>; | |
820 | }; | |
821 | ||
822 | pd_c4cl: c4cl@2 { | |
823 | reg = <2>; | |
824 | #power-domain-cells = <0>; | |
825 | }; | |
826 | ||
827 | pd_d4: d4@3 { | |
828 | reg = <3>; | |
829 | #power-domain-cells = <0>; | |
830 | }; | |
831 | ||
832 | pd_a4bc: a4bc@4 { | |
833 | reg = <4>; | |
834 | #address-cells = <1>; | |
835 | #size-cells = <0>; | |
836 | #power-domain-cells = <0>; | |
837 | ||
838 | pd_a3bc: a3bc@5 { | |
839 | reg = <5>; | |
840 | #power-domain-cells = <0>; | |
841 | }; | |
842 | }; | |
843 | ||
844 | pd_a4l: a4l@6 { | |
845 | reg = <6>; | |
846 | #power-domain-cells = <0>; | |
847 | }; | |
848 | ||
849 | pd_a4lc: a4lc@7 { | |
850 | reg = <7>; | |
851 | #power-domain-cells = <0>; | |
852 | }; | |
853 | ||
854 | pd_a4mp: a4mp@8 { | |
855 | reg = <8>; | |
856 | #address-cells = <1>; | |
857 | #size-cells = <0>; | |
858 | #power-domain-cells = <0>; | |
859 | ||
860 | pd_a3mp: a3mp@9 { | |
861 | reg = <9>; | |
862 | #power-domain-cells = <0>; | |
863 | }; | |
864 | ||
865 | pd_a3vc: a3vc@10 { | |
866 | reg = <10>; | |
867 | #power-domain-cells = <0>; | |
868 | }; | |
869 | }; | |
870 | ||
871 | pd_a4sf: a4sf@11 { | |
872 | reg = <11>; | |
873 | #power-domain-cells = <0>; | |
874 | }; | |
875 | ||
876 | pd_a3r: a3r@12 { | |
877 | reg = <12>; | |
878 | #address-cells = <1>; | |
879 | #size-cells = <0>; | |
880 | #power-domain-cells = <0>; | |
881 | ||
882 | pd_a2rv: a2rv@13 { | |
883 | reg = <13>; | |
884 | #power-domain-cells = <0>; | |
885 | }; | |
886 | ||
887 | pd_a2is: a2is@14 { | |
888 | reg = <14>; | |
889 | #power-domain-cells = <0>; | |
890 | }; | |
891 | }; | |
892 | }; | |
893 | }; | |
894 | }; | |
eccf0607 | 895 | }; |