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ARM: shmobile: ape6evm dts: Move Ethernet node to BSC
[deliverable/linux.git] / arch / arm / boot / dts / r8a73a4.dtsi
CommitLineData
eccf0607
MD		 1/*
2 * Device Tree Source for the r8a73a4 SoC
3 *
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Magnus Damm
6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
a76809a3 12#include <dt-bindings/clock/r8a73a4-clock.h>
5f75e73c
LP		 13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
eccf0607
MD		 16/ {
17 compatible = "renesas,r8a73a4";
18 interrupt-parent = <&gic>;
26a0d2d4
TY		 19 #address-cells = <2>;
20 #size-cells = <2>;
eccf0607
MD		 21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 cpu0: cpu@0 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a15";
29 reg = <0>;
30 clock-frequency = <1500000000>;
31 };
32 };
33
eccf0607
MD		 34 timer {
35 compatible = "arm,armv7-timer";
5f75e73c
LP		 36 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
37 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
38 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
39 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
eccf0607 40 };
984ca295 41
35dd549c
GU		 42 dbsc1: memory-controller@e6790000 {
43 compatible = "renesas,dbsc-r8a73a4";
44 reg = <0 0xe6790000 0 0x10000>;
45 };
46
47 dbsc2: memory-controller@e67a0000 {
48 compatible = "renesas,dbsc-r8a73a4";
49 reg = <0 0xe67a0000 0 0x10000>;
50 };
51
7300505a
UH		 52 dmac: dma-multiplexer {
53 compatible = "renesas,shdma-mux";
54 #dma-cells = <1>;
55 dma-channels = <20>;
56 dma-requests = <256>;
57 #address-cells = <2>;
58 #size-cells = <2>;
59 ranges;
60
61 dma0: dma-controller@e6700020 {
62 compatible = "renesas,shdma-r8a73a4";
63 reg = <0 0xe6700020 0 0x89e0>;
64 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
65 0 200 IRQ_TYPE_LEVEL_HIGH
66 0 201 IRQ_TYPE_LEVEL_HIGH
67 0 202 IRQ_TYPE_LEVEL_HIGH
68 0 203 IRQ_TYPE_LEVEL_HIGH
69 0 204 IRQ_TYPE_LEVEL_HIGH
70 0 205 IRQ_TYPE_LEVEL_HIGH
71 0 206 IRQ_TYPE_LEVEL_HIGH
72 0 207 IRQ_TYPE_LEVEL_HIGH
73 0 208 IRQ_TYPE_LEVEL_HIGH
74 0 209 IRQ_TYPE_LEVEL_HIGH
75 0 210 IRQ_TYPE_LEVEL_HIGH
76 0 211 IRQ_TYPE_LEVEL_HIGH
77 0 212 IRQ_TYPE_LEVEL_HIGH
78 0 213 IRQ_TYPE_LEVEL_HIGH
79 0 214 IRQ_TYPE_LEVEL_HIGH
80 0 215 IRQ_TYPE_LEVEL_HIGH
81 0 216 IRQ_TYPE_LEVEL_HIGH
82 0 217 IRQ_TYPE_LEVEL_HIGH
83 0 218 IRQ_TYPE_LEVEL_HIGH
84 0 219 IRQ_TYPE_LEVEL_HIGH>;
85 interrupt-names = "error",
86 "ch0", "ch1", "ch2", "ch3",
87 "ch4", "ch5", "ch6", "ch7",
88 "ch8", "ch9", "ch10", "ch11",
89 "ch12", "ch13", "ch14", "ch15",
90 "ch16", "ch17", "ch18", "ch19";
662dd64f 91 clocks = <&mstp2_clks R8A73A4_CLK_DMAC>;
7300505a
UH		 92 };
93 };
94
95 pfc: pfc@e6050000 {
96 compatible = "renesas,pfc-r8a73a4";
97 reg = <0 0xe6050000 0 0x9000>;
98 gpio-controller;
99 #gpio-cells = <2>;
100 interrupts-extended =
101 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>,
102 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>,
103 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>,
104 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>,
105 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>,
106 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>,
107 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>,
108 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>,
109 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>,
110 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>,
111 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>,
112 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>,
113 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>,
114 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>,
115 <&irqc1 24 0>, <&irqc1 25 0>;
116 };
117
118 i2c5: i2c@e60b0000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
7e9ad4d0 121 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
7300505a
UH		 122 reg = <0 0xe60b0000 0 0x428>;
123 interrupts = <0 179 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 124 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>;
f7b65230
SH		 125
126 status = "disabled";
127 };
128
129 cmt1: timer@e6130000 {
2cd823fc 130 compatible = "renesas,cmt-48-r8a73a4", "renesas,cmt-48-gen2";
f7b65230
SH		 131 reg = <0 0xe6130000 0 0x1004>;
132 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 133 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>;
134 clock-names = "fck";
f7b65230
SH		 135
136 renesas,channels-mask = <0xff>;
137
7300505a
UH		 138 status = "disabled";
139 };
140
984ca295 141 irqc0: interrupt-controller@e61c0000 {
34abee39 142 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
984ca295
MD		 143 #interrupt-cells = <2>;
144 interrupt-controller;
26a0d2d4 145 reg = <0 0xe61c0000 0 0x200>;
5f75e73c
LP		 146 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
147 <0 1 IRQ_TYPE_LEVEL_HIGH>,
148 <0 2 IRQ_TYPE_LEVEL_HIGH>,
149 <0 3 IRQ_TYPE_LEVEL_HIGH>,
150 <0 4 IRQ_TYPE_LEVEL_HIGH>,
151 <0 5 IRQ_TYPE_LEVEL_HIGH>,
152 <0 6 IRQ_TYPE_LEVEL_HIGH>,
153 <0 7 IRQ_TYPE_LEVEL_HIGH>,
154 <0 8 IRQ_TYPE_LEVEL_HIGH>,
155 <0 9 IRQ_TYPE_LEVEL_HIGH>,
156 <0 10 IRQ_TYPE_LEVEL_HIGH>,
157 <0 11 IRQ_TYPE_LEVEL_HIGH>,
158 <0 12 IRQ_TYPE_LEVEL_HIGH>,
159 <0 13 IRQ_TYPE_LEVEL_HIGH>,
160 <0 14 IRQ_TYPE_LEVEL_HIGH>,
161 <0 15 IRQ_TYPE_LEVEL_HIGH>,
162 <0 16 IRQ_TYPE_LEVEL_HIGH>,
163 <0 17 IRQ_TYPE_LEVEL_HIGH>,
164 <0 18 IRQ_TYPE_LEVEL_HIGH>,
165 <0 19 IRQ_TYPE_LEVEL_HIGH>,
166 <0 20 IRQ_TYPE_LEVEL_HIGH>,
167 <0 21 IRQ_TYPE_LEVEL_HIGH>,
168 <0 22 IRQ_TYPE_LEVEL_HIGH>,
169 <0 23 IRQ_TYPE_LEVEL_HIGH>,
170 <0 24 IRQ_TYPE_LEVEL_HIGH>,
171 <0 25 IRQ_TYPE_LEVEL_HIGH>,
172 <0 26 IRQ_TYPE_LEVEL_HIGH>,
173 <0 27 IRQ_TYPE_LEVEL_HIGH>,
174 <0 28 IRQ_TYPE_LEVEL_HIGH>,
175 <0 29 IRQ_TYPE_LEVEL_HIGH>,
176 <0 30 IRQ_TYPE_LEVEL_HIGH>,
177 <0 31 IRQ_TYPE_LEVEL_HIGH>;
984ca295
MD		 178 };
179
180 irqc1: interrupt-controller@e61c0200 {
34abee39 181 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
984ca295
MD		 182 #interrupt-cells = <2>;
183 interrupt-controller;
26a0d2d4 184 reg = <0 0xe61c0200 0 0x200>;
5f75e73c
LP		 185 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
186 <0 33 IRQ_TYPE_LEVEL_HIGH>,
187 <0 34 IRQ_TYPE_LEVEL_HIGH>,
188 <0 35 IRQ_TYPE_LEVEL_HIGH>,
189 <0 36 IRQ_TYPE_LEVEL_HIGH>,
190 <0 37 IRQ_TYPE_LEVEL_HIGH>,
191 <0 38 IRQ_TYPE_LEVEL_HIGH>,
192 <0 39 IRQ_TYPE_LEVEL_HIGH>,
193 <0 40 IRQ_TYPE_LEVEL_HIGH>,
194 <0 41 IRQ_TYPE_LEVEL_HIGH>,
195 <0 42 IRQ_TYPE_LEVEL_HIGH>,
196 <0 43 IRQ_TYPE_LEVEL_HIGH>,
197 <0 44 IRQ_TYPE_LEVEL_HIGH>,
198 <0 45 IRQ_TYPE_LEVEL_HIGH>,
199 <0 46 IRQ_TYPE_LEVEL_HIGH>,
200 <0 47 IRQ_TYPE_LEVEL_HIGH>,
201 <0 48 IRQ_TYPE_LEVEL_HIGH>,
202 <0 49 IRQ_TYPE_LEVEL_HIGH>,
203 <0 50 IRQ_TYPE_LEVEL_HIGH>,
204 <0 51 IRQ_TYPE_LEVEL_HIGH>,
205 <0 52 IRQ_TYPE_LEVEL_HIGH>,
206 <0 53 IRQ_TYPE_LEVEL_HIGH>,
207 <0 54 IRQ_TYPE_LEVEL_HIGH>,
208 <0 55 IRQ_TYPE_LEVEL_HIGH>,
209 <0 56 IRQ_TYPE_LEVEL_HIGH>,
210 <0 57 IRQ_TYPE_LEVEL_HIGH>;
984ca295
MD		 211 };
212
c91cf2fa 213 thermal@e61f0000 {
a2cfaa74 214 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
26a0d2d4
TY		 215 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>,
216 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>;
5f75e73c 217 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 218 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>;
c91cf2fa 219 };
f98c1069
GL		 220
221 i2c0: i2c@e6500000 {
222 #address-cells = <1>;
223 #size-cells = <0>;
7e9ad4d0 224 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 225 reg = <0 0xe6500000 0 0x428>;
d6dd1313 226 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 227 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>;
eda3a4fa 228 status = "disabled";
f98c1069
GL		 229 };
230
231 i2c1: i2c@e6510000 {
232 #address-cells = <1>;
233 #size-cells = <0>;
7e9ad4d0 234 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 235 reg = <0 0xe6510000 0 0x428>;
d6dd1313 236 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 237 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>;
eda3a4fa 238 status = "disabled";
f98c1069
GL		 239 };
240
241 i2c2: i2c@e6520000 {
242 #address-cells = <1>;
243 #size-cells = <0>;
7e9ad4d0 244 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 245 reg = <0 0xe6520000 0 0x428>;
d6dd1313 246 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 247 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>;
eda3a4fa 248 status = "disabled";
f98c1069
GL		 249 };
250
251 i2c3: i2c@e6530000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
7e9ad4d0 254 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 255 reg = <0 0xe6530000 0 0x428>;
d6dd1313 256 interrupts = <0 177 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 257 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>;
eda3a4fa 258 status = "disabled";
f98c1069
GL		 259 };
260
261 i2c4: i2c@e6540000 {
262 #address-cells = <1>;
263 #size-cells = <0>;
7e9ad4d0 264 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 265 reg = <0 0xe6540000 0 0x428>;
5f75e73c 266 interrupts = <0 178 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 267 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>;
eda3a4fa 268 status = "disabled";
f98c1069
GL		 269 };
270
f98c1069
GL		 271 i2c6: i2c@e6550000 {
272 #address-cells = <1>;
273 #size-cells = <0>;
7e9ad4d0 274 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 275 reg = <0 0xe6550000 0 0x428>;
5f75e73c 276 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 277 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>;
eda3a4fa 278 status = "disabled";
f98c1069
GL		 279 };
280
281 i2c7: i2c@e6560000 {
282 #address-cells = <1>;
283 #size-cells = <0>;
7e9ad4d0 284 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 285 reg = <0 0xe6560000 0 0x428>;
5f75e73c 286 interrupts = <0 185 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 287 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>;
eda3a4fa 288 status = "disabled";
f98c1069
GL		 289 };
290
291 i2c8: i2c@e6570000 {
292 #address-cells = <1>;
293 #size-cells = <0>;
7e9ad4d0 294 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
f98c1069 295 reg = <0 0xe6570000 0 0x428>;
5f75e73c 296 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 297 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>;
94f1a03d
SH		 298 status = "disabled";
299 };
300
0b3a0ef6 301 scifb0: serial@e6c20000 {
94f1a03d
SH		 302 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
303 reg = <0 0xe6c20000 0 0x100>;
304 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 305 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>;
306 clock-names = "sci_ick";
94f1a03d
SH		 307 status = "disabled";
308 };
309
0b3a0ef6 310 scifb1: serial@e6c30000 {
94f1a03d
SH		 311 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
312 reg = <0 0xe6c30000 0 0x100>;
313 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 314 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>;
315 clock-names = "sci_ick";
94f1a03d
SH		 316 status = "disabled";
317 };
318
7300505a
UH		 319 scifa0: serial@e6c40000 {
320 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
321 reg = <0 0xe6c40000 0 0x100>;
322 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 323 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>;
324 clock-names = "sci_ick";
7300505a
UH		 325 status = "disabled";
326 };
327
328 scifa1: serial@e6c50000 {
329 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
330 reg = <0 0xe6c50000 0 0x100>;
331 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 332 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>;
333 clock-names = "sci_ick";
7300505a
UH		 334 status = "disabled";
335 };
336
0b3a0ef6 337 scifb2: serial@e6ce0000 {
94f1a03d
SH		 338 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
339 reg = <0 0xe6ce0000 0 0x100>;
340 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 341 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>;
342 clock-names = "sci_ick";
94f1a03d
SH		 343 status = "disabled";
344 };
345
0b3a0ef6 346 scifb3: serial@e6cf0000 {
94f1a03d
SH		 347 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
348 reg = <0 0xe6cf0000 0 0x100>;
349 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
662dd64f
UH		 350 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>;
351 clock-names = "sci_ick";
eda3a4fa 352 status = "disabled";
f98c1069 353 };
369ee2db 354
43304a5f 355 sdhi0: sd@ee100000 {
df1d0584 356 compatible = "renesas,sdhi-r8a73a4";
369ee2db 357 reg = <0 0xee100000 0 0x100>;
5f75e73c 358 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 359 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>;
369ee2db
GL		 360 cap-sd-highspeed;
361 status = "disabled";
362 };
363
43304a5f 364 sdhi1: sd@ee120000 {
df1d0584 365 compatible = "renesas,sdhi-r8a73a4";
369ee2db 366 reg = <0 0xee120000 0 0x100>;
5f75e73c 367 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 368 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>;
369ee2db
GL		 369 cap-sd-highspeed;
370 status = "disabled";
371 };
372
43304a5f 373 sdhi2: sd@ee140000 {
df1d0584 374 compatible = "renesas,sdhi-r8a73a4";
369ee2db 375 reg = <0 0xee140000 0 0x100>;
5f75e73c 376 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 377 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>;
369ee2db
GL		 378 cap-sd-highspeed;
379 status = "disabled";
380 };
7300505a
UH		 381
382 mmcif0: mmc@ee200000 {
383 compatible = "renesas,sh-mmcif";
384 reg = <0 0xee200000 0 0x80>;
385 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 386 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>;
7300505a
UH		 387 reg-io-width = <4>;
388 status = "disabled";
389 };
390
391 mmcif1: mmc@ee220000 {
392 compatible = "renesas,sh-mmcif";
393 reg = <0 0xee220000 0 0x80>;
394 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
662dd64f 395 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>;
7300505a
UH		 396 reg-io-width = <4>;
397 status = "disabled";
398 };
399
400 gic: interrupt-controller@f1001000 {
401 compatible = "arm,cortex-a15-gic";
402 #interrupt-cells = <3>;
403 #address-cells = <0>;
404 interrupt-controller;
405 reg = <0 0xf1001000 0 0x1000>,
406 <0 0xf1002000 0 0x1000>,
407 <0 0xf1004000 0 0x2000>,
408 <0 0xf1006000 0 0x2000>;
409 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
410 };
a76809a3 411
271b3ad2
GU		 412 bsc: bus@fec10000 {
413 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
414 "simple-pm-bus";
415 #address-cells = <1>;
416 #size-cells = <1>;
417 ranges = <0 0 0 0x20000000>;
418 reg = <0 0xfec10000 0 0x400>;
419 clocks = <&zb_clk>;
420 };
421
a76809a3
UH		 422 clocks {
423 #address-cells = <2>;
424 #size-cells = <2>;
425 ranges;
426
427 /* External root clocks */
428 extalr_clk: extalr_clk {
429 compatible = "fixed-clock";
430 #clock-cells = <0>;
431 clock-frequency = <32768>;
432 clock-output-names = "extalr";
433 };
434 extal1_clk: extal1_clk {
435 compatible = "fixed-clock";
436 #clock-cells = <0>;
437 clock-frequency = <25000000>;
438 clock-output-names = "extal1";
439 };
440 extal2_clk: extal2_clk {
441 compatible = "fixed-clock";
442 #clock-cells = <0>;
443 clock-frequency = <48000000>;
444 clock-output-names = "extal2";
445 };
446 fsiack_clk: fsiack_clk {
447 compatible = "fixed-clock";
448 #clock-cells = <0>;
449 /* This value must be overridden by the board. */
450 clock-frequency = <0>;
451 clock-output-names = "fsiack";
452 };
453 fsibck_clk: fsibck_clk {
454 compatible = "fixed-clock";
455 #clock-cells = <0>;
456 /* This value must be overridden by the board. */
457 clock-frequency = <0>;
458 clock-output-names = "fsibck";
459 };
460
461 /* Special CPG clocks */
462 cpg_clocks: cpg_clocks@e6150000 {
463 compatible = "renesas,r8a73a4-cpg-clocks";
464 reg = <0 0xe6150000 0 0x10000>;
465 clocks = <&extal1_clk>, <&extal2_clk>;
466 #clock-cells = <1>;
467 clock-output-names = "main", "pll0", "pll1", "pll2",
468 "pll2s", "pll2h", "z", "z2",
469 "i", "m3", "b", "m1", "m2",
470 "zx", "zs", "hp";
471 };
472
473 /* Variable factor clocks (DIV6) */
474 zb_clk: zb_clk@e6150010 {
475 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
476 reg = <0 0xe6150010 0 4>;
477 clocks = <&pll1_div2_clk>, <0>,
478 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
479 #clock-cells = <0>;
480 clock-output-names = "zb";
481 };
482 sdhi0_clk: sdhi0_clk@e6150074 {
483 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
484 reg = <0 0xe6150074 0 4>;
485 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
486 <0>, <&extal2_clk>;
487 #clock-cells = <0>;
488 clock-output-names = "sdhi0ck";
489 };
490 sdhi1_clk: sdhi1_clk@e6150078 {
491 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
492 reg = <0 0xe6150078 0 4>;
493 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
494 <0>, <&extal2_clk>;
495 #clock-cells = <0>;
496 clock-output-names = "sdhi1ck";
497 };
498 sdhi2_clk: sdhi2_clk@e615007c {
499 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
500 reg = <0 0xe615007c 0 4>;
501 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
502 <0>, <&extal2_clk>;
503 #clock-cells = <0>;
504 clock-output-names = "sdhi2ck";
505 };
506 mmc0_clk: mmc0_clk@e6150240 {
507 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
508 reg = <0 0xe6150240 0 4>;
509 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
510 <0>, <&extal2_clk>;
511 #clock-cells = <0>;
512 clock-output-names = "mmc0";
513 };
514 mmc1_clk: mmc1_clk@e6150244 {
515 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
516 reg = <0 0xe6150244 0 4>;
517 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
518 <0>, <&extal2_clk>;
519 #clock-cells = <0>;
520 clock-output-names = "mmc1";
521 };
522 vclk1_clk: vclk1_clk@e6150008 {
523 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
524 reg = <0 0xe6150008 0 4>;
525 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
526 <0>, <&extal2_clk>, <&main_div2_clk>,
527 <&extalr_clk>, <0>, <0>;
528 #clock-cells = <0>;
529 clock-output-names = "vclk1";
530 };
531 vclk2_clk: vclk2_clk@e615000c {
532 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
533 reg = <0 0xe615000c 0 4>;
534 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
535 <0>, <&extal2_clk>, <&main_div2_clk>,
536 <&extalr_clk>, <0>, <0>;
537 #clock-cells = <0>;
538 clock-output-names = "vclk2";
539 };
540 vclk3_clk: vclk3_clk@e615001c {
541 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
542 reg = <0 0xe615001c 0 4>;
543 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
544 <0>, <&extal2_clk>, <&main_div2_clk>,
545 <&extalr_clk>, <0>, <0>;
546 #clock-cells = <0>;
547 clock-output-names = "vclk3";
548 };
549 vclk4_clk: vclk4_clk@e6150014 {
550 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
551 reg = <0 0xe6150014 0 4>;
552 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
553 <0>, <&extal2_clk>, <&main_div2_clk>,
554 <&extalr_clk>, <0>, <0>;
555 #clock-cells = <0>;
556 clock-output-names = "vclk4";
557 };
558 vclk5_clk: vclk5_clk@e6150034 {
559 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
560 reg = <0 0xe6150034 0 4>;
561 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
562 <0>, <&extal2_clk>, <&main_div2_clk>,
563 <&extalr_clk>, <0>, <0>;
564 #clock-cells = <0>;
565 clock-output-names = "vclk5";
566 };
567 fsia_clk: fsia_clk@e6150018 {
568 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
569 reg = <0 0xe6150018 0 4>;
570 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
571 <&fsiack_clk>, <0>;
572 #clock-cells = <0>;
573 clock-output-names = "fsia";
574 };
575 fsib_clk: fsib_clk@e6150090 {
576 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
577 reg = <0 0xe6150090 0 4>;
578 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
579 <&fsibck_clk>, <0>;
580 #clock-cells = <0>;
581 clock-output-names = "fsib";
582 };
583 mp_clk: mp_clk@e6150080 {
584 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
585 reg = <0 0xe6150080 0 4>;
586 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
587 <&extal2_clk>, <&extal2_clk>;
588 #clock-cells = <0>;
589 clock-output-names = "mp";
590 };
591 m4_clk: m4_clk@e6150098 {
592 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
593 reg = <0 0xe6150098 0 4>;
594 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>;
595 #clock-cells = <0>;
596 clock-output-names = "m4";
597 };
598 hsi_clk: hsi_clk@e615026c {
599 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
600 reg = <0 0xe615026c 0 4>;
601 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>,
602 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>;
603 #clock-cells = <0>;
604 clock-output-names = "hsi";
605 };
606 spuv_clk: spuv_clk@e6150094 {
607 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
608 reg = <0 0xe6150094 0 4>;
609 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>,
610 <&extal2_clk>, <&extal2_clk>;
611 #clock-cells = <0>;
612 clock-output-names = "spuv";
613 };
614
615 /* Fixed factor clocks */
616 main_div2_clk: main_div2_clk {
617 compatible = "fixed-factor-clock";
618 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>;
619 #clock-cells = <0>;
620 clock-div = <2>;
621 clock-mult = <1>;
622 clock-output-names = "main_div2";
623 };
624 pll0_div2_clk: pll0_div2_clk {
625 compatible = "fixed-factor-clock";
626 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>;
627 #clock-cells = <0>;
628 clock-div = <2>;
629 clock-mult = <1>;
630 clock-output-names = "pll0_div2";
631 };
632 pll1_div2_clk: pll1_div2_clk {
633 compatible = "fixed-factor-clock";
634 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>;
635 #clock-cells = <0>;
636 clock-div = <2>;
637 clock-mult = <1>;
638 clock-output-names = "pll1_div2";
639 };
640 extal1_div2_clk: extal1_div2_clk {
641 compatible = "fixed-factor-clock";
642 clocks = <&extal1_clk>;
643 #clock-cells = <0>;
644 clock-div = <2>;
645 clock-mult = <1>;
646 clock-output-names = "extal1_div2";
647 };
648
649 /* Gate clocks */
650 mstp2_clks: mstp2_clks@e6150138 {
651 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
652 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
653 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
654 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
655 #clock-cells = <1>;
656 clock-indices = <
657 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1
658 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1
659 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3
660 R8A73A4_CLK_DMAC
661 >;
662 clock-output-names =
663 "scifa0", "scifa1", "scifb0", "scifb1",
664 "scifb2", "scifb3", "dmac";
665 };
666 mstp3_clks: mstp3_clks@e615013c {
667 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
668 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
669 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>,
670 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>,
671 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
672 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks
673 R8A73A4_CLK_HP>, <&cpg_clocks
674 R8A73A4_CLK_HP>, <&extalr_clk>;
675 #clock-cells = <1>;
676 clock-indices = <
677 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1
678 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1
679 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0
680 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7
681 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1
682 R8A73A4_CLK_CMT1
683 >;
684 clock-output-names =
685 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0",
686 "mmcif0", "iic6", "iic7", "iic0", "iic1",
687 "cmt1";
688 };
689 mstp4_clks: mstp4_clks@e6150140 {
690 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
691 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
692 clocks = <&main_div2_clk>, <&cpg_clocks R8A73A4_CLK_HP>,
693 <&cpg_clocks R8A73A4_CLK_HP>;
694 #clock-cells = <1>;
695 clock-indices = <
696 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4
697 R8A73A4_CLK_IIC3
698 >;
699 clock-output-names =
700 "iic5", "iic4", "iic3";
701 };
702 mstp5_clks: mstp5_clks@e6150144 {
703 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
704 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
705 clocks = <&extal2_clk>, <&cpg_clocks R8A73A4_CLK_HP>;
706 #clock-cells = <1>;
707 clock-indices = <
708 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8
709 >;
710 clock-output-names =
711 "thermal", "iic8";
712 };
713 };
eccf0607 714};
Linux kernel - Deliverables
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