[deliverable/linux.git] / arch / arm / boot / dts / r8a7779.dtsi

/*
 * Device Tree Source for Renesas r8a7779
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/power/r8a7779-sysc.h>

/ {
	compatible = "renesas,r8a7779";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1000000000>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1000000000>;
			power-domains = <&sysc R8A7779_PD_ARM1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clock-frequency = <1000000000>;
			power-domains = <&sysc R8A7779_PD_ARM2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clock-frequency = <1000000000>;
			power-domains = <&sysc R8A7779_PD_ARM3>;
		};
	};

	aliases {
		spi0 = &hspi0;
		spi1 = &hspi1;
		spi2 = &hspi2;
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	timer@f0000600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0xf0000600 0x20>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
		clocks = <&cpg_clocks R8A7779_CLK_ZS>;
	};

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc40000 0x2c>;
		interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc41000 0x2c>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc42000 0x2c>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc43000 0x2c>;
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc44000 0x2c>;
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio5: gpio@ffc45000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc45000 0x2c>;
		interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio6: gpio@ffc46000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc46000 0x2c>;
		interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 9>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	irqpin0: interrupt-controller@fe78001c {
		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		status = "disabled";
		interrupt-controller;
		reg = <0xfe78001c 4>,
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>,
			<0xfe780000 4>;
		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
			      GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		sense-bitfield-width = <2>;
	};

	i2c0: i2c@ffc70000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc70000 0x1000>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	i2c1: i2c@ffc71000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc71000 0x1000>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	i2c2: i2c@ffc72000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc72000 0x1000>;
		interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	i2c3: i2c@ffc73000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc73000 0x1000>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif0: serial@ffe40000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe40000 0x100>;
		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif1: serial@ffe41000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe41000 0x100>;
		interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif2: serial@ffe42000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe42000 0x100>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif3: serial@ffe43000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe43000 0x100>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif4: serial@ffe44000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe44000 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	scif5: serial@ffe45000 {
		compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
			     "renesas,scif";
		reg = <0xffe45000 0x100>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
			 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
		clock-names = "fck", "brg_int", "scif_clk";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	pfc: pfc@fffc0000 {
		compatible = "renesas,pfc-r8a7779";
		reg = <0xfffc0000 0x23c>;
	};

	thermal@ffc48000 {
		compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
		reg = <0xffc48000 0x38>;
	};

	tmu0: timer@ffd80000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd80000 0x30>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu1: timer@ffd81000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd81000 0x30>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu2: timer@ffd82000 {
		compatible = "renesas,tmu-r8a7779", "renesas,tmu";
		reg = <0xffd82000 0x30>;
		interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
		clock-names = "fck";
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

		#renesas,channels = <3>;

		status = "disabled";
	};

	sata: sata@fc600000 {
		compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
		reg = <0xfc600000 0x2000>;
		interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
	};

	sdhi0: sd@ffe4c000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4c000 0x100>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi1: sd@ffe4d000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4d000 0x100>;
		interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi2: sd@ffe4e000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4e000 0x100>;
		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	sdhi3: sd@ffe4f000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4f000 0x100>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi0: spi@fffc7000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc7000 0x18>;
		interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi1: spi@fffc8000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc8000 0x18>;
		interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	hspi2: spi@fffc6000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc6000 0x18>;
		interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";
	};

	du: display@fff80000 {
		compatible = "renesas,du-r8a7779";
		reg = <0 0xfff80000 0 0x40000>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_DU>;
		power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				du_out_rgb0: endpoint {
				};
			};
			port@1 {
				reg = <1>;
				du_out_rgb1: endpoint {
				};
			};
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clock */
		extal_clk: extal {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overriden by the board. */
			clock-frequency = <0>;
		};

		/* External SCIF clock */
		scif_clk: scif {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overridden by the board. */
			clock-frequency = <0>;
		};

		/* Special CPG clocks */
		cpg_clocks: clocks@ffc80000 {
			compatible = "renesas,r8a7779-cpg-clocks";
			reg = <0xffc80000 0x30>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "plla", "z", "zs", "s",
					     "s1", "p", "b", "out";
			#power-domain-cells = <0>;
		};

		/* Fixed factor clocks */
		i_clk: i {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
		};
		s3_clk: s3 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
		};
		s4_clk: s4 {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <16>;
			clock-mult = <1>;
		};
		g_clk: g {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
		};

		/* Gate clocks */
		mstp0_clks: clocks@ffc80030 {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc80030 4>;
			clocks = <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_HSPI R8A7779_CLK_TMU2
				R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
				R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
			>;
			clock-output-names =
				"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
				"hscif0", "scif5", "scif4", "scif3", "scif2",
				"scif1", "scif0", "i2c3", "i2c2", "i2c1",
				"i2c0";
		};
		mstp1_clks: clocks@ffc80034 {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc80034 4>, <0xffc80044 4>;
			clocks = <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_USB01 R8A7779_CLK_USB2
				R8A7779_CLK_DU R8A7779_CLK_VIN2
				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
				R8A7779_CLK_ETHER R8A7779_CLK_SATA
				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
			>;
			clock-output-names =
				"usb01", "usb2",
				"du", "vin2",
				"vin1", "vin0",
				"ether", "sata",
				"pcie", "vin3";
		};
		mstp3_clks: clocks@ffc8003c {
			compatible = "renesas,r8a7779-mstp-clocks",
				     "renesas,cpg-mstp-clocks";
			reg = <0xffc8003c 4>;
			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
				 <&s4_clk>, <&s4_clk>;
			#clock-cells = <1>;
			clock-indices = <
				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
			>;
			clock-output-names =
				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
				"mmc1", "mmc0";
		};
	};

	sysc: system-controller@ffd85000 {
		compatible = "renesas,r8a7779-sysc";
		reg = <0xffd85000 0x0200>;
		#power-domain-cells = <1>;
	};
};
Commit	Line	Data
c58a1545	1	/*
349f556e	2	* Device Tree Source for Renesas r8a7779
c58a1545 SH	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Simon Horman
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	/include/ "skeleton.dtsi"
	13
1e851538	14	#include <dt-bindings/clock/r8a7779-clock.h>
cea80654	15	#include <dt-bindings/interrupt-controller/arm-gic.h>
5f75e73c	16	#include <dt-bindings/interrupt-controller/irq.h>
b2df3aa4	17	#include <dt-bindings/power/r8a7779-sysc.h>
5f75e73c	18
c58a1545 SH	19	/ {
c58a1545 SH	20	compatible = "renesas,r8a7779";
9ff254ad	21	interrupt-parent = <&gic>;
c58a1545 SH	22
	23	cpus {
	24	#address-cells = <1>;
	25	#size-cells = <0>;
	26
	27	cpu@0 {
	28	device_type = "cpu";
	29	compatible = "arm,cortex-a9";
	30	reg = <0>;
6b060f93	31	clock-frequency = <1000000000>;
c58a1545 SH	32	};
	33	cpu@1 {
	34	device_type = "cpu";
	35	compatible = "arm,cortex-a9";
	36	reg = <1>;
6b060f93	37	clock-frequency = <1000000000>;
b2df3aa4	38	power-domains = <&sysc R8A7779_PD_ARM1>;
c58a1545 SH	39	};
	40	cpu@2 {
	41	device_type = "cpu";
	42	compatible = "arm,cortex-a9";
	43	reg = <2>;
6b060f93	44	clock-frequency = <1000000000>;
b2df3aa4	45	power-domains = <&sysc R8A7779_PD_ARM2>;
c58a1545 SH	46	};
	47	cpu@3 {
	48	device_type = "cpu";
	49	compatible = "arm,cortex-a9";
	50	reg = <3>;
6b060f93	51	clock-frequency = <1000000000>;
b2df3aa4	52	power-domains = <&sysc R8A7779_PD_ARM3>;
c58a1545 SH	53	};
	54	};
	55
3c3f6ad3 SH	56	aliases {
	57	spi0 = &hspi0;
	58	spi1 = &hspi1;
	59	spi2 = &hspi2;
	60	};
	61
cc703a59 SH	62	gic: interrupt-controller@f0001000 {
	63	compatible = "arm,cortex-a9-gic";
	64	#interrupt-cells = <3>;
	65	interrupt-controller;
	66	reg = <0xf0001000 0x1000>,
	67	<0xf0000100 0x100>;
	68	};
10e8d4f6	69
cea80654 MD	70	timer@f0000600 {
	71	compatible = "arm,cortex-a9-twd-timer";
	72	reg = <0xf0000600 0x20>;
	73	interrupts = <GIC_PPI 13
e6c24882	74	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_EDGE_RISING)>;
cea80654 MD	75	clocks = <&cpg_clocks R8A7779_CLK_ZS>;
	76	};
	77
f5c771b5 LP	78	gpio0: gpio@ffc40000 {
	79	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	80	reg = <0xffc40000 0x2c>;
854b7733	81	interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	82	#gpio-cells = <2>;
	83	gpio-controller;
	84	gpio-ranges = <&pfc 0 0 32>;
	85	#interrupt-cells = <2>;
	86	interrupt-controller;
	87	};
	88
	89	gpio1: gpio@ffc41000 {
	90	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	91	reg = <0xffc41000 0x2c>;
854b7733	92	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	93	#gpio-cells = <2>;
	94	gpio-controller;
	95	gpio-ranges = <&pfc 0 32 32>;
	96	#interrupt-cells = <2>;
	97	interrupt-controller;
	98	};
	99
	100	gpio2: gpio@ffc42000 {
	101	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	102	reg = <0xffc42000 0x2c>;
854b7733	103	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	104	#gpio-cells = <2>;
	105	gpio-controller;
	106	gpio-ranges = <&pfc 0 64 32>;
	107	#interrupt-cells = <2>;
	108	interrupt-controller;
	109	};
	110
	111	gpio3: gpio@ffc43000 {
	112	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	113	reg = <0xffc43000 0x2c>;
854b7733	114	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	115	#gpio-cells = <2>;
	116	gpio-controller;
	117	gpio-ranges = <&pfc 0 96 32>;
	118	#interrupt-cells = <2>;
	119	interrupt-controller;
	120	};
	121
	122	gpio4: gpio@ffc44000 {
	123	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	124	reg = <0xffc44000 0x2c>;
854b7733	125	interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	126	#gpio-cells = <2>;
	127	gpio-controller;
	128	gpio-ranges = <&pfc 0 128 32>;
	129	#interrupt-cells = <2>;
	130	interrupt-controller;
	131	};
	132
	133	gpio5: gpio@ffc45000 {
	134	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	135	reg = <0xffc45000 0x2c>;
854b7733	136	interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	137	#gpio-cells = <2>;
	138	gpio-controller;
	139	gpio-ranges = <&pfc 0 160 32>;
	140	#interrupt-cells = <2>;
	141	interrupt-controller;
	142	};
	143
	144	gpio6: gpio@ffc46000 {
	145	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	146	reg = <0xffc46000 0x2c>;
854b7733	147	interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	148	#gpio-cells = <2>;
	149	gpio-controller;
	150	gpio-ranges = <&pfc 0 192 9>;
	151	#interrupt-cells = <2>;
	152	interrupt-controller;
	153	};
	154
7bf46d0b	155	irqpin0: interrupt-controller@fe78001c {
11ef0340	156	compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
24603f3c	157	#interrupt-cells = <2>;
84b47dfc	158	status = "disabled";
24603f3c GL	159	interrupt-controller;
	160	reg = <0xfe78001c 4>,
	161	<0xfe780010 4>,
	162	<0xfe780024 4>,
	163	<0xfe780044 4>,
7bf46d0b MD	164	<0xfe780064 4>,
7bf46d0b MD	165	<0xfe780000 4>;
854b7733 SH	166	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
	167	GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
	168	GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
	169	GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
24603f3c GL	170	sense-bitfield-width = <2>;
	171	};
	172
98724b7e	173	i2c0: i2c@ffc70000 {
10e8d4f6 SH	174	#address-cells = <1>;
10e8d4f6 SH	175	#size-cells = <0>;
6363070e	176	compatible = "renesas,i2c-r8a7779";
10e8d4f6	177	reg = <0xffc70000 0x1000>;
854b7733	178	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	179	clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
751e29bb	180	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
eda3a4fa	181	status = "disabled";
10e8d4f6 SH	182	};
10e8d4f6 SH	183
98724b7e	184	i2c1: i2c@ffc71000 {
10e8d4f6 SH	185	#address-cells = <1>;
10e8d4f6 SH	186	#size-cells = <0>;
6363070e	187	compatible = "renesas,i2c-r8a7779";
10e8d4f6	188	reg = <0xffc71000 0x1000>;
854b7733	189	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	190	clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
751e29bb	191	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
eda3a4fa	192	status = "disabled";
10e8d4f6 SH	193	};
10e8d4f6 SH	194
98724b7e	195	i2c2: i2c@ffc72000 {
10e8d4f6 SH	196	#address-cells = <1>;
10e8d4f6 SH	197	#size-cells = <0>;
6363070e	198	compatible = "renesas,i2c-r8a7779";
10e8d4f6	199	reg = <0xffc72000 0x1000>;
854b7733	200	interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	201	clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
751e29bb	202	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
eda3a4fa	203	status = "disabled";
10e8d4f6 SH	204	};
10e8d4f6 SH	205
98724b7e	206	i2c3: i2c@ffc73000 {
10e8d4f6 SH	207	#address-cells = <1>;
10e8d4f6 SH	208	#size-cells = <0>;
6363070e	209	compatible = "renesas,i2c-r8a7779";
10e8d4f6	210	reg = <0xffc73000 0x1000>;
854b7733	211	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	212	clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
751e29bb	213	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
eda3a4fa	214	status = "disabled";
10e8d4f6	215	};
25a65975	216
fd953b89	217	scif0: serial@ffe40000 {
b2ac44fa GU	218	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	219	"renesas,scif";
fd953b89	220	reg = <0xffe40000 0x100>;
854b7733	221	interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	222	clocks = <&mstp0_clks R8A7779_CLK_SCIF0>,
	223	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	224	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	225	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	226	status = "disabled";
	227	};
	228
	229	scif1: serial@ffe41000 {
b2ac44fa GU	230	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	231	"renesas,scif";
fd953b89	232	reg = <0xffe41000 0x100>;
854b7733	233	interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	234	clocks = <&mstp0_clks R8A7779_CLK_SCIF1>,
	235	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	236	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	237	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	238	status = "disabled";
	239	};
	240
	241	scif2: serial@ffe42000 {
b2ac44fa GU	242	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	243	"renesas,scif";
fd953b89	244	reg = <0xffe42000 0x100>;
854b7733	245	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	246	clocks = <&mstp0_clks R8A7779_CLK_SCIF2>,
	247	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	248	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	249	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	250	status = "disabled";
	251	};
	252
	253	scif3: serial@ffe43000 {
b2ac44fa GU	254	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	255	"renesas,scif";
fd953b89	256	reg = <0xffe43000 0x100>;
854b7733	257	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	258	clocks = <&mstp0_clks R8A7779_CLK_SCIF3>,
	259	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	260	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	261	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	262	status = "disabled";
	263	};
	264
	265	scif4: serial@ffe44000 {
b2ac44fa GU	266	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	267	"renesas,scif";
fd953b89	268	reg = <0xffe44000 0x100>;
854b7733	269	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	270	clocks = <&mstp0_clks R8A7779_CLK_SCIF4>,
	271	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	272	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	273	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	274	status = "disabled";
	275	};
	276
	277	scif5: serial@ffe45000 {
b2ac44fa GU	278	compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif",
b2ac44fa GU	279	"renesas,scif";
fd953b89	280	reg = <0xffe45000 0x100>;
854b7733	281	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
f2be5f00 GU	282	clocks = <&mstp0_clks R8A7779_CLK_SCIF5>,
	283	<&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>;
	284	clock-names = "fck", "brg_int", "scif_clk";
751e29bb	285	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
fd953b89 SH	286	status = "disabled";
	287	};
	288
3ab03d01 LP	289	pfc: pfc@fffc0000 {
	290	compatible = "renesas,pfc-r8a7779";
	291	reg = <0xfffc0000 0x23c>;
	292	};
	293
25a65975	294	thermal@ffc48000 {
4d50e6dd	295	compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal";
25a65975 KM	296	reg = <0xffc48000 0x38>;
25a65975 KM	297	};
7840a65a	298
ef890ea2	299	tmu0: timer@ffd80000 {
a51b7b38	300	compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2	301	reg = <0xffd80000 0x30>;
854b7733 SH	302	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	303	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	304	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
ef890ea2 LP	305	clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
ef890ea2 LP	306	clock-names = "fck";
751e29bb	307	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
ef890ea2 LP	308
	309	#renesas,channels = <3>;
	310
	311	status = "disabled";
	312	};
	313
	314	tmu1: timer@ffd81000 {
a51b7b38	315	compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2	316	reg = <0xffd81000 0x30>;
854b7733 SH	317	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
	318	<GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
	319	<GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
ef890ea2 LP	320	clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
ef890ea2 LP	321	clock-names = "fck";
751e29bb	322	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
ef890ea2 LP	323
	324	#renesas,channels = <3>;
	325
	326	status = "disabled";
	327	};
	328
	329	tmu2: timer@ffd82000 {
a51b7b38	330	compatible = "renesas,tmu-r8a7779", "renesas,tmu";
ef890ea2	331	reg = <0xffd82000 0x30>;
854b7733 SH	332	interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
	333	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	334	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
ef890ea2 LP	335	clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
ef890ea2 LP	336	clock-names = "fck";
751e29bb	337	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
ef890ea2 LP	338
	339	#renesas,channels = <3>;
	340
	341	status = "disabled";
	342	};
	343
7840a65a	344	sata: sata@fc600000 {
25af9c83	345	compatible = "renesas,sata-r8a7779", "renesas,rcar-sata";
7840a65a	346	reg = <0xfc600000 0x2000>;
854b7733	347	interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	348	clocks = <&mstp1_clks R8A7779_CLK_SATA>;
751e29bb	349	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
7840a65a	350	};
c4866e70	351
2624705c	352	sdhi0: sd@ffe4c000 {
c4866e70 KM	353	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	354	reg = <0xffe4c000 0x100>;
854b7733	355	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	356	clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
751e29bb	357	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
c4866e70 KM	358	status = "disabled";
	359	};
	360
2624705c	361	sdhi1: sd@ffe4d000 {
c4866e70 KM	362	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	363	reg = <0xffe4d000 0x100>;
854b7733	364	interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	365	clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
751e29bb	366	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
c4866e70 KM	367	status = "disabled";
	368	};
	369
2624705c	370	sdhi2: sd@ffe4e000 {
c4866e70 KM	371	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	372	reg = <0xffe4e000 0x100>;
854b7733	373	interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	374	clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
751e29bb	375	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
c4866e70 KM	376	status = "disabled";
	377	};
	378
2624705c	379	sdhi3: sd@ffe4f000 {
c4866e70 KM	380	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	381	reg = <0xffe4f000 0x100>;
854b7733	382	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	383	clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
751e29bb	384	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
c4866e70 KM	385	status = "disabled";
c4866e70 KM	386	};
3c3f6ad3 SH	387
3c3f6ad3 SH	388	hspi0: spi@fffc7000 {
7709c33b	389	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	390	reg = <0xfffc7000 0x18>;
854b7733	391	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	392	#address-cells = <1>;
7709c33b GU	393	#size-cells = <0>;
3325cbe8	394	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
751e29bb	395	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
3c3f6ad3 SH	396	status = "disabled";
	397	};
	398
	399	hspi1: spi@fffc8000 {
7709c33b	400	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	401	reg = <0xfffc8000 0x18>;
854b7733	402	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	403	#address-cells = <1>;
7709c33b GU	404	#size-cells = <0>;
3325cbe8	405	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
751e29bb	406	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
3c3f6ad3 SH	407	status = "disabled";
	408	};
	409
	410	hspi2: spi@fffc6000 {
7709c33b	411	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	412	reg = <0xfffc6000 0x18>;
854b7733	413	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	414	#address-cells = <1>;
7709c33b GU	415	#size-cells = <0>;
3325cbe8	416	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
751e29bb	417	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
3c3f6ad3 SH	418	status = "disabled";
3c3f6ad3 SH	419	};
1e851538	420
1f08bbe8 LP	421	du: display@fff80000 {
	422	compatible = "renesas,du-r8a7779";
	423	reg = <0 0xfff80000 0 0x40000>;
854b7733	424	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
1f08bbe8	425	clocks = <&mstp1_clks R8A7779_CLK_DU>;
751e29bb	426	power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;
1f08bbe8 LP	427	status = "disabled";
	428
	429	ports {
	430	#address-cells = <1>;
	431	#size-cells = <0>;
	432
	433	port@0 {
	434	reg = <0>;
	435	du_out_rgb0: endpoint {
	436	};
	437	};
	438	port@1 {
	439	reg = <1>;
	440	du_out_rgb1: endpoint {
	441	};
	442	};
	443	};
	444	};
	445
1e851538	446	clocks {
5cc8afcb GU	447	#address-cells = <1>;
5cc8afcb GU	448	#size-cells = <1>;
1e851538 SH	449	ranges;
	450
	451	/* External root clock */
3f6dba70	452	extal_clk: extal {
1e851538 SH	453	compatible = "fixed-clock";
	454	#clock-cells = <0>;
	455	/* This value must be overriden by the board. */
	456	clock-frequency = <0>;
1e851538 SH	457	};
1e851538 SH	458
f2be5f00 GU	459	/* External SCIF clock */
	460	scif_clk: scif {
	461	compatible = "fixed-clock";
	462	#clock-cells = <0>;
	463	/* This value must be overridden by the board. */
	464	clock-frequency = <0>;
f2be5f00 GU	465	};
f2be5f00 GU	466
1e851538	467	/* Special CPG clocks */
2909b874	468	cpg_clocks: clocks@ffc80000 {
1e851538	469	compatible = "renesas,r8a7779-cpg-clocks";
5cc8afcb	470	reg = <0xffc80000 0x30>;
1e851538 SH	471	clocks = <&extal_clk>;
	472	#clock-cells = <1>;
	473	clock-output-names = "plla", "z", "zs", "s",
	474	"s1", "p", "b", "out";
33c3632a	475	#power-domain-cells = <0>;
1e851538 SH	476	};
	477
	478	/* Fixed factor clocks */
3f6dba70	479	i_clk: i {
1e851538 SH	480	compatible = "fixed-factor-clock";
	481	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	482	#clock-cells = <0>;
	483	clock-div = <2>;
	484	clock-mult = <1>;
1e851538	485	};
3f6dba70	486	s3_clk: s3 {
1e851538 SH	487	compatible = "fixed-factor-clock";
	488	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	489	#clock-cells = <0>;
	490	clock-div = <8>;
	491	clock-mult = <1>;
1e851538	492	};
3f6dba70	493	s4_clk: s4 {
1e851538 SH	494	compatible = "fixed-factor-clock";
	495	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	496	#clock-cells = <0>;
	497	clock-div = <16>;
	498	clock-mult = <1>;
1e851538	499	};
3f6dba70	500	g_clk: g {
1e851538 SH	501	compatible = "fixed-factor-clock";
	502	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	503	#clock-cells = <0>;
	504	clock-div = <24>;
	505	clock-mult = <1>;
1e851538 SH	506	};
	507
	508	/* Gate clocks */
2909b874	509	mstp0_clks: clocks@ffc80030 {
1e851538	510	compatible = "renesas,r8a7779-mstp-clocks",
99e544c7	511	"renesas,cpg-mstp-clocks";
5cc8afcb	512	reg = <0xffc80030 4>;
1e851538	513	clocks = <&cpg_clocks R8A7779_CLK_S>,
99e544c7	514	<&cpg_clocks R8A7779_CLK_P>,
1e851538 SH	515	<&cpg_clocks R8A7779_CLK_P>,
	516	<&cpg_clocks R8A7779_CLK_P>,
	517	<&cpg_clocks R8A7779_CLK_S>,
	518	<&cpg_clocks R8A7779_CLK_S>,
c6ce3cdf MD	519	<&cpg_clocks R8A7779_CLK_P>,
	520	<&cpg_clocks R8A7779_CLK_P>,
	521	<&cpg_clocks R8A7779_CLK_P>,
	522	<&cpg_clocks R8A7779_CLK_P>,
	523	<&cpg_clocks R8A7779_CLK_P>,
	524	<&cpg_clocks R8A7779_CLK_P>,
1e851538 SH	525	<&cpg_clocks R8A7779_CLK_P>,
	526	<&cpg_clocks R8A7779_CLK_P>,
	527	<&cpg_clocks R8A7779_CLK_P>,
	528	<&cpg_clocks R8A7779_CLK_P>;
	529	#clock-cells = <1>;
64530fc2	530	clock-indices = <
1e851538 SH	531	R8A7779_CLK_HSPI R8A7779_CLK_TMU2
	532	R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
	533	R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
	534	R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
	535	R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
	536	R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
	537	R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
	538	R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
	539	>;
	540	clock-output-names =
	541	"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
	542	"hscif0", "scif5", "scif4", "scif3", "scif2",
	543	"scif1", "scif0", "i2c3", "i2c2", "i2c1",
	544	"i2c0";
	545	};
2909b874	546	mstp1_clks: clocks@ffc80034 {
1e851538	547	compatible = "renesas,r8a7779-mstp-clocks",
99e544c7	548	"renesas,cpg-mstp-clocks";
5cc8afcb	549	reg = <0xffc80034 4>, <0xffc80044 4>;
1e851538 SH	550	clocks = <&cpg_clocks R8A7779_CLK_P>,
	551	<&cpg_clocks R8A7779_CLK_P>,
	552	<&cpg_clocks R8A7779_CLK_S>,
	553	<&cpg_clocks R8A7779_CLK_S>,
	554	<&cpg_clocks R8A7779_CLK_S>,
	555	<&cpg_clocks R8A7779_CLK_S>,
	556	<&cpg_clocks R8A7779_CLK_P>,
	557	<&cpg_clocks R8A7779_CLK_P>,
	558	<&cpg_clocks R8A7779_CLK_P>,
	559	<&cpg_clocks R8A7779_CLK_S>;
	560	#clock-cells = <1>;
64530fc2	561	clock-indices = <
1e851538 SH	562	R8A7779_CLK_USB01 R8A7779_CLK_USB2
	563	R8A7779_CLK_DU R8A7779_CLK_VIN2
	564	R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
	565	R8A7779_CLK_ETHER R8A7779_CLK_SATA
	566	R8A7779_CLK_PCIE R8A7779_CLK_VIN3
	567	>;
	568	clock-output-names =
	569	"usb01", "usb2",
	570	"du", "vin2",
	571	"vin1", "vin0",
	572	"ether", "sata",
	573	"pcie", "vin3";
	574	};
2909b874	575	mstp3_clks: clocks@ffc8003c {
1e851538	576	compatible = "renesas,r8a7779-mstp-clocks",
99e544c7	577	"renesas,cpg-mstp-clocks";
5cc8afcb	578	reg = <0xffc8003c 4>;
1e851538 SH	579	clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
	580	<&s4_clk>, <&s4_clk>;
	581	#clock-cells = <1>;
64530fc2	582	clock-indices = <
1e851538 SH	583	R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
	584	R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
	585	R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
	586	>;
	587	clock-output-names =
	588	"sdhi3", "sdhi2", "sdhi1", "sdhi0",
	589	"mmc1", "mmc0";
	590	};
	591	};
b2df3aa4 GU	592
	593	sysc: system-controller@ffd85000 {
	594	compatible = "renesas,r8a7779-sysc";
	595	reg = <0xffd85000 0x0200>;
	596	#power-domain-cells = <1>;
	597	};
c58a1545	598	};