[deliverable/linux.git] / arch / arm / boot / dts / r8a7779.dtsi

/*
 * Device Tree Source for Renesas r8a7779
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7779";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			clock-frequency = <1000000000>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			clock-frequency = <1000000000>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
			clock-frequency = <1000000000>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
			clock-frequency = <1000000000>;
		};
	};

	aliases {
		spi0 = &hspi0;
		spi1 = &hspi1;
		spi2 = &hspi2;
	};

	gic: interrupt-controller@f0001000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xf0001000 0x1000>,
		      <0xf0000100 0x100>;
	};

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc40000 0x2c>;
		interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc41000 0x2c>;
		interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc42000 0x2c>;
		interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc43000 0x2c>;
		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc44000 0x2c>;
		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio5: gpio@ffc45000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc45000 0x2c>;
		interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio6: gpio@ffc46000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc46000 0x2c>;
		interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 9>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	irqpin0: irqpin@fe780010 {
		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		status = "disabled";
		interrupt-controller;
		reg = <0xfe78001c 4>,
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>;
		interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
			      0 28 IRQ_TYPE_LEVEL_HIGH
			      0 29 IRQ_TYPE_LEVEL_HIGH
			      0 30 IRQ_TYPE_LEVEL_HIGH>;
		sense-bitfield-width = <2>;
	};

	i2c0: i2c@ffc70000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc70000 0x1000>;
		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
		status = "disabled";
	};

	i2c1: i2c@ffc71000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc71000 0x1000>;
		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
		status = "disabled";
	};

	i2c2: i2c@ffc72000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc72000 0x1000>;
		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
		status = "disabled";
	};

	i2c3: i2c@ffc73000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc73000 0x1000>;
		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
		status = "disabled";
	};

	scif0: serial@ffe40000 {
		compatible = "renesas,scif-r8a7779", "renesas,scif";
		reg = <0xffe40000 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg_clocks R8A7779_CLK_P>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif1: serial@ffe41000 {
		compatible = "renesas,scif-r8a7779", "renesas,scif";
		reg = <0xffe41000 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg_clocks R8A7779_CLK_P>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif2: serial@ffe42000 {
		compatible = "renesas,scif-r8a7779", "renesas,scif";
		reg = <0xffe42000 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg_clocks R8A7779_CLK_P>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif3: serial@ffe43000 {
		compatible = "renesas,scif-r8a7779", "renesas,scif";
		reg = <0xffe43000 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg_clocks R8A7779_CLK_P>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif4: serial@ffe44000 {
		compatible = "renesas,scif-r8a7779", "renesas,scif";
		reg = <0xffe44000 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg_clocks R8A7779_CLK_P>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	scif5: serial@ffe45000 {
		compatible = "renesas,scif-r8a7779", "renesas,scif";
		reg = <0xffe45000 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&cpg_clocks R8A7779_CLK_P>;
		clock-names = "sci_ick";
		status = "disabled";
	};

	pfc: pfc@fffc0000 {
		compatible = "renesas,pfc-r8a7779";
		reg = <0xfffc0000 0x23c>;
	};

	thermal@ffc48000 {
		compatible = "renesas,rcar-thermal";
		reg = <0xffc48000 0x38>;
	};

	tmu0: timer@ffd80000 {
		compatible = "renesas,tmu";
		reg = <0xffd80000 0x30>;
		interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
			     <0 33 IRQ_TYPE_LEVEL_HIGH>,
			     <0 34 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
		clock-names = "fck";

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu1: timer@ffd81000 {
		compatible = "renesas,tmu";
		reg = <0xffd81000 0x30>;
		interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
			     <0 37 IRQ_TYPE_LEVEL_HIGH>,
			     <0 38 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
		clock-names = "fck";

		#renesas,channels = <3>;

		status = "disabled";
	};

	tmu2: timer@ffd82000 {
		compatible = "renesas,tmu";
		reg = <0xffd82000 0x30>;
		interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
			     <0 41 IRQ_TYPE_LEVEL_HIGH>,
			     <0 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
		clock-names = "fck";

		#renesas,channels = <3>;

		status = "disabled";
	};

	sata: sata@fc600000 {
		compatible = "renesas,rcar-sata";
		reg = <0xfc600000 0x2000>;
		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp1_clks R8A7779_CLK_SATA>;
	};

	sdhi0: sd@ffe4c000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4c000 0x100>;
		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sdhi1: sd@ffe4d000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4d000 0x100>;
		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sdhi2: sd@ffe4e000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4e000 0x100>;
		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sdhi3: sd@ffe4f000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4f000 0x100>;
		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	hspi0: spi@fffc7000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc7000 0x18>;
		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		status = "disabled";
	};

	hspi1: spi@fffc8000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc8000 0x18>;
		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		status = "disabled";
	};

	hspi2: spi@fffc6000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc6000 0x18>;
		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
		status = "disabled";
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		/* External root clock */
		extal_clk: extal_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overriden by the board. */
			clock-frequency = <0>;
			clock-output-names = "extal";
		};

		/* Special CPG clocks */
		cpg_clocks: clocks@ffc80000 {
			compatible = "renesas,r8a7779-cpg-clocks";
			reg = <0xffc80000 0x30>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "plla", "z", "zs", "s",
					     "s1", "p", "b", "out";
		};

		/* Fixed factor clocks */
		i_clk: i_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "i";
		};
		s3_clk: s3_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "s3";
		};
		s4_clk: s4_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <16>;
			clock-mult = <1>;
			clock-output-names = "s4";
		};
		g_clk: g_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
			clock-output-names = "g";
		};

		/* Gate clocks */
		mstp0_clks: clocks@ffc80030 {
			compatible = "renesas,r8a7779-mstp-clocks",
			             "renesas,cpg-mstp-clocks";
			reg = <0xffc80030 4>;
			clocks = <&cpg_clocks R8A7779_CLK_S>,
			         <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7779_CLK_HSPI R8A7779_CLK_TMU2
				R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
				R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
			>;
			clock-output-names =
				"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
				"hscif0", "scif5", "scif4", "scif3", "scif2",
				"scif1", "scif0", "i2c3", "i2c2", "i2c1",
				"i2c0";
		};
		mstp1_clks: clocks@ffc80034 {
			compatible = "renesas,r8a7779-mstp-clocks",
			             "renesas,cpg-mstp-clocks";
			reg = <0xffc80034 4>, <0xffc80044 4>;
			clocks = <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7779_CLK_USB01 R8A7779_CLK_USB2
				R8A7779_CLK_DU R8A7779_CLK_VIN2
				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
				R8A7779_CLK_ETHER R8A7779_CLK_SATA
				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
			>;
			clock-output-names =
				"usb01", "usb2",
				"du", "vin2",
				"vin1", "vin0",
				"ether", "sata",
				"pcie", "vin3";
		};
		mstp3_clks: clocks@ffc8003c {
			compatible = "renesas,r8a7779-mstp-clocks",
			             "renesas,cpg-mstp-clocks";
			reg = <0xffc8003c 4>;
			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
				 <&s4_clk>, <&s4_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
			>;
			clock-output-names =
				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
				"mmc1", "mmc0";
		};
	};
};
Commit	Line	Data
c58a1545	1	/*
349f556e	2	* Device Tree Source for Renesas r8a7779
c58a1545 SH	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Simon Horman
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	/include/ "skeleton.dtsi"
	13
1e851538	14	#include <dt-bindings/clock/r8a7779-clock.h>
5f75e73c LP	15	#include <dt-bindings/interrupt-controller/irq.h>
5f75e73c LP	16
c58a1545 SH	17	/ {
c58a1545 SH	18	compatible = "renesas,r8a7779";
9ff254ad	19	interrupt-parent = <&gic>;
c58a1545 SH	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu@0 {
	26	device_type = "cpu";
	27	compatible = "arm,cortex-a9";
	28	reg = <0>;
6b060f93	29	clock-frequency = <1000000000>;
c58a1545 SH	30	};
	31	cpu@1 {
	32	device_type = "cpu";
	33	compatible = "arm,cortex-a9";
	34	reg = <1>;
6b060f93	35	clock-frequency = <1000000000>;
c58a1545 SH	36	};
	37	cpu@2 {
	38	device_type = "cpu";
	39	compatible = "arm,cortex-a9";
	40	reg = <2>;
6b060f93	41	clock-frequency = <1000000000>;
c58a1545 SH	42	};
	43	cpu@3 {
	44	device_type = "cpu";
	45	compatible = "arm,cortex-a9";
	46	reg = <3>;
6b060f93	47	clock-frequency = <1000000000>;
c58a1545 SH	48	};
	49	};
	50
3c3f6ad3 SH	51	aliases {
	52	spi0 = &hspi0;
	53	spi1 = &hspi1;
	54	spi2 = &hspi2;
	55	};
	56
cc703a59 SH	57	gic: interrupt-controller@f0001000 {
	58	compatible = "arm,cortex-a9-gic";
	59	#interrupt-cells = <3>;
	60	interrupt-controller;
	61	reg = <0xf0001000 0x1000>,
	62	<0xf0000100 0x100>;
	63	};
10e8d4f6	64
f5c771b5 LP	65	gpio0: gpio@ffc40000 {
	66	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	67	reg = <0xffc40000 0x2c>;
5f75e73c	68	interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	69	#gpio-cells = <2>;
	70	gpio-controller;
	71	gpio-ranges = <&pfc 0 0 32>;
	72	#interrupt-cells = <2>;
	73	interrupt-controller;
	74	};
	75
	76	gpio1: gpio@ffc41000 {
	77	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	78	reg = <0xffc41000 0x2c>;
5f75e73c	79	interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	80	#gpio-cells = <2>;
	81	gpio-controller;
	82	gpio-ranges = <&pfc 0 32 32>;
	83	#interrupt-cells = <2>;
	84	interrupt-controller;
	85	};
	86
	87	gpio2: gpio@ffc42000 {
	88	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	89	reg = <0xffc42000 0x2c>;
5f75e73c	90	interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	91	#gpio-cells = <2>;
	92	gpio-controller;
	93	gpio-ranges = <&pfc 0 64 32>;
	94	#interrupt-cells = <2>;
	95	interrupt-controller;
	96	};
	97
	98	gpio3: gpio@ffc43000 {
	99	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	100	reg = <0xffc43000 0x2c>;
5f75e73c	101	interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	102	#gpio-cells = <2>;
	103	gpio-controller;
	104	gpio-ranges = <&pfc 0 96 32>;
	105	#interrupt-cells = <2>;
	106	interrupt-controller;
	107	};
	108
	109	gpio4: gpio@ffc44000 {
	110	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	111	reg = <0xffc44000 0x2c>;
5f75e73c	112	interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	113	#gpio-cells = <2>;
	114	gpio-controller;
	115	gpio-ranges = <&pfc 0 128 32>;
	116	#interrupt-cells = <2>;
	117	interrupt-controller;
	118	};
	119
	120	gpio5: gpio@ffc45000 {
	121	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	122	reg = <0xffc45000 0x2c>;
5f75e73c	123	interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	124	#gpio-cells = <2>;
	125	gpio-controller;
	126	gpio-ranges = <&pfc 0 160 32>;
	127	#interrupt-cells = <2>;
	128	interrupt-controller;
	129	};
	130
	131	gpio6: gpio@ffc46000 {
	132	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	133	reg = <0xffc46000 0x2c>;
5f75e73c	134	interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	135	#gpio-cells = <2>;
	136	gpio-controller;
	137	gpio-ranges = <&pfc 0 192 9>;
	138	#interrupt-cells = <2>;
	139	interrupt-controller;
	140	};
	141
24603f3c	142	irqpin0: irqpin@fe780010 {
11ef0340	143	compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
24603f3c	144	#interrupt-cells = <2>;
84b47dfc	145	status = "disabled";
24603f3c GL	146	interrupt-controller;
	147	reg = <0xfe78001c 4>,
	148	<0xfe780010 4>,
	149	<0xfe780024 4>,
	150	<0xfe780044 4>,
	151	<0xfe780064 4>;
5f75e73c LP	152	interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
	153	0 28 IRQ_TYPE_LEVEL_HIGH
	154	0 29 IRQ_TYPE_LEVEL_HIGH
	155	0 30 IRQ_TYPE_LEVEL_HIGH>;
24603f3c GL	156	sense-bitfield-width = <2>;
	157	};
	158
98724b7e	159	i2c0: i2c@ffc70000 {
10e8d4f6 SH	160	#address-cells = <1>;
10e8d4f6 SH	161	#size-cells = <0>;
6363070e	162	compatible = "renesas,i2c-r8a7779";
10e8d4f6	163	reg = <0xffc70000 0x1000>;
5f75e73c	164	interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	165	clocks = <&mstp0_clks R8A7779_CLK_I2C0>;
eda3a4fa	166	status = "disabled";
10e8d4f6 SH	167	};
10e8d4f6 SH	168
98724b7e	169	i2c1: i2c@ffc71000 {
10e8d4f6 SH	170	#address-cells = <1>;
10e8d4f6 SH	171	#size-cells = <0>;
6363070e	172	compatible = "renesas,i2c-r8a7779";
10e8d4f6	173	reg = <0xffc71000 0x1000>;
5f75e73c	174	interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	175	clocks = <&mstp0_clks R8A7779_CLK_I2C1>;
eda3a4fa	176	status = "disabled";
10e8d4f6 SH	177	};
10e8d4f6 SH	178
98724b7e	179	i2c2: i2c@ffc72000 {
10e8d4f6 SH	180	#address-cells = <1>;
10e8d4f6 SH	181	#size-cells = <0>;
6363070e	182	compatible = "renesas,i2c-r8a7779";
10e8d4f6	183	reg = <0xffc72000 0x1000>;
5f75e73c	184	interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	185	clocks = <&mstp0_clks R8A7779_CLK_I2C2>;
eda3a4fa	186	status = "disabled";
10e8d4f6 SH	187	};
10e8d4f6 SH	188
98724b7e	189	i2c3: i2c@ffc73000 {
10e8d4f6 SH	190	#address-cells = <1>;
10e8d4f6 SH	191	#size-cells = <0>;
6363070e	192	compatible = "renesas,i2c-r8a7779";
10e8d4f6	193	reg = <0xffc73000 0x1000>;
5f75e73c	194	interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	195	clocks = <&mstp0_clks R8A7779_CLK_I2C3>;
eda3a4fa	196	status = "disabled";
10e8d4f6	197	};
25a65975	198
fd953b89 SH	199	scif0: serial@ffe40000 {
	200	compatible = "renesas,scif-r8a7779", "renesas,scif";
	201	reg = <0xffe40000 0x100>;
	202	interrupt-parent = <&gic>;
	203	interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
	204	clocks = <&cpg_clocks R8A7779_CLK_P>;
	205	clock-names = "sci_ick";
	206	status = "disabled";
	207	};
	208
	209	scif1: serial@ffe41000 {
	210	compatible = "renesas,scif-r8a7779", "renesas,scif";
	211	reg = <0xffe41000 0x100>;
	212	interrupt-parent = <&gic>;
	213	interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
	214	clocks = <&cpg_clocks R8A7779_CLK_P>;
	215	clock-names = "sci_ick";
	216	status = "disabled";
	217	};
	218
	219	scif2: serial@ffe42000 {
	220	compatible = "renesas,scif-r8a7779", "renesas,scif";
	221	reg = <0xffe42000 0x100>;
	222	interrupt-parent = <&gic>;
	223	interrupts = <0 90 IRQ_TYPE_LEVEL_HIGH>;
	224	clocks = <&cpg_clocks R8A7779_CLK_P>;
	225	clock-names = "sci_ick";
	226	status = "disabled";
	227	};
	228
	229	scif3: serial@ffe43000 {
	230	compatible = "renesas,scif-r8a7779", "renesas,scif";
	231	reg = <0xffe43000 0x100>;
	232	interrupt-parent = <&gic>;
	233	interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>;
	234	clocks = <&cpg_clocks R8A7779_CLK_P>;
	235	clock-names = "sci_ick";
	236	status = "disabled";
	237	};
	238
	239	scif4: serial@ffe44000 {
	240	compatible = "renesas,scif-r8a7779", "renesas,scif";
	241	reg = <0xffe44000 0x100>;
	242	interrupt-parent = <&gic>;
	243	interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;
	244	clocks = <&cpg_clocks R8A7779_CLK_P>;
	245	clock-names = "sci_ick";
	246	status = "disabled";
	247	};
	248
	249	scif5: serial@ffe45000 {
	250	compatible = "renesas,scif-r8a7779", "renesas,scif";
	251	reg = <0xffe45000 0x100>;
	252	interrupt-parent = <&gic>;
	253	interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>;
	254	clocks = <&cpg_clocks R8A7779_CLK_P>;
	255	clock-names = "sci_ick";
	256	status = "disabled";
	257	};
	258
3ab03d01 LP	259	pfc: pfc@fffc0000 {
	260	compatible = "renesas,pfc-r8a7779";
	261	reg = <0xfffc0000 0x23c>;
	262	};
	263
25a65975 KM	264	thermal@ffc48000 {
	265	compatible = "renesas,rcar-thermal";
	266	reg = <0xffc48000 0x38>;
	267	};
7840a65a	268
ef890ea2 LP	269	tmu0: timer@ffd80000 {
	270	compatible = "renesas,tmu";
	271	reg = <0xffd80000 0x30>;
	272	interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
	273	<0 33 IRQ_TYPE_LEVEL_HIGH>,
	274	<0 34 IRQ_TYPE_LEVEL_HIGH>;
	275	clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
	276	clock-names = "fck";
	277
	278	#renesas,channels = <3>;
	279
	280	status = "disabled";
	281	};
	282
	283	tmu1: timer@ffd81000 {
	284	compatible = "renesas,tmu";
	285	reg = <0xffd81000 0x30>;
	286	interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
	287	<0 37 IRQ_TYPE_LEVEL_HIGH>,
	288	<0 38 IRQ_TYPE_LEVEL_HIGH>;
	289	clocks = <&mstp0_clks R8A7779_CLK_TMU1>;
	290	clock-names = "fck";
	291
	292	#renesas,channels = <3>;
	293
	294	status = "disabled";
	295	};
	296
	297	tmu2: timer@ffd82000 {
	298	compatible = "renesas,tmu";
	299	reg = <0xffd82000 0x30>;
	300	interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
	301	<0 41 IRQ_TYPE_LEVEL_HIGH>,
	302	<0 42 IRQ_TYPE_LEVEL_HIGH>;
	303	clocks = <&mstp0_clks R8A7779_CLK_TMU2>;
	304	clock-names = "fck";
	305
	306	#renesas,channels = <3>;
	307
	308	status = "disabled";
	309	};
	310
7840a65a VB	311	sata: sata@fc600000 {
	312	compatible = "renesas,rcar-sata";
	313	reg = <0xfc600000 0x2000>;
5f75e73c	314	interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	315	clocks = <&mstp1_clks R8A7779_CLK_SATA>;
7840a65a	316	};
c4866e70	317
2624705c	318	sdhi0: sd@ffe4c000 {
c4866e70 KM	319	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	320	reg = <0xffe4c000 0x100>;
5f75e73c	321	interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	322	clocks = <&mstp3_clks R8A7779_CLK_SDHI0>;
c4866e70 KM	323	cap-sd-highspeed;
	324	cap-sdio-irq;
	325	status = "disabled";
	326	};
	327
2624705c	328	sdhi1: sd@ffe4d000 {
c4866e70 KM	329	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	330	reg = <0xffe4d000 0x100>;
5f75e73c	331	interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	332	clocks = <&mstp3_clks R8A7779_CLK_SDHI1>;
c4866e70 KM	333	cap-sd-highspeed;
	334	cap-sdio-irq;
	335	status = "disabled";
	336	};
	337
2624705c	338	sdhi2: sd@ffe4e000 {
c4866e70 KM	339	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	340	reg = <0xffe4e000 0x100>;
5f75e73c	341	interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	342	clocks = <&mstp3_clks R8A7779_CLK_SDHI2>;
c4866e70 KM	343	cap-sd-highspeed;
	344	cap-sdio-irq;
	345	status = "disabled";
	346	};
	347
2624705c	348	sdhi3: sd@ffe4f000 {
c4866e70 KM	349	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	350	reg = <0xffe4f000 0x100>;
5f75e73c	351	interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
3325cbe8	352	clocks = <&mstp3_clks R8A7779_CLK_SDHI3>;
c4866e70 KM	353	cap-sd-highspeed;
	354	cap-sdio-irq;
	355	status = "disabled";
	356	};
3c3f6ad3 SH	357
3c3f6ad3 SH	358	hspi0: spi@fffc7000 {
7709c33b	359	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	360	reg = <0xfffc7000 0x18>;
3c3f6ad3	361	interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	362	#address-cells = <1>;
7709c33b GU	363	#size-cells = <0>;
3325cbe8	364	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
3c3f6ad3 SH	365	status = "disabled";
	366	};
	367
	368	hspi1: spi@fffc8000 {
7709c33b	369	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	370	reg = <0xfffc8000 0x18>;
3c3f6ad3	371	interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	372	#address-cells = <1>;
7709c33b GU	373	#size-cells = <0>;
3325cbe8	374	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
3c3f6ad3 SH	375	status = "disabled";
	376	};
	377
	378	hspi2: spi@fffc6000 {
7709c33b	379	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	380	reg = <0xfffc6000 0x18>;
3c3f6ad3	381	interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	382	#address-cells = <1>;
7709c33b GU	383	#size-cells = <0>;
3325cbe8	384	clocks = <&mstp0_clks R8A7779_CLK_HSPI>;
3c3f6ad3 SH	385	status = "disabled";
3c3f6ad3 SH	386	};
1e851538 SH	387
1e851538 SH	388	clocks {
5cc8afcb GU	389	#address-cells = <1>;
5cc8afcb GU	390	#size-cells = <1>;
1e851538 SH	391	ranges;
	392
	393	/* External root clock */
	394	extal_clk: extal_clk {
	395	compatible = "fixed-clock";
	396	#clock-cells = <0>;
	397	/* This value must be overriden by the board. */
	398	clock-frequency = <0>;
	399	clock-output-names = "extal";
	400	};
	401
	402	/* Special CPG clocks */
2909b874	403	cpg_clocks: clocks@ffc80000 {
1e851538	404	compatible = "renesas,r8a7779-cpg-clocks";
5cc8afcb	405	reg = <0xffc80000 0x30>;
1e851538 SH	406	clocks = <&extal_clk>;
	407	#clock-cells = <1>;
	408	clock-output-names = "plla", "z", "zs", "s",
	409	"s1", "p", "b", "out";
	410	};
	411
	412	/* Fixed factor clocks */
	413	i_clk: i_clk {
	414	compatible = "fixed-factor-clock";
	415	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	416	#clock-cells = <0>;
	417	clock-div = <2>;
	418	clock-mult = <1>;
	419	clock-output-names = "i";
	420	};
	421	s3_clk: s3_clk {
	422	compatible = "fixed-factor-clock";
	423	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	424	#clock-cells = <0>;
	425	clock-div = <8>;
	426	clock-mult = <1>;
	427	clock-output-names = "s3";
	428	};
	429	s4_clk: s4_clk {
	430	compatible = "fixed-factor-clock";
	431	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	432	#clock-cells = <0>;
	433	clock-div = <16>;
	434	clock-mult = <1>;
	435	clock-output-names = "s4";
	436	};
	437	g_clk: g_clk {
	438	compatible = "fixed-factor-clock";
	439	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	440	#clock-cells = <0>;
	441	clock-div = <24>;
	442	clock-mult = <1>;
	443	clock-output-names = "g";
	444	};
	445
	446	/* Gate clocks */
2909b874	447	mstp0_clks: clocks@ffc80030 {
1e851538 SH	448	compatible = "renesas,r8a7779-mstp-clocks",
1e851538 SH	449	"renesas,cpg-mstp-clocks";
5cc8afcb	450	reg = <0xffc80030 4>;
1e851538 SH	451	clocks = <&cpg_clocks R8A7779_CLK_S>,
	452	<&cpg_clocks R8A7779_CLK_P>,
	453	<&cpg_clocks R8A7779_CLK_P>,
	454	<&cpg_clocks R8A7779_CLK_P>,
	455	<&cpg_clocks R8A7779_CLK_S>,
	456	<&cpg_clocks R8A7779_CLK_S>,
	457	<&cpg_clocks R8A7779_CLK_S1>,
	458	<&cpg_clocks R8A7779_CLK_S1>,
	459	<&cpg_clocks R8A7779_CLK_S1>,
	460	<&cpg_clocks R8A7779_CLK_S1>,
	461	<&cpg_clocks R8A7779_CLK_S1>,
	462	<&cpg_clocks R8A7779_CLK_S1>,
	463	<&cpg_clocks R8A7779_CLK_P>,
	464	<&cpg_clocks R8A7779_CLK_P>,
	465	<&cpg_clocks R8A7779_CLK_P>,
	466	<&cpg_clocks R8A7779_CLK_P>;
	467	#clock-cells = <1>;
	468	renesas,clock-indices = <
	469	R8A7779_CLK_HSPI R8A7779_CLK_TMU2
	470	R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
	471	R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
	472	R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
	473	R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
	474	R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
	475	R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
	476	R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
	477	>;
	478	clock-output-names =
	479	"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
	480	"hscif0", "scif5", "scif4", "scif3", "scif2",
	481	"scif1", "scif0", "i2c3", "i2c2", "i2c1",
	482	"i2c0";
	483	};
2909b874	484	mstp1_clks: clocks@ffc80034 {
1e851538 SH	485	compatible = "renesas,r8a7779-mstp-clocks",
1e851538 SH	486	"renesas,cpg-mstp-clocks";
5cc8afcb	487	reg = <0xffc80034 4>, <0xffc80044 4>;
1e851538 SH	488	clocks = <&cpg_clocks R8A7779_CLK_P>,
	489	<&cpg_clocks R8A7779_CLK_P>,
	490	<&cpg_clocks R8A7779_CLK_S>,
	491	<&cpg_clocks R8A7779_CLK_S>,
	492	<&cpg_clocks R8A7779_CLK_S>,
	493	<&cpg_clocks R8A7779_CLK_S>,
	494	<&cpg_clocks R8A7779_CLK_P>,
	495	<&cpg_clocks R8A7779_CLK_P>,
	496	<&cpg_clocks R8A7779_CLK_P>,
	497	<&cpg_clocks R8A7779_CLK_S>;
	498	#clock-cells = <1>;
	499	renesas,clock-indices = <
	500	R8A7779_CLK_USB01 R8A7779_CLK_USB2
	501	R8A7779_CLK_DU R8A7779_CLK_VIN2
	502	R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
	503	R8A7779_CLK_ETHER R8A7779_CLK_SATA
	504	R8A7779_CLK_PCIE R8A7779_CLK_VIN3
	505	>;
	506	clock-output-names =
	507	"usb01", "usb2",
	508	"du", "vin2",
	509	"vin1", "vin0",
	510	"ether", "sata",
	511	"pcie", "vin3";
	512	};
2909b874	513	mstp3_clks: clocks@ffc8003c {
1e851538 SH	514	compatible = "renesas,r8a7779-mstp-clocks",
1e851538 SH	515	"renesas,cpg-mstp-clocks";
5cc8afcb	516	reg = <0xffc8003c 4>;
1e851538 SH	517	clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
	518	<&s4_clk>, <&s4_clk>;
	519	#clock-cells = <1>;
	520	renesas,clock-indices = <
	521	R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
	522	R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
	523	R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
	524	>;
	525	clock-output-names =
	526	"sdhi3", "sdhi2", "sdhi1", "sdhi0",
	527	"mmc1", "mmc0";
	528	};
	529	};
c58a1545	530	};