[deliverable/linux.git] / arch / arm / boot / dts / r8a7779.dtsi

/*
 * Device Tree Source for Renesas r8a7779
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 * Copyright (C) 2013 Simon Horman
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

/include/ "skeleton.dtsi"

#include <dt-bindings/clock/r8a7779-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7779";
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
		};
	};

	aliases {
		spi0 = &hspi0;
		spi1 = &hspi1;
		spi2 = &hspi2;
	};

        gic: interrupt-controller@f0001000 {
                compatible = "arm,cortex-a9-gic";
                #interrupt-cells = <3>;
                interrupt-controller;
                reg = <0xf0001000 0x1000>,
                      <0xf0000100 0x100>;
        };

	gpio0: gpio@ffc40000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc40000 0x2c>;
		interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@ffc41000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc41000 0x2c>;
		interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@ffc42000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc42000 0x2c>;
		interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@ffc43000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc43000 0x2c>;
		interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@ffc44000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc44000 0x2c>;
		interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio5: gpio@ffc45000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc45000 0x2c>;
		interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio6: gpio@ffc46000 {
		compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
		reg = <0xffc46000 0x2c>;
		interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 192 9>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	irqpin0: irqpin@fe780010 {
		compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
		#interrupt-cells = <2>;
		status = "disabled";
		interrupt-controller;
		reg = <0xfe78001c 4>,
			<0xfe780010 4>,
			<0xfe780024 4>,
			<0xfe780044 4>,
			<0xfe780064 4>;
		interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
			      0 28 IRQ_TYPE_LEVEL_HIGH
			      0 29 IRQ_TYPE_LEVEL_HIGH
			      0 30 IRQ_TYPE_LEVEL_HIGH>;
		sense-bitfield-width = <2>;
	};

	i2c0: i2c@ffc70000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc70000 0x1000>;
		interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c1: i2c@ffc71000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc71000 0x1000>;
		interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c2: i2c@ffc72000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc72000 0x1000>;
		interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	i2c3: i2c@ffc73000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7779";
		reg = <0xffc73000 0x1000>;
		interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
		status = "disabled";
	};

	pfc: pfc@fffc0000 {
		compatible = "renesas,pfc-r8a7779";
		reg = <0xfffc0000 0x23c>;
	};

	thermal@ffc48000 {
		compatible = "renesas,rcar-thermal";
		reg = <0xffc48000 0x38>;
	};

	sata: sata@fc600000 {
		compatible = "renesas,rcar-sata";
		reg = <0xfc600000 0x2000>;
		interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
	};

	sdhi0: sd@ffe4c000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4c000 0x100>;
		interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sdhi1: sd@ffe4d000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4d000 0x100>;
		interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sdhi2: sd@ffe4e000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4e000 0x100>;
		interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	sdhi3: sd@ffe4f000 {
		compatible = "renesas,sdhi-r8a7779";
		reg = <0xffe4f000 0x100>;
		interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
		cap-sd-highspeed;
		cap-sdio-irq;
		status = "disabled";
	};

	hspi0: spi@fffc7000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc7000 0x18>;
		interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	hspi1: spi@fffc8000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc8000 0x18>;
		interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	hspi2: spi@fffc6000 {
		compatible = "renesas,hspi-r8a7779", "renesas,hspi";
		reg = <0xfffc6000 0x18>;
		interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* External root clock */
		extal_clk: extal_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overriden by the board. */
			clock-frequency = <0>;
			clock-output-names = "extal";
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@0xe6150000 {
			compatible = "renesas,r8a7779-cpg-clocks";
			reg = <0 0xffc80000 0 0x30>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "plla", "z", "zs", "s",
					     "s1", "p", "b", "out";
		};

		/* Fixed factor clocks */
		i_clk: i_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "i";
		};
		s3_clk: s3_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "s3";
		};
		s4_clk: s4_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <16>;
			clock-mult = <1>;
			clock-output-names = "s4";
		};
		g_clk: g_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
			clock-output-names = "g";
		};

		/* Gate clocks */
		mstp0_clks: mstp0_clks {
			compatible = "renesas,r8a7779-mstp-clocks",
			             "renesas,cpg-mstp-clocks";
			reg = <0 0xffc80030 0 4>;
			clocks = <&cpg_clocks R8A7779_CLK_S>,
			         <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_S1>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7779_CLK_HSPI R8A7779_CLK_TMU2
				R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
				R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
				R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
				R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
				R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
				R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
				R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
			>;
			clock-output-names =
				"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
				"hscif0", "scif5", "scif4", "scif3", "scif2",
				"scif1", "scif0", "i2c3", "i2c2", "i2c1",
				"i2c0";
		};
		mstp1_clks: mstp1_clks {
			compatible = "renesas,r8a7779-mstp-clocks",
			             "renesas,cpg-mstp-clocks";
			reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
			clocks = <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_S>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_P>,
				 <&cpg_clocks R8A7779_CLK_S>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7779_CLK_USB01 R8A7779_CLK_USB2
				R8A7779_CLK_DU R8A7779_CLK_VIN2
				R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
				R8A7779_CLK_ETHER R8A7779_CLK_SATA
				R8A7779_CLK_PCIE R8A7779_CLK_VIN3
			>;
			clock-output-names =
				"usb01", "usb2",
				"du", "vin2",
				"vin1", "vin0",
				"ether", "sata",
				"pcie", "vin3";
		};
		mstp3_clks: mstp3_clks {
			compatible = "renesas,r8a7779-mstp-clocks",
			             "renesas,cpg-mstp-clocks";
			reg = <0 0xffc8003c 0 4>;
			clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
				 <&s4_clk>, <&s4_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
				R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
				R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
			>;
			clock-output-names =
				"sdhi3", "sdhi2", "sdhi1", "sdhi0",
				"mmc1", "mmc0";
		};
	};
};
Commit	Line	Data
c58a1545	1	/*
349f556e	2	* Device Tree Source for Renesas r8a7779
c58a1545 SH	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	* Copyright (C) 2013 Simon Horman
	6	*
	7	* This file is licensed under the terms of the GNU General Public License
	8	* version 2. This program is licensed "as is" without any warranty of any
	9	* kind, whether express or implied.
	10	*/
	11
	12	/include/ "skeleton.dtsi"
	13
1e851538	14	#include <dt-bindings/clock/r8a7779-clock.h>
5f75e73c LP	15	#include <dt-bindings/interrupt-controller/irq.h>
5f75e73c LP	16
c58a1545 SH	17	/ {
c58a1545 SH	18	compatible = "renesas,r8a7779";
9ff254ad	19	interrupt-parent = <&gic>;
c58a1545 SH	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu@0 {
	26	device_type = "cpu";
	27	compatible = "arm,cortex-a9";
	28	reg = <0>;
	29	};
	30	cpu@1 {
	31	device_type = "cpu";
	32	compatible = "arm,cortex-a9";
	33	reg = <1>;
	34	};
	35	cpu@2 {
	36	device_type = "cpu";
	37	compatible = "arm,cortex-a9";
	38	reg = <2>;
	39	};
	40	cpu@3 {
	41	device_type = "cpu";
	42	compatible = "arm,cortex-a9";
	43	reg = <3>;
	44	};
	45	};
	46
3c3f6ad3 SH	47	aliases {
	48	spi0 = &hspi0;
	49	spi1 = &hspi1;
	50	spi2 = &hspi2;
	51	};
	52
c58a1545 SH	53	gic: interrupt-controller@f0001000 {
	54	compatible = "arm,cortex-a9-gic";
	55	#interrupt-cells = <3>;
	56	interrupt-controller;
	57	reg = <0xf0001000 0x1000>,
	58	<0xf0000100 0x100>;
	59	};
10e8d4f6	60
f5c771b5 LP	61	gpio0: gpio@ffc40000 {
	62	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	63	reg = <0xffc40000 0x2c>;
5f75e73c	64	interrupts = <0 141 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	65	#gpio-cells = <2>;
	66	gpio-controller;
	67	gpio-ranges = <&pfc 0 0 32>;
	68	#interrupt-cells = <2>;
	69	interrupt-controller;
	70	};
	71
	72	gpio1: gpio@ffc41000 {
	73	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	74	reg = <0xffc41000 0x2c>;
5f75e73c	75	interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	76	#gpio-cells = <2>;
	77	gpio-controller;
	78	gpio-ranges = <&pfc 0 32 32>;
	79	#interrupt-cells = <2>;
	80	interrupt-controller;
	81	};
	82
	83	gpio2: gpio@ffc42000 {
	84	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	85	reg = <0xffc42000 0x2c>;
5f75e73c	86	interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	87	#gpio-cells = <2>;
	88	gpio-controller;
	89	gpio-ranges = <&pfc 0 64 32>;
	90	#interrupt-cells = <2>;
	91	interrupt-controller;
	92	};
	93
	94	gpio3: gpio@ffc43000 {
	95	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	96	reg = <0xffc43000 0x2c>;
5f75e73c	97	interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	98	#gpio-cells = <2>;
	99	gpio-controller;
	100	gpio-ranges = <&pfc 0 96 32>;
	101	#interrupt-cells = <2>;
	102	interrupt-controller;
	103	};
	104
	105	gpio4: gpio@ffc44000 {
	106	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	107	reg = <0xffc44000 0x2c>;
5f75e73c	108	interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	109	#gpio-cells = <2>;
	110	gpio-controller;
	111	gpio-ranges = <&pfc 0 128 32>;
	112	#interrupt-cells = <2>;
	113	interrupt-controller;
	114	};
	115
	116	gpio5: gpio@ffc45000 {
	117	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	118	reg = <0xffc45000 0x2c>;
5f75e73c	119	interrupts = <0 146 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	120	#gpio-cells = <2>;
	121	gpio-controller;
	122	gpio-ranges = <&pfc 0 160 32>;
	123	#interrupt-cells = <2>;
	124	interrupt-controller;
	125	};
	126
	127	gpio6: gpio@ffc46000 {
	128	compatible = "renesas,gpio-r8a7779", "renesas,gpio-rcar";
	129	reg = <0xffc46000 0x2c>;
5f75e73c	130	interrupts = <0 147 IRQ_TYPE_LEVEL_HIGH>;
f5c771b5 LP	131	#gpio-cells = <2>;
	132	gpio-controller;
	133	gpio-ranges = <&pfc 0 192 9>;
	134	#interrupt-cells = <2>;
	135	interrupt-controller;
	136	};
	137
24603f3c	138	irqpin0: irqpin@fe780010 {
11ef0340	139	compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin";
24603f3c	140	#interrupt-cells = <2>;
84b47dfc	141	status = "disabled";
24603f3c GL	142	interrupt-controller;
	143	reg = <0xfe78001c 4>,
	144	<0xfe780010 4>,
	145	<0xfe780024 4>,
	146	<0xfe780044 4>,
	147	<0xfe780064 4>;
5f75e73c LP	148	interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH
	149	0 28 IRQ_TYPE_LEVEL_HIGH
	150	0 29 IRQ_TYPE_LEVEL_HIGH
	151	0 30 IRQ_TYPE_LEVEL_HIGH>;
24603f3c GL	152	sense-bitfield-width = <2>;
	153	};
	154
98724b7e	155	i2c0: i2c@ffc70000 {
10e8d4f6 SH	156	#address-cells = <1>;
10e8d4f6 SH	157	#size-cells = <0>;
6363070e	158	compatible = "renesas,i2c-r8a7779";
10e8d4f6	159	reg = <0xffc70000 0x1000>;
5f75e73c	160	interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	161	status = "disabled";
10e8d4f6 SH	162	};
10e8d4f6 SH	163
98724b7e	164	i2c1: i2c@ffc71000 {
10e8d4f6 SH	165	#address-cells = <1>;
10e8d4f6 SH	166	#size-cells = <0>;
6363070e	167	compatible = "renesas,i2c-r8a7779";
10e8d4f6	168	reg = <0xffc71000 0x1000>;
5f75e73c	169	interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	170	status = "disabled";
10e8d4f6 SH	171	};
10e8d4f6 SH	172
98724b7e	173	i2c2: i2c@ffc72000 {
10e8d4f6 SH	174	#address-cells = <1>;
10e8d4f6 SH	175	#size-cells = <0>;
6363070e	176	compatible = "renesas,i2c-r8a7779";
10e8d4f6	177	reg = <0xffc72000 0x1000>;
5f75e73c	178	interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	179	status = "disabled";
10e8d4f6 SH	180	};
10e8d4f6 SH	181
98724b7e	182	i2c3: i2c@ffc73000 {
10e8d4f6 SH	183	#address-cells = <1>;
10e8d4f6 SH	184	#size-cells = <0>;
6363070e	185	compatible = "renesas,i2c-r8a7779";
10e8d4f6	186	reg = <0xffc73000 0x1000>;
5f75e73c	187	interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
eda3a4fa	188	status = "disabled";
10e8d4f6	189	};
25a65975	190
3ab03d01 LP	191	pfc: pfc@fffc0000 {
	192	compatible = "renesas,pfc-r8a7779";
	193	reg = <0xfffc0000 0x23c>;
	194	};
	195
25a65975 KM	196	thermal@ffc48000 {
	197	compatible = "renesas,rcar-thermal";
	198	reg = <0xffc48000 0x38>;
	199	};
7840a65a VB	200
	201	sata: sata@fc600000 {
	202	compatible = "renesas,rcar-sata";
	203	reg = <0xfc600000 0x2000>;
5f75e73c	204	interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
7840a65a	205	};
c4866e70	206
2624705c	207	sdhi0: sd@ffe4c000 {
c4866e70 KM	208	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	209	reg = <0xffe4c000 0x100>;
5f75e73c	210	interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH>;
c4866e70 KM	211	cap-sd-highspeed;
	212	cap-sdio-irq;
	213	status = "disabled";
	214	};
	215
2624705c	216	sdhi1: sd@ffe4d000 {
c4866e70 KM	217	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	218	reg = <0xffe4d000 0x100>;
5f75e73c	219	interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
c4866e70 KM	220	cap-sd-highspeed;
	221	cap-sdio-irq;
	222	status = "disabled";
	223	};
	224
2624705c	225	sdhi2: sd@ffe4e000 {
c4866e70 KM	226	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	227	reg = <0xffe4e000 0x100>;
5f75e73c	228	interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
c4866e70 KM	229	cap-sd-highspeed;
	230	cap-sdio-irq;
	231	status = "disabled";
	232	};
	233
2624705c	234	sdhi3: sd@ffe4f000 {
c4866e70 KM	235	compatible = "renesas,sdhi-r8a7779";
c4866e70 KM	236	reg = <0xffe4f000 0x100>;
5f75e73c	237	interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
c4866e70 KM	238	cap-sd-highspeed;
	239	cap-sdio-irq;
	240	status = "disabled";
	241	};
3c3f6ad3 SH	242
3c3f6ad3 SH	243	hspi0: spi@fffc7000 {
7709c33b	244	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	245	reg = <0xfffc7000 0x18>;
3c3f6ad3	246	interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	247	#address-cells = <1>;
7709c33b GU	248	#size-cells = <0>;
3c3f6ad3 SH	249	status = "disabled";
	250	};
	251
	252	hspi1: spi@fffc8000 {
7709c33b	253	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	254	reg = <0xfffc8000 0x18>;
3c3f6ad3	255	interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	256	#address-cells = <1>;
7709c33b GU	257	#size-cells = <0>;
3c3f6ad3 SH	258	status = "disabled";
	259	};
	260
	261	hspi2: spi@fffc6000 {
7709c33b	262	compatible = "renesas,hspi-r8a7779", "renesas,hspi";
3c3f6ad3	263	reg = <0xfffc6000 0x18>;
3c3f6ad3	264	interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
7709c33b GU	265	#address-cells = <1>;
7709c33b GU	266	#size-cells = <0>;
3c3f6ad3 SH	267	status = "disabled";
3c3f6ad3 SH	268	};
1e851538 SH	269
	270	clocks {
	271	#address-cells = <2>;
	272	#size-cells = <2>;
	273	ranges;
	274
	275	/* External root clock */
	276	extal_clk: extal_clk {
	277	compatible = "fixed-clock";
	278	#clock-cells = <0>;
	279	/* This value must be overriden by the board. */
	280	clock-frequency = <0>;
	281	clock-output-names = "extal";
	282	};
	283
	284	/* Special CPG clocks */
	285	cpg_clocks: cpg_clocks@0xe6150000 {
	286	compatible = "renesas,r8a7779-cpg-clocks";
	287	reg = <0 0xffc80000 0 0x30>;
	288	clocks = <&extal_clk>;
	289	#clock-cells = <1>;
	290	clock-output-names = "plla", "z", "zs", "s",
	291	"s1", "p", "b", "out";
	292	};
	293
	294	/* Fixed factor clocks */
	295	i_clk: i_clk {
	296	compatible = "fixed-factor-clock";
	297	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	298	#clock-cells = <0>;
	299	clock-div = <2>;
	300	clock-mult = <1>;
	301	clock-output-names = "i";
	302	};
	303	s3_clk: s3_clk {
	304	compatible = "fixed-factor-clock";
	305	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	306	#clock-cells = <0>;
	307	clock-div = <8>;
	308	clock-mult = <1>;
	309	clock-output-names = "s3";
	310	};
	311	s4_clk: s4_clk {
	312	compatible = "fixed-factor-clock";
	313	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	314	#clock-cells = <0>;
	315	clock-div = <16>;
	316	clock-mult = <1>;
	317	clock-output-names = "s4";
	318	};
	319	g_clk: g_clk {
	320	compatible = "fixed-factor-clock";
	321	clocks = <&cpg_clocks R8A7779_CLK_PLLA>;
	322	#clock-cells = <0>;
	323	clock-div = <24>;
	324	clock-mult = <1>;
	325	clock-output-names = "g";
	326	};
	327
	328	/* Gate clocks */
	329	mstp0_clks: mstp0_clks {
	330	compatible = "renesas,r8a7779-mstp-clocks",
	331	"renesas,cpg-mstp-clocks";
	332	reg = <0 0xffc80030 0 4>;
333	clocks = <&cpg_clocks R8A7779_CLK_S>,
334	<&cpg_clocks R8A7779_CLK_P>,
335	<&cpg_clocks R8A7779_CLK_P>,
336	<&cpg_clocks R8A7779_CLK_P>,
337	<&cpg_clocks R8A7779_CLK_S>,
338	<&cpg_clocks R8A7779_CLK_S>,
339	<&cpg_clocks R8A7779_CLK_S1>,
340	<&cpg_clocks R8A7779_CLK_S1>,
341	<&cpg_clocks R8A7779_CLK_S1>,
342	<&cpg_clocks R8A7779_CLK_S1>,
343	<&cpg_clocks R8A7779_CLK_S1>,
344	<&cpg_clocks R8A7779_CLK_S1>,
345	<&cpg_clocks R8A7779_CLK_P>,
346	<&cpg_clocks R8A7779_CLK_P>,
347	<&cpg_clocks R8A7779_CLK_P>,
348	<&cpg_clocks R8A7779_CLK_P>;
349	#clock-cells = <1>;
350	renesas,clock-indices = <
351	R8A7779_CLK_HSPI R8A7779_CLK_TMU2
352	R8A7779_CLK_TMU1 R8A7779_CLK_TMU0
353	R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0
354	R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4
355	R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2
356	R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0
357	R8A7779_CLK_I2C3 R8A7779_CLK_I2C2
358	R8A7779_CLK_I2C1 R8A7779_CLK_I2C0
359	>;
360	clock-output-names =
361	"hspi", "tmu2", "tmu1", "tmu0", "hscif1",
362	"hscif0", "scif5", "scif4", "scif3", "scif2",
363	"scif1", "scif0", "i2c3", "i2c2", "i2c1",
364	"i2c0";
365	};
366	mstp1_clks: mstp1_clks {
367	compatible = "renesas,r8a7779-mstp-clocks",
368	"renesas,cpg-mstp-clocks";
369	reg = <0 0xffc80034 0 4>, <0 0xffc80044 0 4>;
370	clocks = <&cpg_clocks R8A7779_CLK_P>,
371	<&cpg_clocks R8A7779_CLK_P>,
372	<&cpg_clocks R8A7779_CLK_S>,
373	<&cpg_clocks R8A7779_CLK_S>,
374	<&cpg_clocks R8A7779_CLK_S>,
375	<&cpg_clocks R8A7779_CLK_S>,
376	<&cpg_clocks R8A7779_CLK_P>,
377	<&cpg_clocks R8A7779_CLK_P>,
378	<&cpg_clocks R8A7779_CLK_P>,
379	<&cpg_clocks R8A7779_CLK_S>;
380	#clock-cells = <1>;
381	renesas,clock-indices = <
382	R8A7779_CLK_USB01 R8A7779_CLK_USB2
383	R8A7779_CLK_DU R8A7779_CLK_VIN2
384	R8A7779_CLK_VIN1 R8A7779_CLK_VIN0
385	R8A7779_CLK_ETHER R8A7779_CLK_SATA
386	R8A7779_CLK_PCIE R8A7779_CLK_VIN3
387	>;
388	clock-output-names =
389	"usb01", "usb2",
390	"du", "vin2",
391	"vin1", "vin0",
392	"ether", "sata",
393	"pcie", "vin3";
394	};
395	mstp3_clks: mstp3_clks {
396	compatible = "renesas,r8a7779-mstp-clocks",
397	"renesas,cpg-mstp-clocks";
398	reg = <0 0xffc8003c 0 4>;
399	clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
400	<&s4_clk>, <&s4_clk>;
401	#clock-cells = <1>;
402	renesas,clock-indices = <
403	R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2
404	R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0
405	R8A7779_CLK_MMC1 R8A7779_CLK_MMC0
406	>;
407	clock-output-names =
408	"sdhi3", "sdhi2", "sdhi1", "sdhi0",
409	"mmc1", "mmc0";
410	};
411	};
c58a1545	412	};