[deliverable/linux.git] / arch / arm / boot / dts / r8a7790.dtsi

/*
 * Device Tree Source for the r8a7790 SoC
 *
 * Copyright (C) 2013 Renesas Solutions Corp.
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2.  This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <dt-bindings/clock/r8a7790-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	compatible = "renesas,r8a7790";
	interrupt-parent = <&gic>;
	#address-cells = <2>;
	#size-cells = <2>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <0>;
			clock-frequency = <1300000000>;
		};

		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <1>;
			clock-frequency = <1300000000>;
		};

		cpu2: cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <2>;
			clock-frequency = <1300000000>;
		};

		cpu3: cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a15";
			reg = <3>;
			clock-frequency = <1300000000>;
		};

		cpu4: cpu@4 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x100>;
			clock-frequency = <780000000>;
		};

		cpu5: cpu@5 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x101>;
			clock-frequency = <780000000>;
		};

		cpu6: cpu@6 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x102>;
			clock-frequency = <780000000>;
		};

		cpu7: cpu@7 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x103>;
			clock-frequency = <780000000>;
		};
	};

	gic: interrupt-controller@f1001000 {
		compatible = "arm,cortex-a15-gic";
		#interrupt-cells = <3>;
		#address-cells = <0>;
		interrupt-controller;
		reg = <0 0xf1001000 0 0x1000>,
			<0 0xf1002000 0 0x1000>,
			<0 0xf1004000 0 0x2000>,
			<0 0xf1006000 0 0x2000>;
		interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	gpio0: gpio@e6050000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xe6050000 0 0x50>;
		interrupt-parent = <&gic>;
		interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 0 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio1: gpio@e6051000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xe6051000 0 0x50>;
		interrupt-parent = <&gic>;
		interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 32 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio2: gpio@e6052000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xe6052000 0 0x50>;
		interrupt-parent = <&gic>;
		interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 64 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio3: gpio@e6053000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xe6053000 0 0x50>;
		interrupt-parent = <&gic>;
		interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 96 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio4: gpio@e6054000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xe6054000 0 0x50>;
		interrupt-parent = <&gic>;
		interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 128 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	gpio5: gpio@e6055000 {
		compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
		reg = <0 0xe6055000 0 0x50>;
		interrupt-parent = <&gic>;
		interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		gpio-ranges = <&pfc 0 160 32>;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	thermal@e61f0000 {
		compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
		reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
		interrupt-parent = <&gic>;
		interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
			     <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
	};

	irqc0: interrupt-controller@e61c0000 {
		compatible = "renesas,irqc-r8a7790", "renesas,irqc";
		#interrupt-cells = <2>;
		interrupt-controller;
		reg = <0 0xe61c0000 0 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
			     <0 1 IRQ_TYPE_LEVEL_HIGH>,
			     <0 2 IRQ_TYPE_LEVEL_HIGH>,
			     <0 3 IRQ_TYPE_LEVEL_HIGH>;
	};

	i2c0: i2c@e6508000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7790";
		reg = <0 0xe6508000 0 0x40>;
		interrupt-parent = <&gic>;
		interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_I2C0>;
		status = "disabled";
	};

	i2c1: i2c@e6518000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7790";
		reg = <0 0xe6518000 0 0x40>;
		interrupt-parent = <&gic>;
		interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_I2C1>;
		status = "disabled";
	};

	i2c2: i2c@e6530000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7790";
		reg = <0 0xe6530000 0 0x40>;
		interrupt-parent = <&gic>;
		interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_I2C2>;
		status = "disabled";
	};

	i2c3: i2c@e6540000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "renesas,i2c-r8a7790";
		reg = <0 0xe6540000 0 0x40>;
		interrupt-parent = <&gic>;
		interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_I2C3>;
		status = "disabled";
	};

	mmcif0: mmcif@ee200000 {
		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
		reg = <0 0xee200000 0 0x80>;
		interrupt-parent = <&gic>;
		interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
		reg-io-width = <4>;
		status = "disabled";
	};

	mmcif1: mmc@ee220000 {
		compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
		reg = <0 0xee220000 0 0x80>;
		interrupt-parent = <&gic>;
		interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
		reg-io-width = <4>;
		status = "disabled";
	};

	pfc: pfc@e6060000 {
		compatible = "renesas,pfc-r8a7790";
		reg = <0 0xe6060000 0 0x250>;
	};

	sdhi0: sd@ee100000 {
		compatible = "renesas,sdhi-r8a7790";
		reg = <0 0xee100000 0 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi1: sd@ee120000 {
		compatible = "renesas,sdhi-r8a7790";
		reg = <0 0xee120000 0 0x200>;
		interrupt-parent = <&gic>;
		interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi2: sd@ee140000 {
		compatible = "renesas,sdhi-r8a7790";
		reg = <0 0xee140000 0 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
		cap-sd-highspeed;
		status = "disabled";
	};

	sdhi3: sd@ee160000 {
		compatible = "renesas,sdhi-r8a7790";
		reg = <0 0xee160000 0 0x100>;
		interrupt-parent = <&gic>;
		interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
		cap-sd-highspeed;
		status = "disabled";
	};

	clocks {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		/* External root clock */
		extal_clk: extal_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			/* This value must be overriden by the board. */
			clock-frequency = <0>;
			clock-output-names = "extal";
		};

		/* Special CPG clocks */
		cpg_clocks: cpg_clocks@e6150000 {
			compatible = "renesas,r8a7790-cpg-clocks",
				     "renesas,rcar-gen2-cpg-clocks";
			reg = <0 0xe6150000 0 0x1000>;
			clocks = <&extal_clk>;
			#clock-cells = <1>;
			clock-output-names = "main", "pll0", "pll1", "pll3",
					     "lb", "qspi", "sdh", "sd0", "sd1",
					     "z";
		};

		/* Variable factor clocks */
		sd2_clk: sd2_clk@e6150078 {
			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150078 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sd2";
		};
		sd3_clk: sd3_clk@e615007c {
			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe615007c 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "sd3";
		};
		mmc0_clk: mmc0_clk@e6150240 {
			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150240 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "mmc0";
		};
		mmc1_clk: mmc1_clk@e6150244 {
			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150244 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "mmc1";
		};
		ssp_clk: ssp_clk@e6150248 {
			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe6150248 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "ssp";
		};
		ssprs_clk: ssprs_clk@e615024c {
			compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
			reg = <0 0xe615024c 0 4>;
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-output-names = "ssprs";
		};

		/* Fixed factor clocks */
		pll1_div2_clk: pll1_div2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "pll1_div2";
		};
		z2_clk: z2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "z2";
		};
		zg_clk: zg_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <3>;
			clock-mult = <1>;
			clock-output-names = "zg";
		};
		zx_clk: zx_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <3>;
			clock-mult = <1>;
			clock-output-names = "zx";
		};
		zs_clk: zs_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <6>;
			clock-mult = <1>;
			clock-output-names = "zs";
		};
		hp_clk: hp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <12>;
			clock-mult = <1>;
			clock-output-names = "hp";
		};
		i_clk: i_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "i";
		};
		b_clk: b_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <12>;
			clock-mult = <1>;
			clock-output-names = "b";
		};
		p_clk: p_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <24>;
			clock-mult = <1>;
			clock-output-names = "p";
		};
		cl_clk: cl_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <48>;
			clock-mult = <1>;
			clock-output-names = "cl";
		};
		m2_clk: m2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "m2";
		};
		imp_clk: imp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clock-output-names = "imp";
		};
		rclk_clk: rclk_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <(48 * 1024)>;
			clock-mult = <1>;
			clock-output-names = "rclk";
		};
		oscclk_clk: oscclk_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
			#clock-cells = <0>;
			clock-div = <(12 * 1024)>;
			clock-mult = <1>;
			clock-output-names = "oscclk";
		};
		zb3_clk: zb3_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
			#clock-cells = <0>;
			clock-div = <4>;
			clock-mult = <1>;
			clock-output-names = "zb3";
		};
		zb3d2_clk: zb3d2_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "zb3d2";
		};
		ddr_clk: ddr_clk {
			compatible = "fixed-factor-clock";
			clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
			#clock-cells = <0>;
			clock-div = <8>;
			clock-mult = <1>;
			clock-output-names = "ddr";
		};
		mp_clk: mp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&pll1_div2_clk>;
			#clock-cells = <0>;
			clock-div = <15>;
			clock-mult = <1>;
			clock-output-names = "mp";
		};
		cp_clk: cp_clk {
			compatible = "fixed-factor-clock";
			clocks = <&extal_clk>;
			#clock-cells = <0>;
			clock-div = <2>;
			clock-mult = <1>;
			clock-output-names = "cp";
		};

		/* Gate clocks */
		mstp0_clks: mstp0_clks@e6150130 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
			clocks = <&mp_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
			clock-output-names = "msiof0";
		};
		mstp1_clks: mstp1_clks@e6150134 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
			clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
				 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
				 <&zs_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
				R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
				R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
			>;
			clock-output-names =
				"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
				"vsp1-du0", "vsp1-rt", "vsp1-sy";
		};
		mstp2_clks: mstp2_clks@e6150138 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
			clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
				 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
				R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
				R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
			>;
			clock-output-names =
				"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
				"scifb1", "msiof1", "msiof3", "scifb2";
		};
		mstp3_clks: mstp3_clks@e615013c {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
			clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
				 <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
				 <&mmc0_clk>, <&rclk_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
				R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
				R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
			>;
			clock-output-names =
				"tpu0", "mmcif1", "sdhi3", "sdhi2",
				"sdhi1", "sdhi0", "mmcif0", "cmt1";
		};
		mstp5_clks: mstp5_clks@e6150144 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
			clocks = <&extal_clk>, <&p_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
			clock-output-names = "thermal", "pwm";
		};
		mstp7_clks: mstp7_clks@e615014c {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
			clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
				 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
				 <&zx_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
				R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
				R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
				R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
			>;
			clock-output-names =
				"ehci", "hsusb", "hscif1", "hscif0", "scif1",
				"scif0", "du2", "du1", "du0", "lvds1", "lvds0";
		};
		mstp8_clks: mstp8_clks@e6150990 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
			clocks = <&p_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <R8A7790_CLK_ETHER>;
			clock-output-names = "ether";
		};
		mstp9_clks: mstp9_clks@e6150994 {
			compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
			reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
			clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
				 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
			#clock-cells = <1>;
			renesas,clock-indices = <
				R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
				R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
				R8A7790_CLK_I2C0
			>;
			clock-output-names =
				"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
		};
	};
};
Commit	Line	Data
0468b2d6 MD	1	/*
	2	* Device Tree Source for the r8a7790 SoC
	3	*
	4	* Copyright (C) 2013 Renesas Solutions Corp.
	5	*
	6	* This file is licensed under the terms of the GNU General Public License
	7	* version 2. This program is licensed "as is" without any warranty of any
	8	* kind, whether express or implied.
	9	*/
	10
22a1f595	11	#include <dt-bindings/clock/r8a7790-clock.h>
5f75e73c LP	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
	13	#include <dt-bindings/interrupt-controller/irq.h>
	14
0468b2d6 MD	15	/ {
	16	compatible = "renesas,r8a7790";
	17	interrupt-parent = <&gic>;
8585deb1 TY	18	#address-cells = <2>;
8585deb1 TY	19	#size-cells = <2>;
0468b2d6 MD	20
	21	cpus {
	22	#address-cells = <1>;
	23	#size-cells = <0>;
	24
	25	cpu0: cpu@0 {
	26	device_type = "cpu";
	27	compatible = "arm,cortex-a15";
	28	reg = <0>;
	29	clock-frequency = <1300000000>;
	30	};
c1f95979 MD	31
	32	cpu1: cpu@1 {
	33	device_type = "cpu";
	34	compatible = "arm,cortex-a15";
	35	reg = <1>;
	36	clock-frequency = <1300000000>;
	37	};
	38
	39	cpu2: cpu@2 {
	40	device_type = "cpu";
	41	compatible = "arm,cortex-a15";
	42	reg = <2>;
	43	clock-frequency = <1300000000>;
	44	};
	45
	46	cpu3: cpu@3 {
	47	device_type = "cpu";
	48	compatible = "arm,cortex-a15";
	49	reg = <3>;
	50	clock-frequency = <1300000000>;
	51	};
2007e74c MD	52
	53	cpu4: cpu@4 {
	54	device_type = "cpu";
	55	compatible = "arm,cortex-a7";
	56	reg = <0x100>;
	57	clock-frequency = <780000000>;
	58	};
	59
	60	cpu5: cpu@5 {
	61	device_type = "cpu";
	62	compatible = "arm,cortex-a7";
	63	reg = <0x101>;
	64	clock-frequency = <780000000>;
	65	};
	66
	67	cpu6: cpu@6 {
	68	device_type = "cpu";
	69	compatible = "arm,cortex-a7";
	70	reg = <0x102>;
	71	clock-frequency = <780000000>;
	72	};
	73
	74	cpu7: cpu@7 {
	75	device_type = "cpu";
	76	compatible = "arm,cortex-a7";
	77	reg = <0x103>;
	78	clock-frequency = <780000000>;
	79	};
0468b2d6 MD	80	};
	81
	82	gic: interrupt-controller@f1001000 {
	83	compatible = "arm,cortex-a15-gic";
	84	#interrupt-cells = <3>;
	85	#address-cells = <0>;
	86	interrupt-controller;
8585deb1 TY	87	reg = <0 0xf1001000 0 0x1000>,
	88	<0 0xf1002000 0 0x1000>,
	89	<0 0xf1004000 0 0x2000>,
	90	<0 0xf1006000 0 0x2000>;
5f75e73c	91	interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
0468b2d6 MD	92	};
0468b2d6 MD	93
23de2278	94	gpio0: gpio@e6050000 {
f98e10c8	95	compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278	96	reg = <0 0xe6050000 0 0x50>;
f98e10c8	97	interrupt-parent = <&gic>;
5f75e73c	98	interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8 LP	99	#gpio-cells = <2>;
	100	gpio-controller;
	101	gpio-ranges = <&pfc 0 0 32>;
	102	#interrupt-cells = <2>;
	103	interrupt-controller;
	104	};
	105
23de2278	106	gpio1: gpio@e6051000 {
f98e10c8	107	compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278	108	reg = <0 0xe6051000 0 0x50>;
f98e10c8	109	interrupt-parent = <&gic>;
5f75e73c	110	interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8 LP	111	#gpio-cells = <2>;
	112	gpio-controller;
	113	gpio-ranges = <&pfc 0 32 32>;
	114	#interrupt-cells = <2>;
	115	interrupt-controller;
	116	};
	117
23de2278	118	gpio2: gpio@e6052000 {
f98e10c8	119	compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278	120	reg = <0 0xe6052000 0 0x50>;
f98e10c8	121	interrupt-parent = <&gic>;
5f75e73c	122	interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8 LP	123	#gpio-cells = <2>;
	124	gpio-controller;
	125	gpio-ranges = <&pfc 0 64 32>;
	126	#interrupt-cells = <2>;
	127	interrupt-controller;
	128	};
	129
23de2278	130	gpio3: gpio@e6053000 {
f98e10c8	131	compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278	132	reg = <0 0xe6053000 0 0x50>;
f98e10c8	133	interrupt-parent = <&gic>;
5f75e73c	134	interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8 LP	135	#gpio-cells = <2>;
	136	gpio-controller;
	137	gpio-ranges = <&pfc 0 96 32>;
	138	#interrupt-cells = <2>;
	139	interrupt-controller;
	140	};
	141
23de2278	142	gpio4: gpio@e6054000 {
f98e10c8	143	compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278	144	reg = <0 0xe6054000 0 0x50>;
f98e10c8	145	interrupt-parent = <&gic>;
5f75e73c	146	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8 LP	147	#gpio-cells = <2>;
	148	gpio-controller;
	149	gpio-ranges = <&pfc 0 128 32>;
	150	#interrupt-cells = <2>;
	151	interrupt-controller;
	152	};
	153
23de2278	154	gpio5: gpio@e6055000 {
f98e10c8	155	compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278	156	reg = <0 0xe6055000 0 0x50>;
f98e10c8	157	interrupt-parent = <&gic>;
5f75e73c	158	interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8 LP	159	#gpio-cells = <2>;
	160	gpio-controller;
	161	gpio-ranges = <&pfc 0 160 32>;
	162	#interrupt-cells = <2>;
	163	interrupt-controller;
	164	};
	165
03e2f56b MD	166	thermal@e61f0000 {
	167	compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
	168	reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
	169	interrupt-parent = <&gic>;
	170	interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
	171	};
	172
0468b2d6 MD	173	timer {
0468b2d6 MD	174	compatible = "arm,armv7-timer";
5f75e73c LP	175	interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	176	<1 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	177	<1 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>,
	178	<1 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_LOW)>;
0468b2d6	179	};
8f5ec0a5 MD	180
8f5ec0a5 MD	181	irqc0: interrupt-controller@e61c0000 {
220fc352	182	compatible = "renesas,irqc-r8a7790", "renesas,irqc";
8f5ec0a5 MD	183	#interrupt-cells = <2>;
8f5ec0a5 MD	184	interrupt-controller;
8585deb1	185	reg = <0 0xe61c0000 0 0x200>;
8f5ec0a5	186	interrupt-parent = <&gic>;
5f75e73c LP	187	interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
	188	<0 1 IRQ_TYPE_LEVEL_HIGH>,
	189	<0 2 IRQ_TYPE_LEVEL_HIGH>,
	190	<0 3 IRQ_TYPE_LEVEL_HIGH>;
8f5ec0a5	191	};
8c9b1aa4	192
edd2b9f4 GL	193	i2c0: i2c@e6508000 {
	194	#address-cells = <1>;
	195	#size-cells = <0>;
	196	compatible = "renesas,i2c-r8a7790";
	197	reg = <0 0xe6508000 0 0x40>;
	198	interrupt-parent = <&gic>;
5f75e73c	199	interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	200	clocks = <&mstp3_clks R8A7790_CLK_I2C0>;
edd2b9f4 GL	201	status = "disabled";
	202	};
	203
	204	i2c1: i2c@e6518000 {
	205	#address-cells = <1>;
	206	#size-cells = <0>;
	207	compatible = "renesas,i2c-r8a7790";
	208	reg = <0 0xe6518000 0 0x40>;
	209	interrupt-parent = <&gic>;
5f75e73c	210	interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	211	clocks = <&mstp3_clks R8A7790_CLK_I2C1>;
edd2b9f4 GL	212	status = "disabled";
	213	};
	214
	215	i2c2: i2c@e6530000 {
	216	#address-cells = <1>;
	217	#size-cells = <0>;
	218	compatible = "renesas,i2c-r8a7790";
	219	reg = <0 0xe6530000 0 0x40>;
	220	interrupt-parent = <&gic>;
5f75e73c	221	interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	222	clocks = <&mstp3_clks R8A7790_CLK_I2C2>;
edd2b9f4 GL	223	status = "disabled";
	224	};
	225
	226	i2c3: i2c@e6540000 {
	227	#address-cells = <1>;
	228	#size-cells = <0>;
	229	compatible = "renesas,i2c-r8a7790";
	230	reg = <0 0xe6540000 0 0x40>;
	231	interrupt-parent = <&gic>;
5f75e73c	232	interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	233	clocks = <&mstp3_clks R8A7790_CLK_I2C3>;
edd2b9f4 GL	234	status = "disabled";
	235	};
	236
8c9b1aa4	237	mmcif0: mmcif@ee200000 {
063e8560	238	compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 GL	239	reg = <0 0xee200000 0 0x80>;
8c9b1aa4 GL	240	interrupt-parent = <&gic>;
5f75e73c	241	interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	242	clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
8c9b1aa4 GL	243	reg-io-width = <4>;
	244	status = "disabled";
	245	};
	246
b718aa44	247	mmcif1: mmc@ee220000 {
063e8560	248	compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 GL	249	reg = <0 0xee220000 0 0x80>;
8c9b1aa4 GL	250	interrupt-parent = <&gic>;
5f75e73c	251	interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	252	clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
8c9b1aa4 GL	253	reg-io-width = <4>;
	254	status = "disabled";
	255	};
	256
9694c778 LP	257	pfc: pfc@e6060000 {
	258	compatible = "renesas,pfc-r8a7790";
	259	reg = <0 0xe6060000 0 0x250>;
	260	};
55689bfa	261
b718aa44	262	sdhi0: sd@ee100000 {
df1d0584	263	compatible = "renesas,sdhi-r8a7790";
d721a15c	264	reg = <0 0xee100000 0 0x200>;
8c9b1aa4	265	interrupt-parent = <&gic>;
5f75e73c	266	interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	267	clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
8c9b1aa4 GL	268	cap-sd-highspeed;
	269	status = "disabled";
	270	};
	271
b718aa44	272	sdhi1: sd@ee120000 {
df1d0584	273	compatible = "renesas,sdhi-r8a7790";
d721a15c	274	reg = <0 0xee120000 0 0x200>;
8c9b1aa4	275	interrupt-parent = <&gic>;
5f75e73c	276	interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	277	clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
8c9b1aa4 GL	278	cap-sd-highspeed;
	279	status = "disabled";
	280	};
	281
b718aa44	282	sdhi2: sd@ee140000 {
df1d0584	283	compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 GL	284	reg = <0 0xee140000 0 0x100>;
8c9b1aa4 GL	285	interrupt-parent = <&gic>;
5f75e73c	286	interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	287	clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
8c9b1aa4 GL	288	cap-sd-highspeed;
	289	status = "disabled";
	290	};
	291
b718aa44	292	sdhi3: sd@ee160000 {
df1d0584	293	compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 GL	294	reg = <0 0xee160000 0 0x100>;
8c9b1aa4 GL	295	interrupt-parent = <&gic>;
5f75e73c	296	interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
72197ca7	297	clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
8c9b1aa4 GL	298	cap-sd-highspeed;
	299	status = "disabled";
	300	};
22a1f595 LP	301
	302	clocks {
	303	#address-cells = <2>;
	304	#size-cells = <2>;
	305	ranges;
	306
	307	/* External root clock */
	308	extal_clk: extal_clk {
	309	compatible = "fixed-clock";
	310	#clock-cells = <0>;
	311	/* This value must be overriden by the board. */
	312	clock-frequency = <0>;
	313	clock-output-names = "extal";
	314	};
	315
	316	/* Special CPG clocks */
	317	cpg_clocks: cpg_clocks@e6150000 {
	318	compatible = "renesas,r8a7790-cpg-clocks",
	319	"renesas,rcar-gen2-cpg-clocks";
	320	reg = <0 0xe6150000 0 0x1000>;
	321	clocks = <&extal_clk>;
	322	#clock-cells = <1>;
	323	clock-output-names = "main", "pll0", "pll1", "pll3",
	324	"lb", "qspi", "sdh", "sd0", "sd1",
	325	"z";
	326	};
	327
	328	/* Variable factor clocks */
	329	sd2_clk: sd2_clk@e6150078 {
	330	compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
	331	reg = <0 0xe6150078 0 4>;
	332	clocks = <&pll1_div2_clk>;
	333	#clock-cells = <0>;
	334	clock-output-names = "sd2";
	335	};
	336	sd3_clk: sd3_clk@e615007c {
	337	compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
	338	reg = <0 0xe615007c 0 4>;
	339	clocks = <&pll1_div2_clk>;
	340	#clock-cells = <0>;
	341	clock-output-names = "sd3";
	342	};
	343	mmc0_clk: mmc0_clk@e6150240 {
	344	compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
	345	reg = <0 0xe6150240 0 4>;
	346	clocks = <&pll1_div2_clk>;
	347	#clock-cells = <0>;
	348	clock-output-names = "mmc0";
	349	};
	350	mmc1_clk: mmc1_clk@e6150244 {
	351	compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
	352	reg = <0 0xe6150244 0 4>;
	353	clocks = <&pll1_div2_clk>;
	354	#clock-cells = <0>;
	355	clock-output-names = "mmc1";
	356	};
	357	ssp_clk: ssp_clk@e6150248 {
	358	compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
	359	reg = <0 0xe6150248 0 4>;
	360	clocks = <&pll1_div2_clk>;
	361	#clock-cells = <0>;
	362	clock-output-names = "ssp";
	363	};
	364	ssprs_clk: ssprs_clk@e615024c {
365	compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
366	reg = <0 0xe615024c 0 4>;
367	clocks = <&pll1_div2_clk>;
368	#clock-cells = <0>;
369	clock-output-names = "ssprs";
370	};
371
372	/* Fixed factor clocks */
373	pll1_div2_clk: pll1_div2_clk {
374	compatible = "fixed-factor-clock";
375	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
376	#clock-cells = <0>;
377	clock-div = <2>;
378	clock-mult = <1>;
379	clock-output-names = "pll1_div2";
380	};
381	z2_clk: z2_clk {
382	compatible = "fixed-factor-clock";
383	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
384	#clock-cells = <0>;
385	clock-div = <2>;
386	clock-mult = <1>;
387	clock-output-names = "z2";
388	};
389	zg_clk: zg_clk {
390	compatible = "fixed-factor-clock";
391	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
392	#clock-cells = <0>;
393	clock-div = <3>;
394	clock-mult = <1>;
395	clock-output-names = "zg";
396	};
397	zx_clk: zx_clk {
398	compatible = "fixed-factor-clock";
399	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
400	#clock-cells = <0>;
401	clock-div = <3>;
402	clock-mult = <1>;
403	clock-output-names = "zx";
404	};
405	zs_clk: zs_clk {
406	compatible = "fixed-factor-clock";
407	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
408	#clock-cells = <0>;
409	clock-div = <6>;
410	clock-mult = <1>;
411	clock-output-names = "zs";
412	};
413	hp_clk: hp_clk {
414	compatible = "fixed-factor-clock";
415	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
416	#clock-cells = <0>;
417	clock-div = <12>;
418	clock-mult = <1>;
419	clock-output-names = "hp";
420	};
421	i_clk: i_clk {
422	compatible = "fixed-factor-clock";
423	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
424	#clock-cells = <0>;
425	clock-div = <2>;
426	clock-mult = <1>;
427	clock-output-names = "i";
428	};
429	b_clk: b_clk {
430	compatible = "fixed-factor-clock";
431	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
432	#clock-cells = <0>;
433	clock-div = <12>;
434	clock-mult = <1>;
435	clock-output-names = "b";
436	};
437	p_clk: p_clk {
438	compatible = "fixed-factor-clock";
439	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
440	#clock-cells = <0>;
441	clock-div = <24>;
442	clock-mult = <1>;
443	clock-output-names = "p";
444	};
445	cl_clk: cl_clk {
446	compatible = "fixed-factor-clock";
447	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
448	#clock-cells = <0>;
449	clock-div = <48>;
450	clock-mult = <1>;
451	clock-output-names = "cl";
452	};
453	m2_clk: m2_clk {
454	compatible = "fixed-factor-clock";
455	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
456	#clock-cells = <0>;
457	clock-div = <8>;
458	clock-mult = <1>;
459	clock-output-names = "m2";
460	};
461	imp_clk: imp_clk {
462	compatible = "fixed-factor-clock";
463	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
464	#clock-cells = <0>;
465	clock-div = <4>;
466	clock-mult = <1>;
467	clock-output-names = "imp";
468	};
469	rclk_clk: rclk_clk {
470	compatible = "fixed-factor-clock";
471	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
472	#clock-cells = <0>;
473	clock-div = <(48 * 1024)>;
474	clock-mult = <1>;
475	clock-output-names = "rclk";
476	};
477	oscclk_clk: oscclk_clk {
478	compatible = "fixed-factor-clock";
479	clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
480	#clock-cells = <0>;
481	clock-div = <(12 * 1024)>;
482	clock-mult = <1>;
483	clock-output-names = "oscclk";
484	};
485	zb3_clk: zb3_clk {
486	compatible = "fixed-factor-clock";
487	clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
488	#clock-cells = <0>;
489	clock-div = <4>;
490	clock-mult = <1>;
491	clock-output-names = "zb3";
492	};
493	zb3d2_clk: zb3d2_clk {
494	compatible = "fixed-factor-clock";
495	clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
496	#clock-cells = <0>;
497	clock-div = <8>;
498	clock-mult = <1>;
499	clock-output-names = "zb3d2";
500	};
501	ddr_clk: ddr_clk {
502	compatible = "fixed-factor-clock";
503	clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
504	#clock-cells = <0>;
505	clock-div = <8>;
506	clock-mult = <1>;
507	clock-output-names = "ddr";
508	};
509	mp_clk: mp_clk {
510	compatible = "fixed-factor-clock";
511	clocks = <&pll1_div2_clk>;
512	#clock-cells = <0>;
513	clock-div = <15>;
514	clock-mult = <1>;
515	clock-output-names = "mp";
516	};
517	cp_clk: cp_clk {
518	compatible = "fixed-factor-clock";
519	clocks = <&extal_clk>;
520	#clock-cells = <0>;
521	clock-div = <2>;
522	clock-mult = <1>;
523	clock-output-names = "cp";
524	};
525
526	/* Gate clocks */
9d90951a LP	527	mstp0_clks: mstp0_clks@e6150130 {
	528	compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
	529	reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
	530	clocks = <&mp_clk>;
	531	#clock-cells = <1>;
	532	renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
	533	clock-output-names = "msiof0";
	534	};
22a1f595 LP	535	mstp1_clks: mstp1_clks@e6150134 {
	536	compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
	537	reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
	538	clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
	539	<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
	540	<&zs_clk>;
	541	#clock-cells = <1>;
	542	renesas,clock-indices = <
	543	R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
	544	R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
	545	R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_RT R8A7790_CLK_VSP1_SY
	546	>;
	547	clock-output-names =
	548	"tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
	549	"vsp1-du0", "vsp1-rt", "vsp1-sy";
	550	};
	551	mstp2_clks: mstp2_clks@e6150138 {
	552	compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
	553	reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
	554	clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
9d90951a	555	<&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>;
22a1f595 LP	556	#clock-cells = <1>;
	557	renesas,clock-indices = <
	558	R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
9d90951a LP	559	R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
9d90951a LP	560	R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
22a1f595 LP	561	>;
22a1f595 LP	562	clock-output-names =
9d90951a LP	563	"scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
9d90951a LP	564	"scifb1", "msiof1", "msiof3", "scifb2";
22a1f595 LP	565	};
	566	mstp3_clks: mstp3_clks@e615013c {
	567	compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
	568	reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
	569	clocks = <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, <&sd2_clk>,
	570	<&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>,
	571	<&mmc0_clk>, <&rclk_clk>;
	572	#clock-cells = <1>;
	573	renesas,clock-indices = <
	574	R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
	575	R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0
	576	R8A7790_CLK_MMCIF0 R8A7790_CLK_CMT1
	577	>;
	578	clock-output-names =
	579	"tpu0", "mmcif1", "sdhi3", "sdhi2",
	580	"sdhi1", "sdhi0", "mmcif0", "cmt1";
	581	};
	582	mstp5_clks: mstp5_clks@e6150144 {
	583	compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
	584	reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
	585	clocks = <&extal_clk>, <&p_clk>;
	586	#clock-cells = <1>;
	587	renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
	588	clock-output-names = "thermal", "pwm";
	589	};
	590	mstp7_clks: mstp7_clks@e615014c {
	591	compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
	592	reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
	593	clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
	594	<&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
	595	<&zx_clk>;
	596	#clock-cells = <1>;
	597	renesas,clock-indices = <
	598	R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
	599	R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
	600	R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
	601	R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
	602	>;
	603	clock-output-names =
	604	"ehci", "hsusb", "hscif1", "hscif0", "scif1",
	605	"scif0", "du2", "du1", "du0", "lvds1", "lvds0";
	606	};
	607	mstp8_clks: mstp8_clks@e6150990 {
	608	compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
	609	reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
	610	clocks = <&p_clk>;
	611	#clock-cells = <1>;
	612	renesas,clock-indices = <R8A7790_CLK_ETHER>;
	613	clock-output-names = "ether";
	614	};
	615	mstp9_clks: mstp9_clks@e6150994 {
	616	compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
	617	reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
91b56ca1 LP	618	clocks = <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>,
91b56ca1 LP	619	<&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>;
22a1f595 LP	620	#clock-cells = <1>;
22a1f595 LP	621	renesas,clock-indices = <
91b56ca1 LP	622	R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD
	623	R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1
	624	R8A7790_CLK_I2C0
22a1f595	625	>;
91b56ca1 LP	626	clock-output-names =
91b56ca1 LP	627	"rcan1", "rcan0", "qspi_mod", "i2c3", "i2c2", "i2c1", "i2c0";
22a1f595 LP	628	};
22a1f595 LP	629	};
0468b2d6	630	};