Commit | Line | Data |
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0468b2d6 MD |
1 | /* |
2 | * Device Tree Source for the r8a7790 SoC | |
3 | * | |
4 | * Copyright (C) 2013 Renesas Solutions Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /include/ "skeleton.dtsi" | |
12 | ||
13 | / { | |
14 | compatible = "renesas,r8a7790"; | |
15 | interrupt-parent = <&gic>; | |
16 | ||
17 | cpus { | |
18 | #address-cells = <1>; | |
19 | #size-cells = <0>; | |
20 | ||
21 | cpu0: cpu@0 { | |
22 | device_type = "cpu"; | |
23 | compatible = "arm,cortex-a15"; | |
24 | reg = <0>; | |
25 | clock-frequency = <1300000000>; | |
26 | }; | |
27 | }; | |
28 | ||
29 | gic: interrupt-controller@f1001000 { | |
30 | compatible = "arm,cortex-a15-gic"; | |
31 | #interrupt-cells = <3>; | |
32 | #address-cells = <0>; | |
33 | interrupt-controller; | |
34 | reg = <0xf1001000 0x1000>, | |
35 | <0xf1002000 0x1000>, | |
36 | <0xf1004000 0x2000>, | |
37 | <0xf1006000 0x2000>; | |
38 | interrupts = <1 9 0xf04>; | |
39 | ||
40 | gic-cpuif@4 { | |
41 | compatible = "arm,gic-cpuif"; | |
42 | cpuif-id = <4>; | |
43 | cpu = <&cpu0>; | |
44 | }; | |
45 | }; | |
46 | ||
47 | timer { | |
48 | compatible = "arm,armv7-timer"; | |
49 | interrupts = <1 13 0xf08>, | |
50 | <1 14 0xf08>, | |
51 | <1 11 0xf08>, | |
52 | <1 10 0xf08>; | |
53 | }; | |
8f5ec0a5 MD |
54 | |
55 | irqc0: interrupt-controller@e61c0000 { | |
56 | compatible = "renesas,irqc"; | |
57 | #interrupt-cells = <2>; | |
58 | interrupt-controller; | |
59 | reg = <0xe61c0000 0x200>; | |
60 | interrupt-parent = <&gic>; | |
61 | interrupts = <0 0 4>, <0 1 4>, <0 2 4>, <0 3 4>; | |
62 | }; | |
0468b2d6 | 63 | }; |