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ARM: dts: kzm9g: Configure NMI key as wake-up source
[deliverable/linux.git] / arch / arm / boot / dts / r8a7790.dtsi
CommitLineData
0468b2d6
MD		 1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
b621f6d4 4 * Copyright (C) 2015 Renesas Electronics Corporation
d8913c67
SS		 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
0468b2d6
MD		 7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
22a1f595 13#include <dt-bindings/clock/r8a7790-clock.h>
5f75e73c
LP		 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
0468b2d6
MD		 17/ {
18 compatible = "renesas,r8a7790";
19 interrupt-parent = <&gic>;
8585deb1
TY		 20 #address-cells = <2>;
21 #size-cells = <2>;
0468b2d6 22
6b1d7c68
WS		 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
05f39916
WS		 28 i2c4 = &iic0;
29 i2c5 = &iic1;
30 i2c6 = &iic2;
31 i2c7 = &iic3;
fad6d45c 32 spi0 = &qspi;
ae8a6146
GU		 33 spi1 = &msiof0;
34 spi2 = &msiof1;
35 spi3 = &msiof2;
36 spi4 = &msiof3;
9f685bfc
BD		 37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
40 vin3 = &vin3;
6b1d7c68
WS		 41 };
42
0468b2d6
MD		 43 cpus {
44 #address-cells = <1>;
45 #size-cells = <0>;
46
47 cpu0: cpu@0 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a15";
50 reg = <0>;
51 clock-frequency = <1300000000>;
b989e138
BC		 52 voltage-tolerance = <1>; /* 1% */
53 clocks = <&cpg_clocks R8A7790_CLK_Z>;
54 clock-latency = <300000>; /* 300 us */
fb1cecd4 55 next-level-cache = <&L2_CA15>;
b989e138
BC		 56
57 /* kHz - uV - OPPs unknown yet */
58 operating-points = <1400000 1000000>,
59 <1225000 1000000>,
60 <1050000 1000000>,
61 < 875000 1000000>,
62 < 700000 1000000>,
63 < 350000 1000000>;
0468b2d6 64 };
c1f95979
MD		 65
66 cpu1: cpu@1 {
67 device_type = "cpu";
68 compatible = "arm,cortex-a15";
69 reg = <1>;
70 clock-frequency = <1300000000>;
fb1cecd4 71 next-level-cache = <&L2_CA15>;
c1f95979
MD		 72 };
73
74 cpu2: cpu@2 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a15";
77 reg = <2>;
78 clock-frequency = <1300000000>;
fb1cecd4 79 next-level-cache = <&L2_CA15>;
c1f95979
MD		 80 };
81
82 cpu3: cpu@3 {
83 device_type = "cpu";
84 compatible = "arm,cortex-a15";
85 reg = <3>;
86 clock-frequency = <1300000000>;
fb1cecd4 87 next-level-cache = <&L2_CA15>;
c1f95979 88 };
2007e74c
MD		 89
90 cpu4: cpu@4 {
91 device_type = "cpu";
92 compatible = "arm,cortex-a7";
93 reg = <0x100>;
94 clock-frequency = <780000000>;
fb1cecd4 95 next-level-cache = <&L2_CA7>;
2007e74c
MD		 96 };
97
98 cpu5: cpu@5 {
99 device_type = "cpu";
100 compatible = "arm,cortex-a7";
101 reg = <0x101>;
102 clock-frequency = <780000000>;
fb1cecd4 103 next-level-cache = <&L2_CA7>;
2007e74c
MD		 104 };
105
106 cpu6: cpu@6 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x102>;
110 clock-frequency = <780000000>;
fb1cecd4 111 next-level-cache = <&L2_CA7>;
2007e74c
MD		 112 };
113
114 cpu7: cpu@7 {
115 device_type = "cpu";
116 compatible = "arm,cortex-a7";
117 reg = <0x103>;
118 clock-frequency = <780000000>;
fb1cecd4 119 next-level-cache = <&L2_CA7>;
2007e74c 120 };
0468b2d6
MD		 121 };
122
a8b805f3
KM		 123 thermal-zones {
124 cpu_thermal: cpu-thermal {
125 polling-delay-passive = <0>;
126 polling-delay = <0>;
127
128 thermal-sensors = <&thermal>;
129
130 trips {
131 cpu-crit {
132 temperature = <115000>;
133 hysteresis = <0>;
134 type = "critical";
135 };
136 };
137 cooling-maps {
138 };
139 };
140 };
141
fb1cecd4
GU		 142 L2_CA15: cache-controller@0 {
143 compatible = "cache";
144 cache-unified;
145 cache-level = <2>;
146 };
147
148 L2_CA7: cache-controller@1 {
149 compatible = "cache";
150 cache-unified;
151 cache-level = <2>;
152 };
153
0468b2d6 154 gic: interrupt-controller@f1001000 {
e715e9c5 155 compatible = "arm,gic-400";
0468b2d6
MD		 156 #interrupt-cells = <3>;
157 #address-cells = <0>;
158 interrupt-controller;
8585deb1
TY		 159 reg = <0 0xf1001000 0 0x1000>,
160 <0 0xf1002000 0 0x1000>,
161 <0 0xf1004000 0 0x2000>,
162 <0 0xf1006000 0 0x2000>;
3abb4d5f 163 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0468b2d6
MD		 164 };
165
23de2278 166 gpio0: gpio@e6050000 {
f98e10c8 167 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 168 reg = <0 0xe6050000 0 0x50>;
3abb4d5f 169 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 170 #gpio-cells = <2>;
171 gpio-controller;
172 gpio-ranges = <&pfc 0 0 32>;
173 #interrupt-cells = <2>;
174 interrupt-controller;
81f6883f 175 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
484adb00 176 power-domains = <&cpg_clocks>;
f98e10c8
LP		 177 };
178
23de2278 179 gpio1: gpio@e6051000 {
f98e10c8 180 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 181 reg = <0 0xe6051000 0 0x50>;
3abb4d5f 182 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 183 #gpio-cells = <2>;
184 gpio-controller;
56a2182f 185 gpio-ranges = <&pfc 0 32 30>;
f98e10c8
LP		 186 #interrupt-cells = <2>;
187 interrupt-controller;
81f6883f 188 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
484adb00 189 power-domains = <&cpg_clocks>;
f98e10c8
LP		 190 };
191
23de2278 192 gpio2: gpio@e6052000 {
f98e10c8 193 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 194 reg = <0 0xe6052000 0 0x50>;
3abb4d5f 195 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 196 #gpio-cells = <2>;
197 gpio-controller;
56a2182f 198 gpio-ranges = <&pfc 0 64 30>;
f98e10c8
LP		 199 #interrupt-cells = <2>;
200 interrupt-controller;
81f6883f 201 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
484adb00 202 power-domains = <&cpg_clocks>;
f98e10c8
LP		 203 };
204
23de2278 205 gpio3: gpio@e6053000 {
f98e10c8 206 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 207 reg = <0 0xe6053000 0 0x50>;
3abb4d5f 208 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 209 #gpio-cells = <2>;
210 gpio-controller;
211 gpio-ranges = <&pfc 0 96 32>;
212 #interrupt-cells = <2>;
213 interrupt-controller;
81f6883f 214 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
484adb00 215 power-domains = <&cpg_clocks>;
f98e10c8
LP		 216 };
217
23de2278 218 gpio4: gpio@e6054000 {
f98e10c8 219 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 220 reg = <0 0xe6054000 0 0x50>;
3abb4d5f 221 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 222 #gpio-cells = <2>;
223 gpio-controller;
224 gpio-ranges = <&pfc 0 128 32>;
225 #interrupt-cells = <2>;
226 interrupt-controller;
81f6883f 227 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
484adb00 228 power-domains = <&cpg_clocks>;
f98e10c8
LP		 229 };
230
23de2278 231 gpio5: gpio@e6055000 {
f98e10c8 232 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 233 reg = <0 0xe6055000 0 0x50>;
3abb4d5f 234 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 235 #gpio-cells = <2>;
236 gpio-controller;
237 gpio-ranges = <&pfc 0 160 32>;
238 #interrupt-cells = <2>;
239 interrupt-controller;
81f6883f 240 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
484adb00 241 power-domains = <&cpg_clocks>;
f98e10c8
LP		 242 };
243
a8b805f3
KM		 244 thermal: thermal@e61f0000 {
245 compatible = "renesas,thermal-r8a7790",
246 "renesas,rcar-gen2-thermal",
247 "renesas,rcar-thermal";
03e2f56b 248 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
3abb4d5f 249 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
d3a439db 250 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
484adb00 251 power-domains = <&cpg_clocks>;
a8b805f3 252 #thermal-sensor-cells = <0>;
03e2f56b
MD		 253 };
254
0468b2d6
MD		 255 timer {
256 compatible = "arm,armv7-timer";
3abb4d5f
SH		 257 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
258 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
259 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
260 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0468b2d6 261 };
8f5ec0a5 262
39cf6d73 263 cmt0: timer@ffca0000 {
37757030 264 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73 265 reg = <0 0xffca0000 0 0x1004>;
3abb4d5f
SH		 266 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
267 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
39cf6d73
LP		 268 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
269 clock-names = "fck";
484adb00 270 power-domains = <&cpg_clocks>;
39cf6d73
LP		 271
272 renesas,channels-mask = <0x60>;
273
274 status = "disabled";
275 };
276
277 cmt1: timer@e6130000 {
37757030 278 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73 279 reg = <0 0xe6130000 0 0x1004>;
3abb4d5f
SH		 280 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
39cf6d73
LP		 288 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
289 clock-names = "fck";
484adb00 290 power-domains = <&cpg_clocks>;
39cf6d73
LP		 291
292 renesas,channels-mask = <0xff>;
293
294 status = "disabled";
295 };
296
8f5ec0a5 297 irqc0: interrupt-controller@e61c0000 {
220fc352 298 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
8f5ec0a5
MD		 299 #interrupt-cells = <2>;
300 interrupt-controller;
8585deb1 301 reg = <0 0xe61c0000 0 0x200>;
3abb4d5f
SH		 302 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
61624caf 306 clocks = <&mstp4_clks R8A7790_CLK_IRQC>;
484adb00 307 power-domains = <&cpg_clocks>;
8f5ec0a5 308 };
8c9b1aa4 309
b9fea49c 310 dmac0: dma-controller@e6700000 {
4af0a664 311 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
b9fea49c 312 reg = <0 0xe6700000 0 0x20000>;
3abb4d5f
SH		 313 interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
314 GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
315 GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
316 GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
317 GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
318 GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
319 GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
320 GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
321 GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
322 GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
325 GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
326 GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
327 GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
328 GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
b9fea49c
LP		 329 interrupt-names = "error",
330 "ch0", "ch1", "ch2", "ch3",
331 "ch4", "ch5", "ch6", "ch7",
332 "ch8", "ch9", "ch10", "ch11",
333 "ch12", "ch13", "ch14";
334 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
335 clock-names = "fck";
484adb00 336 power-domains = <&cpg_clocks>;
b9fea49c
LP		 337 #dma-cells = <1>;
338 dma-channels = <15>;
339 };
340
341 dmac1: dma-controller@e6720000 {
4af0a664 342 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
b9fea49c 343 reg = <0 0xe6720000 0 0x20000>;
3abb4d5f
SH		 344 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
345 GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
346 GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
347 GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
349 GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
350 GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
351 GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
352 GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
353 GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
354 GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
355 GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
356 GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
357 GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
358 GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
359 GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
b9fea49c
LP		 360 interrupt-names = "error",
361 "ch0", "ch1", "ch2", "ch3",
362 "ch4", "ch5", "ch6", "ch7",
363 "ch8", "ch9", "ch10", "ch11",
364 "ch12", "ch13", "ch14";
365 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
366 clock-names = "fck";
484adb00 367 power-domains = <&cpg_clocks>;
b9fea49c
LP		 368 #dma-cells = <1>;
369 dma-channels = <15>;
370 };
ba3240be
KM		 371
372 audma0: dma-controller@ec700000 {
4af0a664 373 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
ba3240be 374 reg = <0 0xec700000 0 0x10000>;
3abb4d5f
SH		 375 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
376 GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
377 GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
378 GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
379 GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
380 GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
381 GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
382 GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
383 GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
384 GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
385 GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
386 GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
387 GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
388 GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
ba3240be
KM		 389 interrupt-names = "error",
390 "ch0", "ch1", "ch2", "ch3",
391 "ch4", "ch5", "ch6", "ch7",
392 "ch8", "ch9", "ch10", "ch11",
393 "ch12";
394 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>;
395 clock-names = "fck";
484adb00 396 power-domains = <&cpg_clocks>;
ba3240be
KM		 397 #dma-cells = <1>;
398 dma-channels = <13>;
399 };
400
401 audma1: dma-controller@ec720000 {
4af0a664 402 compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
ba3240be 403 reg = <0 0xec720000 0 0x10000>;
3abb4d5f
SH		 404 interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH
405 GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH
406 GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH
407 GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH
408 GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH
409 GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH
410 GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH
411 GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH
412 GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH
413 GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH
414 GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH
415 GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH
416 GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH
417 GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
ba3240be
KM		 418 interrupt-names = "error",
419 "ch0", "ch1", "ch2", "ch3",
420 "ch4", "ch5", "ch6", "ch7",
421 "ch8", "ch9", "ch10", "ch11",
422 "ch12";
423 clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>;
424 clock-names = "fck";
484adb00 425 power-domains = <&cpg_clocks>;
ba3240be
KM		 426 #dma-cells = <1>;
427 dma-channels = <13>;
428 };
429
a3ff2090 430 usb_dmac0: dma-controller@e65a0000 {
d01c8bec 431 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
a3ff2090 432 reg = <0 0xe65a0000 0 0x100>;
3abb4d5f
SH		 433 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH
434 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
a3ff2090
YS		 435 interrupt-names = "ch0", "ch1";
436 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC0>;
484adb00 437 power-domains = <&cpg_clocks>;
a3ff2090
YS		 438 #dma-cells = <1>;
439 dma-channels = <2>;
440 };
441
442 usb_dmac1: dma-controller@e65b0000 {
d01c8bec 443 compatible = "renesas,r8a7790-usb-dmac", "renesas,usb-dmac";
a3ff2090 444 reg = <0 0xe65b0000 0 0x100>;
3abb4d5f
SH		 445 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH
446 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
a3ff2090
YS		 447 interrupt-names = "ch0", "ch1";
448 clocks = <&mstp3_clks R8A7790_CLK_USBDMAC1>;
484adb00 449 power-domains = <&cpg_clocks>;
a3ff2090
YS		 450 #dma-cells = <1>;
451 dma-channels = <2>;
452 };
453
edd2b9f4
GL		 454 i2c0: i2c@e6508000 {
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "renesas,i2c-r8a7790";
458 reg = <0 0xe6508000 0 0x40>;
3abb4d5f 459 interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
2450badf 460 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
484adb00 461 power-domains = <&cpg_clocks>;
ac8e7f31 462 i2c-scl-internal-delay-ns = <110>;
edd2b9f4
GL		 463 status = "disabled";
464 };
465
466 i2c1: i2c@e6518000 {
467 #address-cells = <1>;
468 #size-cells = <0>;
469 compatible = "renesas,i2c-r8a7790";
470 reg = <0 0xe6518000 0 0x40>;
3abb4d5f 471 interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
2450badf 472 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
484adb00 473 power-domains = <&cpg_clocks>;
ac8e7f31 474 i2c-scl-internal-delay-ns = <6>;
edd2b9f4
GL		 475 status = "disabled";
476 };
477
478 i2c2: i2c@e6530000 {
479 #address-cells = <1>;
480 #size-cells = <0>;
481 compatible = "renesas,i2c-r8a7790";
482 reg = <0 0xe6530000 0 0x40>;
3abb4d5f 483 interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
2450badf 484 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
484adb00 485 power-domains = <&cpg_clocks>;
ac8e7f31 486 i2c-scl-internal-delay-ns = <6>;
edd2b9f4
GL		 487 status = "disabled";
488 };
489
490 i2c3: i2c@e6540000 {
491 #address-cells = <1>;
492 #size-cells = <0>;
493 compatible = "renesas,i2c-r8a7790";
494 reg = <0 0xe6540000 0 0x40>;
3abb4d5f 495 interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
2450badf 496 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
484adb00 497 power-domains = <&cpg_clocks>;
ac8e7f31 498 i2c-scl-internal-delay-ns = <110>;
edd2b9f4
GL		 499 status = "disabled";
500 };
501
05f39916
WS		 502 iic0: i2c@e6500000 {
503 #address-cells = <1>;
504 #size-cells = <0>;
505 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
506 reg = <0 0xe6500000 0 0x425>;
3abb4d5f 507 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
05f39916 508 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
0d73ca41
WS		 509 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
510 dma-names = "tx", "rx";
484adb00 511 power-domains = <&cpg_clocks>;
05f39916
WS		 512 status = "disabled";
513 };
514
515 iic1: i2c@e6510000 {
516 #address-cells = <1>;
517 #size-cells = <0>;
518 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
519 reg = <0 0xe6510000 0 0x425>;
3abb4d5f 520 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
05f39916 521 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
0d73ca41
WS		 522 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
523 dma-names = "tx", "rx";
484adb00 524 power-domains = <&cpg_clocks>;
05f39916
WS		 525 status = "disabled";
526 };
527
528 iic2: i2c@e6520000 {
529 #address-cells = <1>;
530 #size-cells = <0>;
531 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
532 reg = <0 0xe6520000 0 0x425>;
3abb4d5f 533 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
05f39916 534 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
0d73ca41
WS		 535 dmas = <&dmac0 0x69>, <&dmac0 0x6a>;
536 dma-names = "tx", "rx";
484adb00 537 power-domains = <&cpg_clocks>;
05f39916
WS		 538 status = "disabled";
539 };
540
541 iic3: i2c@e60b0000 {
542 #address-cells = <1>;
543 #size-cells = <0>;
544 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
545 reg = <0 0xe60b0000 0 0x425>;
3abb4d5f 546 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
05f39916 547 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
0d73ca41
WS		 548 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
549 dma-names = "tx", "rx";
484adb00 550 power-domains = <&cpg_clocks>;
05f39916
WS		 551 status = "disabled";
552 };
553
22c2b78d 554 mmcif0: mmc@ee200000 {
063e8560 555 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 556 reg = <0 0xee200000 0 0x80>;
3abb4d5f 557 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 558 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
108216c1
LP		 559 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
560 dma-names = "tx", "rx";
484adb00 561 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 562 reg-io-width = <4>;
563 status = "disabled";
96370057 564 max-frequency = <97500000>;
8c9b1aa4
GL		 565 };
566
b718aa44 567 mmcif1: mmc@ee220000 {
063e8560 568 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 569 reg = <0 0xee220000 0 0x80>;
3abb4d5f 570 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 571 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
108216c1
LP		 572 dmas = <&dmac0 0xe1>, <&dmac0 0xe2>;
573 dma-names = "tx", "rx";
484adb00 574 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 575 reg-io-width = <4>;
576 status = "disabled";
96370057 577 max-frequency = <97500000>;
8c9b1aa4
GL		 578 };
579
9694c778
LP		 580 pfc: pfc@e6060000 {
581 compatible = "renesas,pfc-r8a7790";
582 reg = <0 0xe6060000 0 0x250>;
583 };
55689bfa 584
b718aa44 585 sdhi0: sd@ee100000 {
df1d0584 586 compatible = "renesas,sdhi-r8a7790";
66f47ed0 587 reg = <0 0xee100000 0 0x328>;
3abb4d5f 588 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 589 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
941fe36b
LP		 590 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
591 dma-names = "tx", "rx";
22f708b0 592 max-frequency = <156000000>;
484adb00 593 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 594 status = "disabled";
595 };
596
b718aa44 597 sdhi1: sd@ee120000 {
df1d0584 598 compatible = "renesas,sdhi-r8a7790";
66f47ed0 599 reg = <0 0xee120000 0 0x328>;
3abb4d5f 600 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 601 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
941fe36b
LP		 602 dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
603 dma-names = "tx", "rx";
22f708b0 604 max-frequency = <156000000>;
484adb00 605 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 606 status = "disabled";
607 };
608
b718aa44 609 sdhi2: sd@ee140000 {
df1d0584 610 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 611 reg = <0 0xee140000 0 0x100>;
3abb4d5f 612 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 613 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
941fe36b
LP		 614 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
615 dma-names = "tx", "rx";
22f708b0 616 max-frequency = <97500000>;
484adb00 617 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 618 status = "disabled";
619 };
620
b718aa44 621 sdhi3: sd@ee160000 {
df1d0584 622 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 623 reg = <0 0xee160000 0 0x100>;
3abb4d5f 624 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 625 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
941fe36b
LP		 626 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
627 dma-names = "tx", "rx";
22f708b0 628 max-frequency = <97500000>;
484adb00 629 power-domains = <&cpg_clocks>;
8c9b1aa4
GL		 630 status = "disabled";
631 };
22a1f595 632
597af20f 633 scifa0: serial@e6c40000 {
a20dc9f2
GU		 634 compatible = "renesas,scifa-r8a7790",
635 "renesas,rcar-gen2-scifa", "renesas,scifa";
597af20f 636 reg = <0 0xe6c40000 0 64>;
3abb4d5f 637 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
597af20f 638 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
6c6e12a1 639 clock-names = "fck";
acea43fc
GU		 640 dmas = <&dmac0 0x21>, <&dmac0 0x22>;
641 dma-names = "tx", "rx";
484adb00 642 power-domains = <&cpg_clocks>;
597af20f
LP		 643 status = "disabled";
644 };
645
646 scifa1: serial@e6c50000 {
a20dc9f2
GU		 647 compatible = "renesas,scifa-r8a7790",
648 "renesas,rcar-gen2-scifa", "renesas,scifa";
597af20f 649 reg = <0 0xe6c50000 0 64>;
3abb4d5f 650 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
597af20f 651 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
6c6e12a1 652 clock-names = "fck";
acea43fc
GU		 653 dmas = <&dmac0 0x25>, <&dmac0 0x26>;
654 dma-names = "tx", "rx";
484adb00 655 power-domains = <&cpg_clocks>;
597af20f
LP		 656 status = "disabled";
657 };
658
659 scifa2: serial@e6c60000 {
a20dc9f2
GU		 660 compatible = "renesas,scifa-r8a7790",
661 "renesas,rcar-gen2-scifa", "renesas,scifa";
597af20f 662 reg = <0 0xe6c60000 0 64>;
3abb4d5f 663 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
597af20f 664 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
6c6e12a1 665 clock-names = "fck";
acea43fc
GU		 666 dmas = <&dmac0 0x27>, <&dmac0 0x28>;
667 dma-names = "tx", "rx";
484adb00 668 power-domains = <&cpg_clocks>;
597af20f
LP		 669 status = "disabled";
670 };
671
672 scifb0: serial@e6c20000 {
a20dc9f2
GU		 673 compatible = "renesas,scifb-r8a7790",
674 "renesas,rcar-gen2-scifb", "renesas,scifb";
597af20f 675 reg = <0 0xe6c20000 0 64>;
3abb4d5f 676 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
597af20f 677 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
6c6e12a1 678 clock-names = "fck";
acea43fc
GU		 679 dmas = <&dmac0 0x3d>, <&dmac0 0x3e>;
680 dma-names = "tx", "rx";
484adb00 681 power-domains = <&cpg_clocks>;
597af20f
LP		 682 status = "disabled";
683 };
684
685 scifb1: serial@e6c30000 {
a20dc9f2
GU		 686 compatible = "renesas,scifb-r8a7790",
687 "renesas,rcar-gen2-scifb", "renesas,scifb";
597af20f 688 reg = <0 0xe6c30000 0 64>;
3abb4d5f 689 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
597af20f 690 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
6c6e12a1 691 clock-names = "fck";
acea43fc
GU		 692 dmas = <&dmac0 0x19>, <&dmac0 0x1a>;
693 dma-names = "tx", "rx";
484adb00 694 power-domains = <&cpg_clocks>;
597af20f
LP		 695 status = "disabled";
696 };
697
698 scifb2: serial@e6ce0000 {
a20dc9f2
GU		 699 compatible = "renesas,scifb-r8a7790",
700 "renesas,rcar-gen2-scifb", "renesas,scifb";
597af20f 701 reg = <0 0xe6ce0000 0 64>;
3abb4d5f 702 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
597af20f 703 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
6c6e12a1 704 clock-names = "fck";
acea43fc
GU		 705 dmas = <&dmac0 0x1d>, <&dmac0 0x1e>;
706 dma-names = "tx", "rx";
484adb00 707 power-domains = <&cpg_clocks>;
597af20f
LP		 708 status = "disabled";
709 };
710
711 scif0: serial@e6e60000 {
a20dc9f2
GU		 712 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
713 "renesas,scif";
597af20f 714 reg = <0 0xe6e60000 0 64>;
3abb4d5f 715 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
42af65e8
GU		 716 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>, <&zs_clk>,
717 <&scif_clk>;
718 clock-names = "fck", "brg_int", "scif_clk";
acea43fc
GU		 719 dmas = <&dmac0 0x29>, <&dmac0 0x2a>;
720 dma-names = "tx", "rx";
484adb00 721 power-domains = <&cpg_clocks>;
597af20f
LP		 722 status = "disabled";
723 };
724
725 scif1: serial@e6e68000 {
a20dc9f2
GU		 726 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
727 "renesas,scif";
597af20f 728 reg = <0 0xe6e68000 0 64>;
3abb4d5f 729 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
42af65e8
GU		 730 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>, <&zs_clk>,
731 <&scif_clk>;
732 clock-names = "fck", "brg_int", "scif_clk";
acea43fc
GU		 733 dmas = <&dmac0 0x2d>, <&dmac0 0x2e>;
734 dma-names = "tx", "rx";
484adb00 735 power-domains = <&cpg_clocks>;
597af20f
LP		 736 status = "disabled";
737 };
738
022869a2
GU		 739 scif2: serial@e6e56000 {
740 compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
741 "renesas,scif";
742 reg = <0 0xe6e56000 0 64>;
743 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
744 clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
745 <&scif_clk>;
746 clock-names = "fck", "brg_int", "scif_clk";
747 dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
748 dma-names = "tx", "rx";
749 power-domains = <&cpg_clocks>;
750 status = "disabled";
751 };
752
597af20f 753 hscif0: serial@e62c0000 {
a20dc9f2
GU		 754 compatible = "renesas,hscif-r8a7790",
755 "renesas,rcar-gen2-hscif", "renesas,hscif";
597af20f 756 reg = <0 0xe62c0000 0 96>;
3abb4d5f 757 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
42af65e8
GU		 758 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>, <&zs_clk>,
759 <&scif_clk>;
760 clock-names = "fck", "brg_int", "scif_clk";
acea43fc
GU		 761 dmas = <&dmac0 0x39>, <&dmac0 0x3a>;
762 dma-names = "tx", "rx";
484adb00 763 power-domains = <&cpg_clocks>;
597af20f
LP		 764 status = "disabled";
765 };
766
767 hscif1: serial@e62c8000 {
a20dc9f2
GU		 768 compatible = "renesas,hscif-r8a7790",
769 "renesas,rcar-gen2-hscif", "renesas,hscif";
597af20f 770 reg = <0 0xe62c8000 0 96>;
3abb4d5f 771 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
42af65e8
GU		 772 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>, <&zs_clk>,
773 <&scif_clk>;
774 clock-names = "fck", "brg_int", "scif_clk";
acea43fc
GU		 775 dmas = <&dmac0 0x4d>, <&dmac0 0x4e>;
776 dma-names = "tx", "rx";
484adb00 777 power-domains = <&cpg_clocks>;
597af20f
LP		 778 status = "disabled";
779 };
780
d8913c67
SS		 781 ether: ethernet@ee700000 {
782 compatible = "renesas,ether-r8a7790";
783 reg = <0 0xee700000 0 0x400>;
3abb4d5f 784 interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
d8913c67 785 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
484adb00 786 power-domains = <&cpg_clocks>;
d8913c67
SS		 787 phy-mode = "rmii";
788 #address-cells = <1>;
789 #size-cells = <0>;
790 status = "disabled";
791 };
792
f25d6b97 793 avb: ethernet@e6800000 {
d92df7e5
SH		 794 compatible = "renesas,etheravb-r8a7790",
795 "renesas,etheravb-rcar-gen2";
f25d6b97 796 reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>;
3abb4d5f 797 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
f25d6b97 798 clocks = <&mstp8_clks R8A7790_CLK_ETHERAVB>;
484adb00 799 power-domains = <&cpg_clocks>;
f25d6b97
SS		 800 #address-cells = <1>;
801 #size-cells = <0>;
802 status = "disabled";
803 };
804
cde630f7
VB		 805 sata0: sata@ee300000 {
806 compatible = "renesas,sata-r8a7790";
807 reg = <0 0xee300000 0 0x2000>;
3abb4d5f 808 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
cde630f7 809 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
484adb00 810 power-domains = <&cpg_clocks>;
cde630f7
VB		 811 status = "disabled";
812 };
813
814 sata1: sata@ee500000 {
815 compatible = "renesas,sata-r8a7790";
816 reg = <0 0xee500000 0 0x2000>;
3abb4d5f 817 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
cde630f7 818 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
484adb00 819 power-domains = <&cpg_clocks>;
cde630f7
VB		 820 status = "disabled";
821 };
822
ae0a555b 823 hsusb: usb@e6590000 {
d87ec94a 824 compatible = "renesas,usbhs-r8a7790", "renesas,rcar-gen2-usbhs";
ae0a555b 825 reg = <0 0xe6590000 0 0x100>;
3abb4d5f 826 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
ae0a555b 827 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
e8295dc3
YS		 828 dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
829 <&usb_dmac1 0>, <&usb_dmac1 1>;
830 dma-names = "ch0", "ch1", "ch2", "ch3";
484adb00
GU		 831 power-domains = <&cpg_clocks>;
832 renesas,buswait = <4>;
833 phys = <&usb0 1>;
834 phy-names = "usb";
ae0a555b
YS		 835 status = "disabled";
836 };
837
e089f657
SS		 838 usbphy: usb-phy@e6590100 {
839 compatible = "renesas,usb-phy-r8a7790";
840 reg = <0 0xe6590100 0 0x100>;
841 #address-cells = <1>;
842 #size-cells = <0>;
843 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
844 clock-names = "usbhs";
484adb00 845 power-domains = <&cpg_clocks>;
e089f657
SS		 846 status = "disabled";
847
848 usb0: usb-channel@0 {
849 reg = <0>;
850 #phy-cells = <1>;
851 };
852 usb2: usb-channel@2 {
853 reg = <2>;
854 #phy-cells = <1>;
855 };
856 };
857
9f685bfc
BD		 858 vin0: video@e6ef0000 {
859 compatible = "renesas,vin-r8a7790";
9f685bfc 860 reg = <0 0xe6ef0000 0 0x1000>;
3abb4d5f 861 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 862 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
863 power-domains = <&cpg_clocks>;
9f685bfc
BD		 864 status = "disabled";
865 };
866
867 vin1: video@e6ef1000 {
868 compatible = "renesas,vin-r8a7790";
9f685bfc 869 reg = <0 0xe6ef1000 0 0x1000>;
3abb4d5f 870 interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 871 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
872 power-domains = <&cpg_clocks>;
9f685bfc
BD		 873 status = "disabled";
874 };
875
876 vin2: video@e6ef2000 {
877 compatible = "renesas,vin-r8a7790";
9f685bfc 878 reg = <0 0xe6ef2000 0 0x1000>;
3abb4d5f 879 interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 880 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
881 power-domains = <&cpg_clocks>;
9f685bfc
BD		 882 status = "disabled";
883 };
884
885 vin3: video@e6ef3000 {
886 compatible = "renesas,vin-r8a7790";
9f685bfc 887 reg = <0 0xe6ef3000 0 0x1000>;
3abb4d5f 888 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 889 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
890 power-domains = <&cpg_clocks>;
9f685bfc
BD		 891 status = "disabled";
892 };
893
3ac6a83c
LP		 894 vsp1@fe920000 {
895 compatible = "renesas,vsp1";
896 reg = <0 0xfe920000 0 0x8000>;
3abb4d5f 897 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c 898 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
484adb00 899 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 900
901 renesas,has-sru;
902 renesas,#rpf = <5>;
903 renesas,#uds = <1>;
904 renesas,#wpf = <4>;
905 };
906
907 vsp1@fe928000 {
908 compatible = "renesas,vsp1";
909 reg = <0 0xfe928000 0 0x8000>;
3abb4d5f 910 interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c 911 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
484adb00 912 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 913
914 renesas,has-lut;
915 renesas,has-sru;
916 renesas,#rpf = <5>;
917 renesas,#uds = <3>;
918 renesas,#wpf = <4>;
919 };
920
921 vsp1@fe930000 {
922 compatible = "renesas,vsp1";
923 reg = <0 0xfe930000 0 0x8000>;
3abb4d5f 924 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c 925 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
484adb00 926 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 927
928 renesas,has-lif;
929 renesas,has-lut;
930 renesas,#rpf = <4>;
931 renesas,#uds = <1>;
932 renesas,#wpf = <4>;
933 };
934
935 vsp1@fe938000 {
936 compatible = "renesas,vsp1";
937 reg = <0 0xfe938000 0 0x8000>;
3abb4d5f 938 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c 939 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
484adb00 940 power-domains = <&cpg_clocks>;
3ac6a83c
LP		 941
942 renesas,has-lif;
943 renesas,has-lut;
944 renesas,#rpf = <4>;
945 renesas,#uds = <1>;
946 renesas,#wpf = <4>;
947 };
948
949 du: display@feb00000 {
950 compatible = "renesas,du-r8a7790";
951 reg = <0 0xfeb00000 0 0x70000>,
952 <0 0xfeb90000 0 0x1c>,
953 <0 0xfeb94000 0 0x1c>;
954 reg-names = "du", "lvds.0", "lvds.1";
3abb4d5f
SH		 955 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
956 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
3ac6a83c
LP		 958 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
959 <&mstp7_clks R8A7790_CLK_DU1>,
960 <&mstp7_clks R8A7790_CLK_DU2>,
961 <&mstp7_clks R8A7790_CLK_LVDS0>,
962 <&mstp7_clks R8A7790_CLK_LVDS1>;
963 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
964 status = "disabled";
965
966 ports {
967 #address-cells = <1>;
968 #size-cells = <0>;
969
970 port@0 {
971 reg = <0>;
972 du_out_rgb: endpoint {
973 };
974 };
975 port@1 {
976 reg = <1>;
977 du_out_lvds0: endpoint {
978 };
979 };
980 port@2 {
981 reg = <2>;
982 du_out_lvds1: endpoint {
983 };
984 };
985 };
986 };
987
6a7742b4 988 can0: can@e6e80000 {
28e941de 989 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
6a7742b4 990 reg = <0 0xe6e80000 0 0x1000>;
3abb4d5f 991 interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
6a7742b4
SS		 992 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
993 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
994 clock-names = "clkp1", "clkp2", "can_clk";
484adb00 995 power-domains = <&cpg_clocks>;
6a7742b4
SS		 996 status = "disabled";
997 };
998
999 can1: can@e6e88000 {
28e941de 1000 compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
6a7742b4 1001 reg = <0 0xe6e88000 0 0x1000>;
3abb4d5f 1002 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
6a7742b4
SS		 1003 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
1004 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
1005 clock-names = "clkp1", "clkp2", "can_clk";
484adb00 1006 power-domains = <&cpg_clocks>;
6a7742b4
SS		 1007 status = "disabled";
1008 };
1009
fb847575 1010 jpu: jpeg-codec@fe980000 {
1c4b68fd 1011 compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
fb847575 1012 reg = <0 0xfe980000 0 0x10300>;
3abb4d5f 1013 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
fb847575 1014 clocks = <&mstp1_clks R8A7790_CLK_JPU>;
484adb00 1015 power-domains = <&cpg_clocks>;
fb847575
MU		 1016 };
1017
22a1f595
LP		 1018 clocks {
1019 #address-cells = <2>;
1020 #size-cells = <2>;
1021 ranges;
1022
1023 /* External root clock */
b19dd47b 1024 extal_clk: extal {
22a1f595
LP		 1025 compatible = "fixed-clock";
1026 #clock-cells = <0>;
1027 /* This value must be overriden by the board. */
1028 clock-frequency = <0>;
22a1f595
LP		 1029 };
1030
51d17918 1031 /* External PCIe clock - can be overridden by the board */
b19dd47b 1032 pcie_bus_clk: pcie_bus {
51d17918
PE		 1033 compatible = "fixed-clock";
1034 #clock-cells = <0>;
1035 clock-frequency = <100000000>;
51d17918
PE		 1036 status = "disabled";
1037 };
1038
c7c2ec3a
KM		 1039 /*
1040 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
1041 * default. Boards that provide audio clocks should override them.
1042 */
1043 audio_clk_a: audio_clk_a {
1044 compatible = "fixed-clock";
1045 #clock-cells = <0>;
1046 clock-frequency = <0>;
c7c2ec3a
KM		 1047 };
1048 audio_clk_b: audio_clk_b {
1049 compatible = "fixed-clock";
1050 #clock-cells = <0>;
1051 clock-frequency = <0>;
c7c2ec3a
KM		 1052 };
1053 audio_clk_c: audio_clk_c {
1054 compatible = "fixed-clock";
1055 #clock-cells = <0>;
1056 clock-frequency = <0>;
c7c2ec3a
KM		 1057 };
1058
42af65e8
GU		 1059 /* External SCIF clock */
1060 scif_clk: scif {
1061 compatible = "fixed-clock";
1062 #clock-cells = <0>;
1063 /* This value must be overridden by the board. */
1064 clock-frequency = <0>;
1065 status = "disabled";
1066 };
1067
41650f40 1068 /* External USB clock - can be overridden by the board */
b19dd47b 1069 usb_extal_clk: usb_extal {
41650f40
SS		 1070 compatible = "fixed-clock";
1071 #clock-cells = <0>;
1072 clock-frequency = <48000000>;
41650f40
SS		 1073 };
1074
1075 /* External CAN clock */
1076 can_clk: can_clk {
1077 compatible = "fixed-clock";
1078 #clock-cells = <0>;
1079 /* This value must be overridden by the board. */
1080 clock-frequency = <0>;
41650f40
SS		 1081 status = "disabled";
1082 };
1083
22a1f595
LP		 1084 /* Special CPG clocks */
1085 cpg_clocks: cpg_clocks@e6150000 {
1086 compatible = "renesas,r8a7790-cpg-clocks",
1087 "renesas,rcar-gen2-cpg-clocks";
1088 reg = <0 0xe6150000 0 0x1000>;
41650f40 1089 clocks = <&extal_clk &usb_extal_clk>;
22a1f595
LP		 1090 #clock-cells = <1>;
1091 clock-output-names = "main", "pll0", "pll1", "pll3",
1092 "lb", "qspi", "sdh", "sd0", "sd1",
3453ca9e 1093 "z", "rcan", "adsp";
484adb00 1094 #power-domain-cells = <0>;
22a1f595
LP		 1095 };
1096
1097 /* Variable factor clocks */
b19dd47b 1098 sd2_clk: sd2@e6150078 {
22a1f595
LP		 1099 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1100 reg = <0 0xe6150078 0 4>;
1101 clocks = <&pll1_div2_clk>;
1102 #clock-cells = <0>;
22a1f595 1103 };
b19dd47b 1104 sd3_clk: sd3@e615026c {
22a1f595 1105 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
edd7b938 1106 reg = <0 0xe615026c 0 4>;
22a1f595
LP		 1107 clocks = <&pll1_div2_clk>;
1108 #clock-cells = <0>;
22a1f595 1109 };
b19dd47b 1110 mmc0_clk: mmc0@e6150240 {
22a1f595
LP		 1111 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1112 reg = <0 0xe6150240 0 4>;
1113 clocks = <&pll1_div2_clk>;
1114 #clock-cells = <0>;
22a1f595 1115 };
b19dd47b 1116 mmc1_clk: mmc1@e6150244 {
22a1f595
LP		 1117 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1118 reg = <0 0xe6150244 0 4>;
1119 clocks = <&pll1_div2_clk>;
1120 #clock-cells = <0>;
22a1f595 1121 };
b19dd47b 1122 ssp_clk: ssp@e6150248 {
22a1f595
LP		 1123 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1124 reg = <0 0xe6150248 0 4>;
1125 clocks = <&pll1_div2_clk>;
1126 #clock-cells = <0>;
22a1f595 1127 };
b19dd47b 1128 ssprs_clk: ssprs@e615024c {
22a1f595
LP		 1129 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
1130 reg = <0 0xe615024c 0 4>;
1131 clocks = <&pll1_div2_clk>;
1132 #clock-cells = <0>;
22a1f595
LP		 1133 };
1134
1135 /* Fixed factor clocks */
b19dd47b 1136 pll1_div2_clk: pll1_div2 {
22a1f595
LP		 1137 compatible = "fixed-factor-clock";
1138 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1139 #clock-cells = <0>;
1140 clock-div = <2>;
1141 clock-mult = <1>;
22a1f595 1142 };
b19dd47b 1143 z2_clk: z2 {
22a1f595
LP		 1144 compatible = "fixed-factor-clock";
1145 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1146 #clock-cells = <0>;
1147 clock-div = <2>;
1148 clock-mult = <1>;
22a1f595 1149 };
b19dd47b 1150 zg_clk: zg {
22a1f595
LP		 1151 compatible = "fixed-factor-clock";
1152 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1153 #clock-cells = <0>;
1154 clock-div = <3>;
1155 clock-mult = <1>;
22a1f595 1156 };
b19dd47b 1157 zx_clk: zx {
22a1f595
LP		 1158 compatible = "fixed-factor-clock";
1159 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1160 #clock-cells = <0>;
1161 clock-div = <3>;
1162 clock-mult = <1>;
22a1f595 1163 };
b19dd47b 1164 zs_clk: zs {
22a1f595
LP		 1165 compatible = "fixed-factor-clock";
1166 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1167 #clock-cells = <0>;
1168 clock-div = <6>;
1169 clock-mult = <1>;
22a1f595 1170 };
b19dd47b 1171 hp_clk: hp {
22a1f595
LP		 1172 compatible = "fixed-factor-clock";
1173 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1174 #clock-cells = <0>;
1175 clock-div = <12>;
1176 clock-mult = <1>;
22a1f595 1177 };
b19dd47b 1178 i_clk: i {
22a1f595
LP		 1179 compatible = "fixed-factor-clock";
1180 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1181 #clock-cells = <0>;
1182 clock-div = <2>;
1183 clock-mult = <1>;
22a1f595 1184 };
b19dd47b 1185 b_clk: b {
22a1f595
LP		 1186 compatible = "fixed-factor-clock";
1187 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1188 #clock-cells = <0>;
1189 clock-div = <12>;
1190 clock-mult = <1>;
22a1f595 1191 };
b19dd47b 1192 p_clk: p {
22a1f595
LP		 1193 compatible = "fixed-factor-clock";
1194 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1195 #clock-cells = <0>;
1196 clock-div = <24>;
1197 clock-mult = <1>;
22a1f595 1198 };
b19dd47b 1199 cl_clk: cl {
22a1f595
LP		 1200 compatible = "fixed-factor-clock";
1201 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1202 #clock-cells = <0>;
1203 clock-div = <48>;
1204 clock-mult = <1>;
22a1f595 1205 };
b19dd47b 1206 m2_clk: m2 {
22a1f595
LP		 1207 compatible = "fixed-factor-clock";
1208 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1209 #clock-cells = <0>;
1210 clock-div = <8>;
1211 clock-mult = <1>;
22a1f595 1212 };
b19dd47b 1213 imp_clk: imp {
22a1f595
LP		 1214 compatible = "fixed-factor-clock";
1215 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1216 #clock-cells = <0>;
1217 clock-div = <4>;
1218 clock-mult = <1>;
22a1f595 1219 };
b19dd47b 1220 rclk_clk: rclk {
22a1f595
LP		 1221 compatible = "fixed-factor-clock";
1222 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1223 #clock-cells = <0>;
1224 clock-div = <(48 * 1024)>;
1225 clock-mult = <1>;
22a1f595 1226 };
b19dd47b 1227 oscclk_clk: oscclk {
22a1f595
LP		 1228 compatible = "fixed-factor-clock";
1229 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
1230 #clock-cells = <0>;
1231 clock-div = <(12 * 1024)>;
1232 clock-mult = <1>;
22a1f595 1233 };
b19dd47b 1234 zb3_clk: zb3 {
22a1f595
LP		 1235 compatible = "fixed-factor-clock";
1236 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1237 #clock-cells = <0>;
1238 clock-div = <4>;
1239 clock-mult = <1>;
22a1f595 1240 };
b19dd47b 1241 zb3d2_clk: zb3d2 {
22a1f595
LP		 1242 compatible = "fixed-factor-clock";
1243 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1244 #clock-cells = <0>;
1245 clock-div = <8>;
1246 clock-mult = <1>;
22a1f595 1247 };
b19dd47b 1248 ddr_clk: ddr {
22a1f595
LP		 1249 compatible = "fixed-factor-clock";
1250 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
1251 #clock-cells = <0>;
1252 clock-div = <8>;
1253 clock-mult = <1>;
22a1f595 1254 };
b19dd47b 1255 mp_clk: mp {
22a1f595
LP		 1256 compatible = "fixed-factor-clock";
1257 clocks = <&pll1_div2_clk>;
1258 #clock-cells = <0>;
1259 clock-div = <15>;
1260 clock-mult = <1>;
22a1f595 1261 };
b19dd47b 1262 cp_clk: cp {
22a1f595
LP		 1263 compatible = "fixed-factor-clock";
1264 clocks = <&extal_clk>;
1265 #clock-cells = <0>;
1266 clock-div = <2>;
1267 clock-mult = <1>;
22a1f595
LP		 1268 };
1269
1270 /* Gate clocks */
9d90951a
LP		 1271 mstp0_clks: mstp0_clks@e6150130 {
1272 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1273 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1274 clocks = <&mp_clk>;
1275 #clock-cells = <1>;
b54010af 1276 clock-indices = <R8A7790_CLK_MSIOF0>;
9d90951a
LP		 1277 clock-output-names = "msiof0";
1278 };
22a1f595
LP		 1279 mstp1_clks: mstp1_clks@e6150134 {
1280 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1281 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
4ba8f246
YH		 1282 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
1283 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
1284 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
1285 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
22a1f595 1286 #clock-cells = <1>;
b54010af 1287 clock-indices = <
4ba8f246
YH		 1288 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
1289 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
1290 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
1291 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
1292 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
1293 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
1294 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
22a1f595
LP		 1295 >;
1296 clock-output-names =
4ba8f246
YH		 1297 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
1298 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
1299 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
2284ff5f 1300 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
22a1f595
LP		 1301 };
1302 mstp2_clks: mstp2_clks@e6150138 {
1303 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1304 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1305 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
c819acda
LP		 1306 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1307 <&zs_clk>;
22a1f595 1308 #clock-cells = <1>;
b54010af 1309 clock-indices = <
22a1f595 1310 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
9d90951a
LP		 1311 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1312 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
c819acda 1313 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
22a1f595
LP		 1314 >;
1315 clock-output-names =
9d90951a 1316 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
c819acda
LP		 1317 "scifb1", "msiof1", "msiof3", "scifb2",
1318 "sys-dmac1", "sys-dmac0";
22a1f595
LP		 1319 };
1320 mstp3_clks: mstp3_clks@e615013c {
1321 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1322 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
38805823 1323 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
17465149 1324 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
b02ce79f
YS		 1325 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1326 <&hp_clk>, <&hp_clk>;
22a1f595 1327 #clock-cells = <1>;
b54010af 1328 clock-indices = <
38805823 1329 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
17465149 1330 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
ecafea8c 1331 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
b02ce79f 1332 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
22a1f595
LP		 1333 >;
1334 clock-output-names =
38805823 1335 "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
17465149 1336 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
b02ce79f
YS		 1337 "iic0", "pciec", "iic1", "ssusb", "cmt1",
1338 "usbdmac0", "usbdmac1";
22a1f595 1339 };
61624caf
GU		 1340 mstp4_clks: mstp4_clks@e6150140 {
1341 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1342 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
1343 clocks = <&cp_clk>;
1344 #clock-cells = <1>;
1345 clock-indices = <R8A7790_CLK_IRQC>;
1346 clock-output-names = "irqc";
1347 };
22a1f595
LP		 1348 mstp5_clks: mstp5_clks@e6150144 {
1349 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1350 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
3453ca9e
SS		 1351 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1352 <&extal_clk>, <&p_clk>;
22a1f595 1353 #clock-cells = <1>;
b54010af
BD		 1354 clock-indices = <
1355 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
3453ca9e
SS		 1356 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1357 R8A7790_CLK_PWM
b54010af 1358 >;
3453ca9e
SS		 1359 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1360 "thermal", "pwm";
22a1f595
LP		 1361 };
1362 mstp7_clks: mstp7_clks@e615014c {
1363 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1364 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
b621f6d4 1365 clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
22a1f595
LP		 1366 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1367 <&zx_clk>;
1368 #clock-cells = <1>;
b54010af 1369 clock-indices = <
22a1f595
LP		 1370 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1371 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1372 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1373 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1374 >;
1375 clock-output-names =
1376 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1377 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1378 };
1379 mstp8_clks: mstp8_clks@e6150990 {
1380 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1381 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
f6b5dd40 1382 clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
63d2d750
SS		 1383 <&zg_clk>, <&hp_clk>, <&p_clk>, <&zs_clk>,
1384 <&zs_clk>;
22a1f595 1385 #clock-cells = <1>;
b54010af 1386 clock-indices = <
f6b5dd40 1387 R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2
63d2d750
SS		 1388 R8A7790_CLK_VIN1 R8A7790_CLK_VIN0
1389 R8A7790_CLK_ETHERAVB R8A7790_CLK_ETHER
f6b5dd40 1390 R8A7790_CLK_SATA1 R8A7790_CLK_SATA0
3f2beaa9 1391 >;
bccccc3d 1392 clock-output-names =
63d2d750
SS		 1393 "mlb", "vin3", "vin2", "vin1", "vin0",
1394 "etheravb", "ether", "sata1", "sata0";
22a1f595
LP		 1395 };
1396 mstp9_clks: mstp9_clks@e6150994 {
1397 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1398 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
81f6883f
GU		 1399 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1400 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1401 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
3672b059 1402 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
22a1f595 1403 #clock-cells = <1>;
b54010af 1404 clock-indices = <
81f6883f
GU		 1405 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1406 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
17465149
WS		 1407 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1408 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
22a1f595 1409 >;
91b56ca1 1410 clock-output-names =
81f6883f 1411 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
17465149
WS		 1412 "rcan1", "rcan0", "qspi_mod", "iic3",
1413 "i2c3", "i2c2", "i2c1", "i2c0";
22a1f595 1414 };
bcde3722
KM		 1415 mstp10_clks: mstp10_clks@e6150998 {
1416 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1417 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1418 clocks = <&p_clk>,
1419 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1420 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1421 <&p_clk>,
1422 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1423 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1424 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1425 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1426 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
a7163784 1427 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
bcde3722
KM		 1428 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1429
1430 #clock-cells = <1>;
1431 clock-indices = <
1432 R8A7790_CLK_SSI_ALL
1433 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1434 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1435 R8A7790_CLK_SCU_ALL
1436 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
a7163784 1437 R8A7790_CLK_SCU_CTU1_MIX1 R8A7790_CLK_SCU_CTU0_MIX0
bcde3722
KM		 1438 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1439 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1440 >;
1441 clock-output-names =
1442 "ssi-all",
1443 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1444 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1445 "scu-all",
1446 "scu-dvc1", "scu-dvc0",
a7163784 1447 "scu-ctu1-mix1", "scu-ctu0-mix0",
bcde3722
KM		 1448 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1449 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1450 };
22a1f595 1451 };
7053e134 1452
fad6d45c 1453 qspi: spi@e6b10000 {
7053e134
GU		 1454 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1455 reg = <0 0xe6b10000 0 0x2c>;
3abb4d5f 1456 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
7053e134 1457 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
37cf3d61
GU		 1458 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1459 dma-names = "tx", "rx";
484adb00 1460 power-domains = <&cpg_clocks>;
7053e134
GU		 1461 num-cs = <1>;
1462 #address-cells = <1>;
1463 #size-cells = <0>;
1464 status = "disabled";
1465 };
ae8a6146
GU		 1466
1467 msiof0: spi@e6e20000 {
1468 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1469 reg = <0 0xe6e20000 0 0x0064>;
3abb4d5f 1470 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
ae8a6146 1471 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
fbff6688
GU		 1472 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1473 dma-names = "tx", "rx";
484adb00 1474 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1475 #address-cells = <1>;
1476 #size-cells = <0>;
1477 status = "disabled";
1478 };
1479
1480 msiof1: spi@e6e10000 {
1481 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1482 reg = <0 0xe6e10000 0 0x0064>;
3abb4d5f 1483 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
ae8a6146 1484 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
fbff6688
GU		 1485 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1486 dma-names = "tx", "rx";
484adb00 1487 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1488 #address-cells = <1>;
1489 #size-cells = <0>;
1490 status = "disabled";
1491 };
1492
1493 msiof2: spi@e6e00000 {
1494 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1495 reg = <0 0xe6e00000 0 0x0064>;
3abb4d5f 1496 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
ae8a6146 1497 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
fbff6688
GU		 1498 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1499 dma-names = "tx", "rx";
484adb00 1500 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1501 #address-cells = <1>;
1502 #size-cells = <0>;
1503 status = "disabled";
1504 };
1505
1506 msiof3: spi@e6c90000 {
1507 compatible = "renesas,msiof-r8a7790";
c7d1f08a 1508 reg = <0 0xe6c90000 0 0x0064>;
3abb4d5f 1509 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
ae8a6146 1510 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
fbff6688
GU		 1511 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1512 dma-names = "tx", "rx";
484adb00 1513 power-domains = <&cpg_clocks>;
ae8a6146
GU		 1514 #address-cells = <1>;
1515 #size-cells = <0>;
1516 status = "disabled";
1517 };
7df2fd57 1518
157fcd8a 1519 xhci: usb@ee000000 {
92cc7798 1520 compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
157fcd8a 1521 reg = <0 0xee000000 0 0xc00>;
3abb4d5f 1522 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
157fcd8a 1523 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
484adb00 1524 power-domains = <&cpg_clocks>;
157fcd8a
YS		 1525 phys = <&usb2 1>;
1526 phy-names = "usb";
1527 status = "disabled";
1528 };
1529
ff4f3eb8 1530 pci0: pci@ee090000 {
2d82c144 1531 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
ff4f3eb8 1532 device_type = "pci";
ff4f3eb8
BD		 1533 reg = <0 0xee090000 0 0xc00>,
1534 <0 0xee080000 0 0x1100>;
3abb4d5f 1535 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 1536 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1537 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1538 status = "disabled";
1539
1540 bus-range = <0 0>;
1541 #address-cells = <3>;
1542 #size-cells = <2>;
1543 #interrupt-cells = <1>;
1544 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1545 interrupt-map-mask = <0xff00 0 0 0x7>;
3abb4d5f
SH		 1546 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1547 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH
1548 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1549
1550 usb@0,1 {
1551 reg = <0x800 0 0 0 0>;
1552 device_type = "pci";
1553 phys = <&usb0 0>;
1554 phy-names = "usb";
1555 };
1556
1557 usb@0,2 {
1558 reg = <0x1000 0 0 0 0>;
1559 device_type = "pci";
1560 phys = <&usb0 0>;
1561 phy-names = "usb";
1562 };
ff4f3eb8
BD		 1563 };
1564
1565 pci1: pci@ee0b0000 {
2d82c144 1566 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
ff4f3eb8 1567 device_type = "pci";
ff4f3eb8
BD		 1568 reg = <0 0xee0b0000 0 0xc00>,
1569 <0 0xee0a0000 0 0x1100>;
3abb4d5f 1570 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
484adb00
GU		 1571 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1572 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1573 status = "disabled";
1574
1575 bus-range = <1 1>;
1576 #address-cells = <3>;
1577 #size-cells = <2>;
1578 #interrupt-cells = <1>;
1579 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1580 interrupt-map-mask = <0xff00 0 0 0x7>;
3abb4d5f
SH		 1581 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1582 0x0800 0 0 1 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
1583 0x1000 0 0 2 &gic GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
ff4f3eb8
BD		 1584 };
1585
1586 pci2: pci@ee0d0000 {
2d82c144 1587 compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
ff4f3eb8
BD		 1588 device_type = "pci";
1589 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
484adb00 1590 power-domains = <&cpg_clocks>;
ff4f3eb8
BD		 1591 reg = <0 0xee0d0000 0 0xc00>,
1592 <0 0xee0c0000 0 0x1100>;
3abb4d5f 1593 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
ff4f3eb8
BD		 1594 status = "disabled";
1595
1596 bus-range = <2 2>;
1597 #address-cells = <3>;
1598 #size-cells = <2>;
1599 #interrupt-cells = <1>;
1600 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1601 interrupt-map-mask = <0xff00 0 0 0x7>;
3abb4d5f
SH		 1602 interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1603 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
1604 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1605
1606 usb@0,1 {
1607 reg = <0x800 0 0 0 0>;
1608 device_type = "pci";
1609 phys = <&usb2 0>;
1610 phy-names = "usb";
1611 };
1612
1613 usb@0,2 {
1614 reg = <0x1000 0 0 0 0>;
1615 device_type = "pci";
1616 phys = <&usb2 0>;
1617 phy-names = "usb";
1618 };
ff4f3eb8
BD		 1619 };
1620
745329d2 1621 pciec: pcie@fe000000 {
e670be8d 1622 compatible = "renesas,pcie-r8a7790", "renesas,pcie-rcar-gen2";
745329d2
PE		 1623 reg = <0 0xfe000000 0 0x80000>;
1624 #address-cells = <3>;
1625 #size-cells = <2>;
1626 bus-range = <0x00 0xff>;
1627 device_type = "pci";
1628 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1629 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1630 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1631 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1632 /* Map all possible DDR as inbound ranges */
1633 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1634 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
3abb4d5f
SH		 1635 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
1636 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
1637 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
745329d2
PE		 1638 #interrupt-cells = <1>;
1639 interrupt-map-mask = <0 0 0 0>;
3abb4d5f 1640 interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
745329d2
PE		 1641 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1642 clock-names = "pcie", "pcie_bus";
484adb00 1643 power-domains = <&cpg_clocks>;
745329d2
PE		 1644 status = "disabled";
1645 };
1646
b694e380 1647 rcar_sound: sound@ec500000 {
ad63241c
KM		 1648 /*
1649 * #sound-dai-cells is required
1650 *
1651 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1652 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1653 */
31078ecd 1654 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2";
7df2fd57
KM		 1655 reg = <0 0xec500000 0 0x1000>, /* SCU */
1656 <0 0xec5a0000 0 0x100>, /* ADG */
1657 <0 0xec540000 0 0x1000>, /* SSIU */
4bc4a205 1658 <0 0xec541000 0 0x280>, /* SSI */
0c602677
KM		 1659 <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
1660 reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
46a158f2 1661
7df2fd57
KM		 1662 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1663 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1664 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1665 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1666 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1667 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1668 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1669 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1670 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1671 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1672 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
a7163784 1673 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
fc67bf42 1674 <&mstp10_clks R8A7790_CLK_SCU_CTU0_MIX0>, <&mstp10_clks R8A7790_CLK_SCU_CTU1_MIX1>,
334d69a2 1675 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
7df2fd57
KM		 1676 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1677 clock-names = "ssi-all",
1678 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1679 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1680 "src.9", "src.8", "src.7", "src.6", "src.5",
1681 "src.4", "src.3", "src.2", "src.1", "src.0",
a7163784 1682 "ctu.0", "ctu.1",
fc67bf42 1683 "mix.0", "mix.1",
334d69a2 1684 "dvc.0", "dvc.1",
7df2fd57 1685 "clk_a", "clk_b", "clk_c", "clk_i";
6507c4ef 1686 power-domains = <&cpg_clocks>;
7df2fd57
KM		 1687
1688 status = "disabled";
1689
334d69a2 1690 rcar_sound,dvc {
118a5093
KM		 1691 dvc0: dvc@0 {
1692 dmas = <&audma0 0xbc>;
1693 dma-names = "tx";
1694 };
1695 dvc1: dvc@1 {
1696 dmas = <&audma0 0xbe>;
1697 dma-names = "tx";
1698 };
334d69a2
KM		 1699 };
1700
fc67bf42
KM		 1701 rcar_sound,mix {
1702 mix0: mix@0 { };
1703 mix1: mix@1 { };
1704 };
1705
a7163784
KM		 1706 rcar_sound,ctu {
1707 ctu00: ctu@0 { };
1708 ctu01: ctu@1 { };
1709 ctu02: ctu@2 { };
1710 ctu03: ctu@3 { };
1711 ctu10: ctu@4 { };
1712 ctu11: ctu@5 { };
1713 ctu12: ctu@6 { };
1714 ctu13: ctu@7 { };
1715 };
1716
7df2fd57 1717 rcar_sound,src {
118a5093 1718 src0: src@0 {
3abb4d5f 1719 interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1720 dmas = <&audma0 0x85>, <&audma1 0x9a>;
1721 dma-names = "rx", "tx";
1722 };
1723 src1: src@1 {
3abb4d5f 1724 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1725 dmas = <&audma0 0x87>, <&audma1 0x9c>;
1726 dma-names = "rx", "tx";
1727 };
1728 src2: src@2 {
3abb4d5f 1729 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1730 dmas = <&audma0 0x89>, <&audma1 0x9e>;
1731 dma-names = "rx", "tx";
1732 };
1733 src3: src@3 {
3abb4d5f 1734 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1735 dmas = <&audma0 0x8b>, <&audma1 0xa0>;
1736 dma-names = "rx", "tx";
1737 };
1738 src4: src@4 {
3abb4d5f 1739 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1740 dmas = <&audma0 0x8d>, <&audma1 0xb0>;
1741 dma-names = "rx", "tx";
1742 };
1743 src5: src@5 {
3abb4d5f 1744 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1745 dmas = <&audma0 0x8f>, <&audma1 0xb2>;
1746 dma-names = "rx", "tx";
1747 };
1748 src6: src@6 {
3abb4d5f 1749 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1750 dmas = <&audma0 0x91>, <&audma1 0xb4>;
1751 dma-names = "rx", "tx";
1752 };
1753 src7: src@7 {
3abb4d5f 1754 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1755 dmas = <&audma0 0x93>, <&audma1 0xb6>;
1756 dma-names = "rx", "tx";
1757 };
1758 src8: src@8 {
3abb4d5f 1759 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1760 dmas = <&audma0 0x95>, <&audma1 0xb8>;
1761 dma-names = "rx", "tx";
1762 };
1763 src9: src@9 {
3abb4d5f 1764 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1765 dmas = <&audma0 0x97>, <&audma1 0xba>;
1766 dma-names = "rx", "tx";
1767 };
7df2fd57
KM		 1768 };
1769
1770 rcar_sound,ssi {
118a5093 1771 ssi0: ssi@0 {
3abb4d5f 1772 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1773 dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>;
1774 dma-names = "rx", "tx", "rxu", "txu";
1775 };
1776 ssi1: ssi@1 {
3abb4d5f 1777 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1778 dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>;
1779 dma-names = "rx", "tx", "rxu", "txu";
1780 };
1781 ssi2: ssi@2 {
3abb4d5f 1782 interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1783 dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>;
1784 dma-names = "rx", "tx", "rxu", "txu";
1785 };
1786 ssi3: ssi@3 {
3abb4d5f 1787 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1788 dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>;
1789 dma-names = "rx", "tx", "rxu", "txu";
1790 };
1791 ssi4: ssi@4 {
3abb4d5f 1792 interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1793 dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>;
1794 dma-names = "rx", "tx", "rxu", "txu";
1795 };
1796 ssi5: ssi@5 {
3abb4d5f 1797 interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1798 dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>;
1799 dma-names = "rx", "tx", "rxu", "txu";
1800 };
1801 ssi6: ssi@6 {
3abb4d5f 1802 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1803 dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>;
1804 dma-names = "rx", "tx", "rxu", "txu";
1805 };
1806 ssi7: ssi@7 {
3abb4d5f 1807 interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1808 dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>;
1809 dma-names = "rx", "tx", "rxu", "txu";
1810 };
1811 ssi8: ssi@8 {
3abb4d5f 1812 interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1813 dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>;
1814 dma-names = "rx", "tx", "rxu", "txu";
1815 };
1816 ssi9: ssi@9 {
3abb4d5f 1817 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
118a5093
KM		 1818 dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>;
1819 dma-names = "rx", "tx", "rxu", "txu";
1820 };
7df2fd57
KM		 1821 };
1822 };
70496727
LP		 1823
1824 ipmmu_sy0: mmu@e6280000 {
c8d6686e 1825 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1826 reg = <0 0xe6280000 0 0x1000>;
3abb4d5f
SH		 1827 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>,
1828 <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1829 #iommu-cells = <1>;
1830 status = "disabled";
1831 };
1832
1833 ipmmu_sy1: mmu@e6290000 {
c8d6686e 1834 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1835 reg = <0 0xe6290000 0 0x1000>;
3abb4d5f 1836 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1837 #iommu-cells = <1>;
1838 status = "disabled";
1839 };
1840
1841 ipmmu_ds: mmu@e6740000 {
c8d6686e 1842 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1843 reg = <0 0xe6740000 0 0x1000>;
3abb4d5f
SH		 1844 interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
1845 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1846 #iommu-cells = <1>;
1847 status = "disabled";
1848 };
1849
1850 ipmmu_mp: mmu@ec680000 {
c8d6686e 1851 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1852 reg = <0 0xec680000 0 0x1000>;
3abb4d5f 1853 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1854 #iommu-cells = <1>;
1855 status = "disabled";
1856 };
1857
1858 ipmmu_mx: mmu@fe951000 {
c8d6686e 1859 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1860 reg = <0 0xfe951000 0 0x1000>;
3abb4d5f
SH		 1861 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>,
1862 <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1863 #iommu-cells = <1>;
1864 status = "disabled";
1865 };
1866
1867 ipmmu_rt: mmu@ffc80000 {
c8d6686e 1868 compatible = "renesas,ipmmu-r8a7790", "renesas,ipmmu-vmsa";
70496727 1869 reg = <0 0xffc80000 0 0x1000>;
3abb4d5f 1870 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
70496727
LP		 1871 #iommu-cells = <1>;
1872 status = "disabled";
1873 };
0468b2d6 1874};
Linux kernel - Deliverables
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