projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 0468b2d6 MD |
1 | /* |
| 2 | * Device Tree Source for the r8a7790 SoC | |
| 3 | * | |
| d8913c67 SS |
4 | * Copyright (C) 2013-2014 Renesas Solutions Corp. |
| 5 | * Copyright (C) 2014 Cogent Embedded Inc. | |
| 0468b2d6 MD |
6 | * |
| 7 | * This file is licensed under the terms of the GNU General Public License | |
| 8 | * version 2. This program is licensed "as is" without any warranty of any | |
| 9 | * kind, whether express or implied. | |
| 10 | */ | |
| 11 | ||
| 22a1f595 | 12 | #include <dt-bindings/clock/r8a7790-clock.h> |
| 5f75e73c LP |
13 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 14 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 15 | ||
| 0468b2d6 MD |
16 | / { |
| 17 | compatible = "renesas,r8a7790"; | |
| 18 | interrupt-parent = <&gic>; | |
| 8585deb1 TY |
19 | #address-cells = <2>; |
| 20 | #size-cells = <2>; | |
| 0468b2d6 | 21 | |
| 6b1d7c68 WS |
22 | aliases { |
| 23 | i2c0 = &i2c0; | |
| 24 | i2c1 = &i2c1; | |
| 25 | i2c2 = &i2c2; | |
| 26 | i2c3 = &i2c3; | |
| 05f39916 WS |
27 | i2c4 = &iic0; |
| 28 | i2c5 = &iic1; | |
| 29 | i2c6 = &iic2; | |
| 30 | i2c7 = &iic3; | |
| fad6d45c | 31 | spi0 = &qspi; |
| ae8a6146 GU |
32 | spi1 = &msiof0; |
| 33 | spi2 = &msiof1; | |
| 34 | spi3 = &msiof2; | |
| 35 | spi4 = &msiof3; | |
| 9f685bfc BD |
36 | vin0 = &vin0; |
| 37 | vin1 = &vin1; | |
| 38 | vin2 = &vin2; | |
| 39 | vin3 = &vin3; | |
| 6b1d7c68 WS |
40 | }; |
| 41 | ||
| 0468b2d6 MD |
42 | cpus { |
| 43 | #address-cells = <1>; | |
| 44 | #size-cells = <0>; | |
| 45 | ||
| 46 | cpu0: cpu@0 { | |
| 47 | device_type = "cpu"; | |
| 48 | compatible = "arm,cortex-a15"; | |
| 49 | reg = <0>; | |
| 50 | clock-frequency = <1300000000>; | |
| b989e138 BC |
51 | voltage-tolerance = <1>; /* 1% */ |
| 52 | clocks = <&cpg_clocks R8A7790_CLK_Z>; | |
| 53 | clock-latency = <300000>; /* 300 us */ | |
| 54 | ||
| 55 | /* kHz - uV - OPPs unknown yet */ | |
| 56 | operating-points = <1400000 1000000>, | |
| 57 | <1225000 1000000>, | |
| 58 | <1050000 1000000>, | |
| 59 | < 875000 1000000>, | |
| 60 | < 700000 1000000>, | |
| 61 | < 350000 1000000>; | |
| 0468b2d6 | 62 | }; |
| c1f95979 MD |
63 | |
| 64 | cpu1: cpu@1 { | |
| 65 | device_type = "cpu"; | |
| 66 | compatible = "arm,cortex-a15"; | |
| 67 | reg = <1>; | |
| 68 | clock-frequency = <1300000000>; | |
| 69 | }; | |
| 70 | ||
| 71 | cpu2: cpu@2 { | |
| 72 | device_type = "cpu"; | |
| 73 | compatible = "arm,cortex-a15"; | |
| 74 | reg = <2>; | |
| 75 | clock-frequency = <1300000000>; | |
| 76 | }; | |
| 77 | ||
| 78 | cpu3: cpu@3 { | |
| 79 | device_type = "cpu"; | |
| 80 | compatible = "arm,cortex-a15"; | |
| 81 | reg = <3>; | |
| 82 | clock-frequency = <1300000000>; | |
| 83 | }; | |
| 2007e74c MD |
84 | |
| 85 | cpu4: cpu@4 { | |
| 86 | device_type = "cpu"; | |
| 87 | compatible = "arm,cortex-a7"; | |
| 88 | reg = <0x100>; | |
| 89 | clock-frequency = <780000000>; | |
| 90 | }; | |
| 91 | ||
| 92 | cpu5: cpu@5 { | |
| 93 | device_type = "cpu"; | |
| 94 | compatible = "arm,cortex-a7"; | |
| 95 | reg = <0x101>; | |
| 96 | clock-frequency = <780000000>; | |
| 97 | }; | |
| 98 | ||
| 99 | cpu6: cpu@6 { | |
| 100 | device_type = "cpu"; | |
| 101 | compatible = "arm,cortex-a7"; | |
| 102 | reg = <0x102>; | |
| 103 | clock-frequency = <780000000>; | |
| 104 | }; | |
| 105 | ||
| 106 | cpu7: cpu@7 { | |
| 107 | device_type = "cpu"; | |
| 108 | compatible = "arm,cortex-a7"; | |
| 109 | reg = <0x103>; | |
| 110 | clock-frequency = <780000000>; | |
| 111 | }; | |
| 0468b2d6 MD |
112 | }; |
| 113 | ||
| 114 | gic: interrupt-controller@f1001000 { | |
| 115 | compatible = "arm,cortex-a15-gic"; | |
| 116 | #interrupt-cells = <3>; | |
| 117 | #address-cells = <0>; | |
| 118 | interrupt-controller; | |
| 8585deb1 TY |
119 | reg = <0 0xf1001000 0 0x1000>, |
| 120 | <0 0xf1002000 0 0x1000>, | |
| 121 | <0 0xf1004000 0 0x2000>, | |
| 122 | <0 0xf1006000 0 0x2000>; | |
| 5f75e73c | 123 | interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| 0468b2d6 MD |
124 | }; |
| 125 | ||
| 23de2278 | 126 | gpio0: gpio@e6050000 { |
| f98e10c8 | 127 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 128 | reg = <0 0xe6050000 0 0x50>; |
| 5f75e73c | 129 | interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
130 | #gpio-cells = <2>; |
| 131 | gpio-controller; | |
| 132 | gpio-ranges = <&pfc 0 0 32>; | |
| 133 | #interrupt-cells = <2>; | |
| 134 | interrupt-controller; | |
| 81f6883f | 135 | clocks = <&mstp9_clks R8A7790_CLK_GPIO0>; |
| f98e10c8 LP |
136 | }; |
| 137 | ||
| 23de2278 | 138 | gpio1: gpio@e6051000 { |
| f98e10c8 | 139 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 140 | reg = <0 0xe6051000 0 0x50>; |
| 5f75e73c | 141 | interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
142 | #gpio-cells = <2>; |
| 143 | gpio-controller; | |
| 144 | gpio-ranges = <&pfc 0 32 32>; | |
| 145 | #interrupt-cells = <2>; | |
| 146 | interrupt-controller; | |
| 81f6883f | 147 | clocks = <&mstp9_clks R8A7790_CLK_GPIO1>; |
| f98e10c8 LP |
148 | }; |
| 149 | ||
| 23de2278 | 150 | gpio2: gpio@e6052000 { |
| f98e10c8 | 151 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 152 | reg = <0 0xe6052000 0 0x50>; |
| 5f75e73c | 153 | interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
154 | #gpio-cells = <2>; |
| 155 | gpio-controller; | |
| 156 | gpio-ranges = <&pfc 0 64 32>; | |
| 157 | #interrupt-cells = <2>; | |
| 158 | interrupt-controller; | |
| 81f6883f | 159 | clocks = <&mstp9_clks R8A7790_CLK_GPIO2>; |
| f98e10c8 LP |
160 | }; |
| 161 | ||
| 23de2278 | 162 | gpio3: gpio@e6053000 { |
| f98e10c8 | 163 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 164 | reg = <0 0xe6053000 0 0x50>; |
| 5f75e73c | 165 | interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
166 | #gpio-cells = <2>; |
| 167 | gpio-controller; | |
| 168 | gpio-ranges = <&pfc 0 96 32>; | |
| 169 | #interrupt-cells = <2>; | |
| 170 | interrupt-controller; | |
| 81f6883f | 171 | clocks = <&mstp9_clks R8A7790_CLK_GPIO3>; |
| f98e10c8 LP |
172 | }; |
| 173 | ||
| 23de2278 | 174 | gpio4: gpio@e6054000 { |
| f98e10c8 | 175 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 176 | reg = <0 0xe6054000 0 0x50>; |
| 5f75e73c | 177 | interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
178 | #gpio-cells = <2>; |
| 179 | gpio-controller; | |
| 180 | gpio-ranges = <&pfc 0 128 32>; | |
| 181 | #interrupt-cells = <2>; | |
| 182 | interrupt-controller; | |
| 81f6883f | 183 | clocks = <&mstp9_clks R8A7790_CLK_GPIO4>; |
| f98e10c8 LP |
184 | }; |
| 185 | ||
| 23de2278 | 186 | gpio5: gpio@e6055000 { |
| f98e10c8 | 187 | compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar"; |
| 23de2278 | 188 | reg = <0 0xe6055000 0 0x50>; |
| 5f75e73c | 189 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>; |
| f98e10c8 LP |
190 | #gpio-cells = <2>; |
| 191 | gpio-controller; | |
| 192 | gpio-ranges = <&pfc 0 160 32>; | |
| 193 | #interrupt-cells = <2>; | |
| 194 | interrupt-controller; | |
| 81f6883f | 195 | clocks = <&mstp9_clks R8A7790_CLK_GPIO5>; |
| f98e10c8 LP |
196 | }; |
| 197 | ||
| 03e2f56b MD |
198 | thermal@e61f0000 { |
| 199 | compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; | |
| 200 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; | |
| 03e2f56b | 201 | interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; |
| d3a439db | 202 | clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; |
| 03e2f56b MD |
203 | }; |
| 204 | ||
| 0468b2d6 MD |
205 | timer { |
| 206 | compatible = "arm,armv7-timer"; | |
| 5f75e73c LP |
207 | interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 208 | <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 209 | <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| 210 | <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| 0468b2d6 | 211 | }; |
| 8f5ec0a5 | 212 | |
| 39cf6d73 | 213 | cmt0: timer@ffca0000 { |
| 37757030 | 214 | compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; |
| 39cf6d73 LP |
215 | reg = <0 0xffca0000 0 0x1004>; |
| 216 | interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>, | |
| 217 | <0 143 IRQ_TYPE_LEVEL_HIGH>; | |
| 218 | clocks = <&mstp1_clks R8A7790_CLK_CMT0>; | |
| 219 | clock-names = "fck"; | |
| 220 | ||
| 221 | renesas,channels-mask = <0x60>; | |
| 222 | ||
| 223 | status = "disabled"; | |
| 224 | }; | |
| 225 | ||
| 226 | cmt1: timer@e6130000 { | |
| 37757030 | 227 | compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2"; |
| 39cf6d73 LP |
228 | reg = <0 0xe6130000 0 0x1004>; |
| 229 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>, | |
| 230 | <0 121 IRQ_TYPE_LEVEL_HIGH>, | |
| 231 | <0 122 IRQ_TYPE_LEVEL_HIGH>, | |
| 232 | <0 123 IRQ_TYPE_LEVEL_HIGH>, | |
| 233 | <0 124 IRQ_TYPE_LEVEL_HIGH>, | |
| 234 | <0 125 IRQ_TYPE_LEVEL_HIGH>, | |
| 235 | <0 126 IRQ_TYPE_LEVEL_HIGH>, | |
| 236 | <0 127 IRQ_TYPE_LEVEL_HIGH>; | |
| 237 | clocks = <&mstp3_clks R8A7790_CLK_CMT1>; | |
| 238 | clock-names = "fck"; | |
| 239 | ||
| 240 | renesas,channels-mask = <0xff>; | |
| 241 | ||
| 242 | status = "disabled"; | |
| 243 | }; | |
| 244 | ||
| 8f5ec0a5 | 245 | irqc0: interrupt-controller@e61c0000 { |
| 220fc352 | 246 | compatible = "renesas,irqc-r8a7790", "renesas,irqc"; |
| 8f5ec0a5 MD |
247 | #interrupt-cells = <2>; |
| 248 | interrupt-controller; | |
| 8585deb1 | 249 | reg = <0 0xe61c0000 0 0x200>; |
| 5f75e73c LP |
250 | interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, |
| 251 | <0 1 IRQ_TYPE_LEVEL_HIGH>, | |
| 252 | <0 2 IRQ_TYPE_LEVEL_HIGH>, | |
| 253 | <0 3 IRQ_TYPE_LEVEL_HIGH>; | |
| 8f5ec0a5 | 254 | }; |
| 8c9b1aa4 | 255 | |
| b9fea49c LP |
256 | dmac0: dma-controller@e6700000 { |
| 257 | compatible = "renesas,rcar-dmac"; | |
| 258 | reg = <0 0xe6700000 0 0x20000>; | |
| 259 | interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH | |
| 260 | 0 200 IRQ_TYPE_LEVEL_HIGH | |
| 261 | 0 201 IRQ_TYPE_LEVEL_HIGH | |
| 262 | 0 202 IRQ_TYPE_LEVEL_HIGH | |
| 263 | 0 203 IRQ_TYPE_LEVEL_HIGH | |
| 264 | 0 204 IRQ_TYPE_LEVEL_HIGH | |
| 265 | 0 205 IRQ_TYPE_LEVEL_HIGH | |
| 266 | 0 206 IRQ_TYPE_LEVEL_HIGH | |
| 267 | 0 207 IRQ_TYPE_LEVEL_HIGH | |
| 268 | 0 208 IRQ_TYPE_LEVEL_HIGH | |
| 269 | 0 209 IRQ_TYPE_LEVEL_HIGH | |
| 270 | 0 210 IRQ_TYPE_LEVEL_HIGH | |
| 271 | 0 211 IRQ_TYPE_LEVEL_HIGH | |
| 272 | 0 212 IRQ_TYPE_LEVEL_HIGH | |
| 273 | 0 213 IRQ_TYPE_LEVEL_HIGH | |
| 274 | 0 214 IRQ_TYPE_LEVEL_HIGH>; | |
| 275 | interrupt-names = "error", | |
| 276 | "ch0", "ch1", "ch2", "ch3", | |
| 277 | "ch4", "ch5", "ch6", "ch7", | |
| 278 | "ch8", "ch9", "ch10", "ch11", | |
| 279 | "ch12", "ch13", "ch14"; | |
| 280 | clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>; | |
| 281 | clock-names = "fck"; | |
| 282 | #dma-cells = <1>; | |
| 283 | dma-channels = <15>; | |
| 284 | }; | |
| 285 | ||
| 286 | dmac1: dma-controller@e6720000 { | |
| 287 | compatible = "renesas,rcar-dmac"; | |
| 288 | reg = <0 0xe6720000 0 0x20000>; | |
| 289 | interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH | |
| 290 | 0 216 IRQ_TYPE_LEVEL_HIGH | |
| 291 | 0 217 IRQ_TYPE_LEVEL_HIGH | |
| 292 | 0 218 IRQ_TYPE_LEVEL_HIGH | |
| 293 | 0 219 IRQ_TYPE_LEVEL_HIGH | |
| 294 | 0 308 IRQ_TYPE_LEVEL_HIGH | |
| 295 | 0 309 IRQ_TYPE_LEVEL_HIGH | |
| 296 | 0 310 IRQ_TYPE_LEVEL_HIGH | |
| 297 | 0 311 IRQ_TYPE_LEVEL_HIGH | |
| 298 | 0 312 IRQ_TYPE_LEVEL_HIGH | |
| 299 | 0 313 IRQ_TYPE_LEVEL_HIGH | |
| 300 | 0 314 IRQ_TYPE_LEVEL_HIGH | |
| 301 | 0 315 IRQ_TYPE_LEVEL_HIGH | |
| 302 | 0 316 IRQ_TYPE_LEVEL_HIGH | |
| 303 | 0 317 IRQ_TYPE_LEVEL_HIGH | |
| 304 | 0 318 IRQ_TYPE_LEVEL_HIGH>; | |
| 305 | interrupt-names = "error", | |
| 306 | "ch0", "ch1", "ch2", "ch3", | |
| 307 | "ch4", "ch5", "ch6", "ch7", | |
| 308 | "ch8", "ch9", "ch10", "ch11", | |
| 309 | "ch12", "ch13", "ch14"; | |
| 310 | clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>; | |
| 311 | clock-names = "fck"; | |
| 312 | #dma-cells = <1>; | |
| 313 | dma-channels = <15>; | |
| 314 | }; | |
| ba3240be KM |
315 | |
| 316 | audma0: dma-controller@ec700000 { | |
| 317 | compatible = "renesas,rcar-dmac"; | |
| 318 | reg = <0 0xec700000 0 0x10000>; | |
| 319 | interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH | |
| 320 | 0 320 IRQ_TYPE_LEVEL_HIGH | |
| 321 | 0 321 IRQ_TYPE_LEVEL_HIGH | |
| 322 | 0 322 IRQ_TYPE_LEVEL_HIGH | |
| 323 | 0 323 IRQ_TYPE_LEVEL_HIGH | |
| 324 | 0 324 IRQ_TYPE_LEVEL_HIGH | |
| 325 | 0 325 IRQ_TYPE_LEVEL_HIGH | |
| 326 | 0 326 IRQ_TYPE_LEVEL_HIGH | |
| 327 | 0 327 IRQ_TYPE_LEVEL_HIGH | |
| 328 | 0 328 IRQ_TYPE_LEVEL_HIGH | |
| 329 | 0 329 IRQ_TYPE_LEVEL_HIGH | |
| 330 | 0 330 IRQ_TYPE_LEVEL_HIGH | |
| 331 | 0 331 IRQ_TYPE_LEVEL_HIGH | |
| 332 | 0 332 IRQ_TYPE_LEVEL_HIGH>; | |
| 333 | interrupt-names = "error", | |
| 334 | "ch0", "ch1", "ch2", "ch3", | |
| 335 | "ch4", "ch5", "ch6", "ch7", | |
| 336 | "ch8", "ch9", "ch10", "ch11", | |
| 337 | "ch12"; | |
| 338 | clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC0>; | |
| 339 | clock-names = "fck"; | |
| 340 | #dma-cells = <1>; | |
| 341 | dma-channels = <13>; | |
| 342 | }; | |
| 343 | ||
| 344 | audma1: dma-controller@ec720000 { | |
| 345 | compatible = "renesas,rcar-dmac"; | |
| 346 | reg = <0 0xec720000 0 0x10000>; | |
| 347 | interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH | |
| 348 | 0 333 IRQ_TYPE_LEVEL_HIGH | |
| 349 | 0 334 IRQ_TYPE_LEVEL_HIGH | |
| 350 | 0 335 IRQ_TYPE_LEVEL_HIGH | |
| 351 | 0 336 IRQ_TYPE_LEVEL_HIGH | |
| 352 | 0 337 IRQ_TYPE_LEVEL_HIGH | |
| 353 | 0 338 IRQ_TYPE_LEVEL_HIGH | |
| 354 | 0 339 IRQ_TYPE_LEVEL_HIGH | |
| 355 | 0 340 IRQ_TYPE_LEVEL_HIGH | |
| 356 | 0 341 IRQ_TYPE_LEVEL_HIGH | |
| 357 | 0 342 IRQ_TYPE_LEVEL_HIGH | |
| 358 | 0 343 IRQ_TYPE_LEVEL_HIGH | |
| 359 | 0 344 IRQ_TYPE_LEVEL_HIGH | |
| 360 | 0 345 IRQ_TYPE_LEVEL_HIGH>; | |
| 361 | interrupt-names = "error", | |
| 362 | "ch0", "ch1", "ch2", "ch3", | |
| 363 | "ch4", "ch5", "ch6", "ch7", | |
| 364 | "ch8", "ch9", "ch10", "ch11", | |
| 365 | "ch12"; | |
| 366 | clocks = <&mstp5_clks R8A7790_CLK_AUDIO_DMAC1>; | |
| 367 | clock-names = "fck"; | |
| 368 | #dma-cells = <1>; | |
| 369 | dma-channels = <13>; | |
| 370 | }; | |
| 371 | ||
| e416b66a KM |
372 | audmapp: dma-controller@ec740000 { |
| 373 | compatible = "renesas,rcar-audmapp"; | |
| 374 | #dma-cells = <1>; | |
| 375 | ||
| 376 | reg = <0 0xec740000 0 0x200>; | |
| 377 | }; | |
| 378 | ||
| edd2b9f4 GL |
379 | i2c0: i2c@e6508000 { |
| 380 | #address-cells = <1>; | |
| 381 | #size-cells = <0>; | |
| 382 | compatible = "renesas,i2c-r8a7790"; | |
| 383 | reg = <0 0xe6508000 0 0x40>; | |
| 5f75e73c | 384 | interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>; |
| 2450badf | 385 | clocks = <&mstp9_clks R8A7790_CLK_I2C0>; |
| edd2b9f4 GL |
386 | status = "disabled"; |
| 387 | }; | |
| 388 | ||
| 389 | i2c1: i2c@e6518000 { | |
| 390 | #address-cells = <1>; | |
| 391 | #size-cells = <0>; | |
| 392 | compatible = "renesas,i2c-r8a7790"; | |
| 393 | reg = <0 0xe6518000 0 0x40>; | |
| 5f75e73c | 394 | interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>; |
| 2450badf | 395 | clocks = <&mstp9_clks R8A7790_CLK_I2C1>; |
| edd2b9f4 GL |
396 | status = "disabled"; |
| 397 | }; | |
| 398 | ||
| 399 | i2c2: i2c@e6530000 { | |
| 400 | #address-cells = <1>; | |
| 401 | #size-cells = <0>; | |
| 402 | compatible = "renesas,i2c-r8a7790"; | |
| 403 | reg = <0 0xe6530000 0 0x40>; | |
| 5f75e73c | 404 | interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>; |
| 2450badf | 405 | clocks = <&mstp9_clks R8A7790_CLK_I2C2>; |
| edd2b9f4 GL |
406 | status = "disabled"; |
| 407 | }; | |
| 408 | ||
| 409 | i2c3: i2c@e6540000 { | |
| 410 | #address-cells = <1>; | |
| 411 | #size-cells = <0>; | |
| 412 | compatible = "renesas,i2c-r8a7790"; | |
| 413 | reg = <0 0xe6540000 0 0x40>; | |
| 5f75e73c | 414 | interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>; |
| 2450badf | 415 | clocks = <&mstp9_clks R8A7790_CLK_I2C3>; |
| edd2b9f4 GL |
416 | status = "disabled"; |
| 417 | }; | |
| 418 | ||
| 05f39916 WS |
419 | iic0: i2c@e6500000 { |
| 420 | #address-cells = <1>; | |
| 421 | #size-cells = <0>; | |
| 422 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
| 423 | reg = <0 0xe6500000 0 0x425>; | |
| 424 | interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>; | |
| 425 | clocks = <&mstp3_clks R8A7790_CLK_IIC0>; | |
| 0d73ca41 WS |
426 | dmas = <&dmac0 0x61>, <&dmac0 0x62>; |
| 427 | dma-names = "tx", "rx"; | |
| 05f39916 WS |
428 | status = "disabled"; |
| 429 | }; | |
| 430 | ||
| 431 | iic1: i2c@e6510000 { | |
| 432 | #address-cells = <1>; | |
| 433 | #size-cells = <0>; | |
| 434 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
| 435 | reg = <0 0xe6510000 0 0x425>; | |
| 436 | interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>; | |
| 437 | clocks = <&mstp3_clks R8A7790_CLK_IIC1>; | |
| 0d73ca41 WS |
438 | dmas = <&dmac0 0x65>, <&dmac0 0x66>; |
| 439 | dma-names = "tx", "rx"; | |
| 05f39916 WS |
440 | status = "disabled"; |
| 441 | }; | |
| 442 | ||
| 443 | iic2: i2c@e6520000 { | |
| 444 | #address-cells = <1>; | |
| 445 | #size-cells = <0>; | |
| 446 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
| 447 | reg = <0 0xe6520000 0 0x425>; | |
| 448 | interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>; | |
| 449 | clocks = <&mstp3_clks R8A7790_CLK_IIC2>; | |
| 0d73ca41 WS |
450 | dmas = <&dmac0 0x69>, <&dmac0 0x6a>; |
| 451 | dma-names = "tx", "rx"; | |
| 05f39916 WS |
452 | status = "disabled"; |
| 453 | }; | |
| 454 | ||
| 455 | iic3: i2c@e60b0000 { | |
| 456 | #address-cells = <1>; | |
| 457 | #size-cells = <0>; | |
| 458 | compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic"; | |
| 459 | reg = <0 0xe60b0000 0 0x425>; | |
| 460 | interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>; | |
| 461 | clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>; | |
| 0d73ca41 WS |
462 | dmas = <&dmac0 0x77>, <&dmac0 0x78>; |
| 463 | dma-names = "tx", "rx"; | |
| 05f39916 WS |
464 | status = "disabled"; |
| 465 | }; | |
| 466 | ||
| 22c2b78d | 467 | mmcif0: mmc@ee200000 { |
| 063e8560 | 468 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
| 8c9b1aa4 | 469 | reg = <0 0xee200000 0 0x80>; |
| 5f75e73c | 470 | interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 471 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>; |
| 108216c1 LP |
472 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>; |
| 473 | dma-names = "tx", "rx"; | |
| 8c9b1aa4 GL |
474 | reg-io-width = <4>; |
| 475 | status = "disabled"; | |
| 476 | }; | |
| 477 | ||
| b718aa44 | 478 | mmcif1: mmc@ee220000 { |
| 063e8560 | 479 | compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif"; |
| 8c9b1aa4 | 480 | reg = <0 0xee220000 0 0x80>; |
| 5f75e73c | 481 | interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 482 | clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>; |
| 108216c1 LP |
483 | dmas = <&dmac0 0xe1>, <&dmac0 0xe2>; |
| 484 | dma-names = "tx", "rx"; | |
| 8c9b1aa4 GL |
485 | reg-io-width = <4>; |
| 486 | status = "disabled"; | |
| 487 | }; | |
| 488 | ||
| 9694c778 LP |
489 | pfc: pfc@e6060000 { |
| 490 | compatible = "renesas,pfc-r8a7790"; | |
| 491 | reg = <0 0xe6060000 0 0x250>; | |
| 492 | }; | |
| 55689bfa | 493 | |
| b718aa44 | 494 | sdhi0: sd@ee100000 { |
| df1d0584 | 495 | compatible = "renesas,sdhi-r8a7790"; |
| d721a15c | 496 | reg = <0 0xee100000 0 0x200>; |
| 5f75e73c | 497 | interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 498 | clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; |
| 941fe36b LP |
499 | dmas = <&dmac1 0xcd>, <&dmac1 0xce>; |
| 500 | dma-names = "tx", "rx"; | |
| 8c9b1aa4 GL |
501 | status = "disabled"; |
| 502 | }; | |
| 503 | ||
| b718aa44 | 504 | sdhi1: sd@ee120000 { |
| df1d0584 | 505 | compatible = "renesas,sdhi-r8a7790"; |
| d721a15c | 506 | reg = <0 0xee120000 0 0x200>; |
| 5f75e73c | 507 | interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 508 | clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; |
| 941fe36b LP |
509 | dmas = <&dmac1 0xc9>, <&dmac1 0xca>; |
| 510 | dma-names = "tx", "rx"; | |
| 8c9b1aa4 GL |
511 | status = "disabled"; |
| 512 | }; | |
| 513 | ||
| b718aa44 | 514 | sdhi2: sd@ee140000 { |
| df1d0584 | 515 | compatible = "renesas,sdhi-r8a7790"; |
| 8c9b1aa4 | 516 | reg = <0 0xee140000 0 0x100>; |
| 5f75e73c | 517 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 518 | clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; |
| 941fe36b LP |
519 | dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; |
| 520 | dma-names = "tx", "rx"; | |
| 8c9b1aa4 GL |
521 | status = "disabled"; |
| 522 | }; | |
| 523 | ||
| b718aa44 | 524 | sdhi3: sd@ee160000 { |
| df1d0584 | 525 | compatible = "renesas,sdhi-r8a7790"; |
| 8c9b1aa4 | 526 | reg = <0 0xee160000 0 0x100>; |
| 5f75e73c | 527 | interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>; |
| 72197ca7 | 528 | clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; |
| 941fe36b LP |
529 | dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; |
| 530 | dma-names = "tx", "rx"; | |
| 8c9b1aa4 GL |
531 | status = "disabled"; |
| 532 | }; | |
| 22a1f595 | 533 | |
| 597af20f | 534 | scifa0: serial@e6c40000 { |
| 59d2b517 | 535 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
| 597af20f | 536 | reg = <0 0xe6c40000 0 64>; |
| 1f4c745b | 537 | interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
538 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>; |
| 539 | clock-names = "sci_ick"; | |
| 540 | status = "disabled"; | |
| 541 | }; | |
| 542 | ||
| 543 | scifa1: serial@e6c50000 { | |
| 59d2b517 | 544 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
| 597af20f | 545 | reg = <0 0xe6c50000 0 64>; |
| 1f4c745b | 546 | interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
547 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>; |
| 548 | clock-names = "sci_ick"; | |
| 549 | status = "disabled"; | |
| 550 | }; | |
| 551 | ||
| 552 | scifa2: serial@e6c60000 { | |
| 59d2b517 | 553 | compatible = "renesas,scifa-r8a7790", "renesas,scifa"; |
| 597af20f | 554 | reg = <0 0xe6c60000 0 64>; |
| 1f4c745b | 555 | interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
556 | clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>; |
| 557 | clock-names = "sci_ick"; | |
| 558 | status = "disabled"; | |
| 559 | }; | |
| 560 | ||
| 561 | scifb0: serial@e6c20000 { | |
| 59d2b517 | 562 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
| 597af20f | 563 | reg = <0 0xe6c20000 0 64>; |
| 1f4c745b | 564 | interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
565 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>; |
| 566 | clock-names = "sci_ick"; | |
| 567 | status = "disabled"; | |
| 568 | }; | |
| 569 | ||
| 570 | scifb1: serial@e6c30000 { | |
| 59d2b517 | 571 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
| 597af20f | 572 | reg = <0 0xe6c30000 0 64>; |
| 1f4c745b | 573 | interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
574 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>; |
| 575 | clock-names = "sci_ick"; | |
| 576 | status = "disabled"; | |
| 577 | }; | |
| 578 | ||
| 579 | scifb2: serial@e6ce0000 { | |
| 59d2b517 | 580 | compatible = "renesas,scifb-r8a7790", "renesas,scifb"; |
| 597af20f | 581 | reg = <0 0xe6ce0000 0 64>; |
| 1f4c745b | 582 | interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
583 | clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>; |
| 584 | clock-names = "sci_ick"; | |
| 585 | status = "disabled"; | |
| 586 | }; | |
| 587 | ||
| 588 | scif0: serial@e6e60000 { | |
| 59d2b517 | 589 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
| 597af20f | 590 | reg = <0 0xe6e60000 0 64>; |
| 1f4c745b | 591 | interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
592 | clocks = <&mstp7_clks R8A7790_CLK_SCIF0>; |
| 593 | clock-names = "sci_ick"; | |
| 594 | status = "disabled"; | |
| 595 | }; | |
| 596 | ||
| 597 | scif1: serial@e6e68000 { | |
| 59d2b517 | 598 | compatible = "renesas,scif-r8a7790", "renesas,scif"; |
| 597af20f | 599 | reg = <0 0xe6e68000 0 64>; |
| 1f4c745b | 600 | interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
601 | clocks = <&mstp7_clks R8A7790_CLK_SCIF1>; |
| 602 | clock-names = "sci_ick"; | |
| 603 | status = "disabled"; | |
| 604 | }; | |
| 605 | ||
| 606 | hscif0: serial@e62c0000 { | |
| 59d2b517 | 607 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
| 597af20f | 608 | reg = <0 0xe62c0000 0 96>; |
| 1f4c745b | 609 | interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
610 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>; |
| 611 | clock-names = "sci_ick"; | |
| 612 | status = "disabled"; | |
| 613 | }; | |
| 614 | ||
| 615 | hscif1: serial@e62c8000 { | |
| 59d2b517 | 616 | compatible = "renesas,hscif-r8a7790", "renesas,hscif"; |
| 597af20f | 617 | reg = <0 0xe62c8000 0 96>; |
| 1f4c745b | 618 | interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>; |
| 597af20f LP |
619 | clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>; |
| 620 | clock-names = "sci_ick"; | |
| 621 | status = "disabled"; | |
| 622 | }; | |
| 623 | ||
| d8913c67 SS |
624 | ether: ethernet@ee700000 { |
| 625 | compatible = "renesas,ether-r8a7790"; | |
| 626 | reg = <0 0xee700000 0 0x400>; | |
| 627 | interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>; | |
| 628 | clocks = <&mstp8_clks R8A7790_CLK_ETHER>; | |
| 629 | phy-mode = "rmii"; | |
| 630 | #address-cells = <1>; | |
| 631 | #size-cells = <0>; | |
| 632 | status = "disabled"; | |
| 633 | }; | |
| 634 | ||
| cde630f7 VB |
635 | sata0: sata@ee300000 { |
| 636 | compatible = "renesas,sata-r8a7790"; | |
| 637 | reg = <0 0xee300000 0 0x2000>; | |
| cde630f7 VB |
638 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; |
| 639 | clocks = <&mstp8_clks R8A7790_CLK_SATA0>; | |
| 640 | status = "disabled"; | |
| 641 | }; | |
| 642 | ||
| 643 | sata1: sata@ee500000 { | |
| 644 | compatible = "renesas,sata-r8a7790"; | |
| 645 | reg = <0 0xee500000 0 0x2000>; | |
| cde630f7 VB |
646 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; |
| 647 | clocks = <&mstp8_clks R8A7790_CLK_SATA1>; | |
| 648 | status = "disabled"; | |
| 649 | }; | |
| 650 | ||
| ae0a555b YS |
651 | hsusb: usb@e6590000 { |
| 652 | compatible = "renesas,usbhs-r8a7790"; | |
| 653 | reg = <0 0xe6590000 0 0x100>; | |
| 654 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
| 655 | clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; | |
| 656 | renesas,buswait = <4>; | |
| 657 | phys = <&usb0 1>; | |
| 658 | phy-names = "usb"; | |
| 659 | status = "disabled"; | |
| 660 | }; | |
| 661 | ||
| e089f657 SS |
662 | usbphy: usb-phy@e6590100 { |
| 663 | compatible = "renesas,usb-phy-r8a7790"; | |
| 664 | reg = <0 0xe6590100 0 0x100>; | |
| 665 | #address-cells = <1>; | |
| 666 | #size-cells = <0>; | |
| 667 | clocks = <&mstp7_clks R8A7790_CLK_HSUSB>; | |
| 668 | clock-names = "usbhs"; | |
| 669 | status = "disabled"; | |
| 670 | ||
| 671 | usb0: usb-channel@0 { | |
| 672 | reg = <0>; | |
| 673 | #phy-cells = <1>; | |
| 674 | }; | |
| 675 | usb2: usb-channel@2 { | |
| 676 | reg = <2>; | |
| 677 | #phy-cells = <1>; | |
| 678 | }; | |
| 679 | }; | |
| 680 | ||
| 9f685bfc BD |
681 | vin0: video@e6ef0000 { |
| 682 | compatible = "renesas,vin-r8a7790"; | |
| 683 | clocks = <&mstp8_clks R8A7790_CLK_VIN0>; | |
| 684 | reg = <0 0xe6ef0000 0 0x1000>; | |
| 685 | interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>; | |
| 686 | status = "disabled"; | |
| 687 | }; | |
| 688 | ||
| 689 | vin1: video@e6ef1000 { | |
| 690 | compatible = "renesas,vin-r8a7790"; | |
| 691 | clocks = <&mstp8_clks R8A7790_CLK_VIN1>; | |
| 692 | reg = <0 0xe6ef1000 0 0x1000>; | |
| 693 | interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>; | |
| 694 | status = "disabled"; | |
| 695 | }; | |
| 696 | ||
| 697 | vin2: video@e6ef2000 { | |
| 698 | compatible = "renesas,vin-r8a7790"; | |
| 699 | clocks = <&mstp8_clks R8A7790_CLK_VIN2>; | |
| 700 | reg = <0 0xe6ef2000 0 0x1000>; | |
| 701 | interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>; | |
| 702 | status = "disabled"; | |
| 703 | }; | |
| 704 | ||
| 705 | vin3: video@e6ef3000 { | |
| 706 | compatible = "renesas,vin-r8a7790"; | |
| 707 | clocks = <&mstp8_clks R8A7790_CLK_VIN3>; | |
| 708 | reg = <0 0xe6ef3000 0 0x1000>; | |
| 709 | interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>; | |
| 710 | status = "disabled"; | |
| 711 | }; | |
| 712 | ||
| 3ac6a83c LP |
713 | vsp1@fe920000 { |
| 714 | compatible = "renesas,vsp1"; | |
| 715 | reg = <0 0xfe920000 0 0x8000>; | |
| 716 | interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>; | |
| 717 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>; | |
| 718 | ||
| 719 | renesas,has-sru; | |
| 720 | renesas,#rpf = <5>; | |
| 721 | renesas,#uds = <1>; | |
| 722 | renesas,#wpf = <4>; | |
| 723 | }; | |
| 724 | ||
| 725 | vsp1@fe928000 { | |
| 726 | compatible = "renesas,vsp1"; | |
| 727 | reg = <0 0xfe928000 0 0x8000>; | |
| 728 | interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>; | |
| 729 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>; | |
| 730 | ||
| 731 | renesas,has-lut; | |
| 732 | renesas,has-sru; | |
| 733 | renesas,#rpf = <5>; | |
| 734 | renesas,#uds = <3>; | |
| 735 | renesas,#wpf = <4>; | |
| 736 | }; | |
| 737 | ||
| 738 | vsp1@fe930000 { | |
| 739 | compatible = "renesas,vsp1"; | |
| 740 | reg = <0 0xfe930000 0 0x8000>; | |
| 741 | interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>; | |
| 742 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>; | |
| 743 | ||
| 744 | renesas,has-lif; | |
| 745 | renesas,has-lut; | |
| 746 | renesas,#rpf = <4>; | |
| 747 | renesas,#uds = <1>; | |
| 748 | renesas,#wpf = <4>; | |
| 749 | }; | |
| 750 | ||
| 751 | vsp1@fe938000 { | |
| 752 | compatible = "renesas,vsp1"; | |
| 753 | reg = <0 0xfe938000 0 0x8000>; | |
| 754 | interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>; | |
| 755 | clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>; | |
| 756 | ||
| 757 | renesas,has-lif; | |
| 758 | renesas,has-lut; | |
| 759 | renesas,#rpf = <4>; | |
| 760 | renesas,#uds = <1>; | |
| 761 | renesas,#wpf = <4>; | |
| 762 | }; | |
| 763 | ||
| 764 | du: display@feb00000 { | |
| 765 | compatible = "renesas,du-r8a7790"; | |
| 766 | reg = <0 0xfeb00000 0 0x70000>, | |
| 767 | <0 0xfeb90000 0 0x1c>, | |
| 768 | <0 0xfeb94000 0 0x1c>; | |
| 769 | reg-names = "du", "lvds.0", "lvds.1"; | |
| 770 | interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>, | |
| 771 | <0 268 IRQ_TYPE_LEVEL_HIGH>, | |
| 772 | <0 269 IRQ_TYPE_LEVEL_HIGH>; | |
| 773 | clocks = <&mstp7_clks R8A7790_CLK_DU0>, | |
| 774 | <&mstp7_clks R8A7790_CLK_DU1>, | |
| 775 | <&mstp7_clks R8A7790_CLK_DU2>, | |
| 776 | <&mstp7_clks R8A7790_CLK_LVDS0>, | |
| 777 | <&mstp7_clks R8A7790_CLK_LVDS1>; | |
| 778 | clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1"; | |
| 779 | status = "disabled"; | |
| 780 | ||
| 781 | ports { | |
| 782 | #address-cells = <1>; | |
| 783 | #size-cells = <0>; | |
| 784 | ||
| 785 | port@0 { | |
| 786 | reg = <0>; | |
| 787 | du_out_rgb: endpoint { | |
| 788 | }; | |
| 789 | }; | |
| 790 | port@1 { | |
| 791 | reg = <1>; | |
| 792 | du_out_lvds0: endpoint { | |
| 793 | }; | |
| 794 | }; | |
| 795 | port@2 { | |
| 796 | reg = <2>; | |
| 797 | du_out_lvds1: endpoint { | |
| 798 | }; | |
| 799 | }; | |
| 800 | }; | |
| 801 | }; | |
| 802 | ||
| 6a7742b4 SS |
803 | can0: can@e6e80000 { |
| 804 | compatible = "renesas,can-r8a7790"; | |
| 805 | reg = <0 0xe6e80000 0 0x1000>; | |
| 806 | interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>; | |
| 807 | clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, | |
| 808 | <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; | |
| 809 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 810 | status = "disabled"; | |
| 811 | }; | |
| 812 | ||
| 813 | can1: can@e6e88000 { | |
| 814 | compatible = "renesas,can-r8a7790"; | |
| 815 | reg = <0 0xe6e88000 0 0x1000>; | |
| 816 | interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>; | |
| 817 | clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, | |
| 818 | <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>; | |
| 819 | clock-names = "clkp1", "clkp2", "can_clk"; | |
| 820 | status = "disabled"; | |
| 821 | }; | |
| 822 | ||
| 22a1f595 LP |
823 | clocks { |
| 824 | #address-cells = <2>; | |
| 825 | #size-cells = <2>; | |
| 826 | ranges; | |
| 827 | ||
| 828 | /* External root clock */ | |
| 829 | extal_clk: extal_clk { | |
| 830 | compatible = "fixed-clock"; | |
| 831 | #clock-cells = <0>; | |
| 832 | /* This value must be overriden by the board. */ | |
| 833 | clock-frequency = <0>; | |
| 834 | clock-output-names = "extal"; | |
| 835 | }; | |
| 836 | ||
| 51d17918 PE |
837 | /* External PCIe clock - can be overridden by the board */ |
| 838 | pcie_bus_clk: pcie_bus_clk { | |
| 839 | compatible = "fixed-clock"; | |
| 840 | #clock-cells = <0>; | |
| 841 | clock-frequency = <100000000>; | |
| 842 | clock-output-names = "pcie_bus"; | |
| 843 | status = "disabled"; | |
| 844 | }; | |
| 845 | ||
| c7c2ec3a KM |
846 | /* |
| 847 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
| 848 | * default. Boards that provide audio clocks should override them. | |
| 849 | */ | |
| 850 | audio_clk_a: audio_clk_a { | |
| 851 | compatible = "fixed-clock"; | |
| 852 | #clock-cells = <0>; | |
| 853 | clock-frequency = <0>; | |
| 854 | clock-output-names = "audio_clk_a"; | |
| 855 | }; | |
| 856 | audio_clk_b: audio_clk_b { | |
| 857 | compatible = "fixed-clock"; | |
| 858 | #clock-cells = <0>; | |
| 859 | clock-frequency = <0>; | |
| 860 | clock-output-names = "audio_clk_b"; | |
| 861 | }; | |
| 862 | audio_clk_c: audio_clk_c { | |
| 863 | compatible = "fixed-clock"; | |
| 864 | #clock-cells = <0>; | |
| 865 | clock-frequency = <0>; | |
| 866 | clock-output-names = "audio_clk_c"; | |
| 867 | }; | |
| 868 | ||
| 41650f40 SS |
869 | /* External USB clock - can be overridden by the board */ |
| 870 | usb_extal_clk: usb_extal_clk { | |
| 871 | compatible = "fixed-clock"; | |
| 872 | #clock-cells = <0>; | |
| 873 | clock-frequency = <48000000>; | |
| 874 | clock-output-names = "usb_extal"; | |
| 875 | }; | |
| 876 | ||
| 877 | /* External CAN clock */ | |
| 878 | can_clk: can_clk { | |
| 879 | compatible = "fixed-clock"; | |
| 880 | #clock-cells = <0>; | |
| 881 | /* This value must be overridden by the board. */ | |
| 882 | clock-frequency = <0>; | |
| 883 | clock-output-names = "can_clk"; | |
| 884 | status = "disabled"; | |
| 885 | }; | |
| 886 | ||
| 22a1f595 LP |
887 | /* Special CPG clocks */ |
| 888 | cpg_clocks: cpg_clocks@e6150000 { | |
| 889 | compatible = "renesas,r8a7790-cpg-clocks", | |
| 890 | "renesas,rcar-gen2-cpg-clocks"; | |
| 891 | reg = <0 0xe6150000 0 0x1000>; | |
| 41650f40 | 892 | clocks = <&extal_clk &usb_extal_clk>; |
| 22a1f595 LP |
893 | #clock-cells = <1>; |
| 894 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
| 895 | "lb", "qspi", "sdh", "sd0", "sd1", | |
| 3453ca9e | 896 | "z", "rcan", "adsp"; |
| 22a1f595 LP |
897 | }; |
| 898 | ||
| 899 | /* Variable factor clocks */ | |
| 900 | sd2_clk: sd2_clk@e6150078 { | |
| 901 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 902 | reg = <0 0xe6150078 0 4>; | |
| 903 | clocks = <&pll1_div2_clk>; | |
| 904 | #clock-cells = <0>; | |
| 905 | clock-output-names = "sd2"; | |
| 906 | }; | |
| edd7b938 | 907 | sd3_clk: sd3_clk@e615026c { |
| 22a1f595 | 908 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; |
| edd7b938 | 909 | reg = <0 0xe615026c 0 4>; |
| 22a1f595 LP |
910 | clocks = <&pll1_div2_clk>; |
| 911 | #clock-cells = <0>; | |
| 912 | clock-output-names = "sd3"; | |
| 913 | }; | |
| 914 | mmc0_clk: mmc0_clk@e6150240 { | |
| 915 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 916 | reg = <0 0xe6150240 0 4>; | |
| 917 | clocks = <&pll1_div2_clk>; | |
| 918 | #clock-cells = <0>; | |
| 919 | clock-output-names = "mmc0"; | |
| 920 | }; | |
| 921 | mmc1_clk: mmc1_clk@e6150244 { | |
| 922 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 923 | reg = <0 0xe6150244 0 4>; | |
| 924 | clocks = <&pll1_div2_clk>; | |
| 925 | #clock-cells = <0>; | |
| 926 | clock-output-names = "mmc1"; | |
| 927 | }; | |
| 928 | ssp_clk: ssp_clk@e6150248 { | |
| 929 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 930 | reg = <0 0xe6150248 0 4>; | |
| 931 | clocks = <&pll1_div2_clk>; | |
| 932 | #clock-cells = <0>; | |
| 933 | clock-output-names = "ssp"; | |
| 934 | }; | |
| 935 | ssprs_clk: ssprs_clk@e615024c { | |
| 936 | compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock"; | |
| 937 | reg = <0 0xe615024c 0 4>; | |
| 938 | clocks = <&pll1_div2_clk>; | |
| 939 | #clock-cells = <0>; | |
| 940 | clock-output-names = "ssprs"; | |
| 941 | }; | |
| 942 | ||
| 943 | /* Fixed factor clocks */ | |
| 944 | pll1_div2_clk: pll1_div2_clk { | |
| 945 | compatible = "fixed-factor-clock"; | |
| 946 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 947 | #clock-cells = <0>; | |
| 948 | clock-div = <2>; | |
| 949 | clock-mult = <1>; | |
| 950 | clock-output-names = "pll1_div2"; | |
| 951 | }; | |
| 952 | z2_clk: z2_clk { | |
| 953 | compatible = "fixed-factor-clock"; | |
| 954 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 955 | #clock-cells = <0>; | |
| 956 | clock-div = <2>; | |
| 957 | clock-mult = <1>; | |
| 958 | clock-output-names = "z2"; | |
| 959 | }; | |
| 960 | zg_clk: zg_clk { | |
| 961 | compatible = "fixed-factor-clock"; | |
| 962 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 963 | #clock-cells = <0>; | |
| 964 | clock-div = <3>; | |
| 965 | clock-mult = <1>; | |
| 966 | clock-output-names = "zg"; | |
| 967 | }; | |
| 968 | zx_clk: zx_clk { | |
| 969 | compatible = "fixed-factor-clock"; | |
| 970 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 971 | #clock-cells = <0>; | |
| 972 | clock-div = <3>; | |
| 973 | clock-mult = <1>; | |
| 974 | clock-output-names = "zx"; | |
| 975 | }; | |
| 976 | zs_clk: zs_clk { | |
| 977 | compatible = "fixed-factor-clock"; | |
| 978 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 979 | #clock-cells = <0>; | |
| 980 | clock-div = <6>; | |
| 981 | clock-mult = <1>; | |
| 982 | clock-output-names = "zs"; | |
| 983 | }; | |
| 984 | hp_clk: hp_clk { | |
| 985 | compatible = "fixed-factor-clock"; | |
| 986 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 987 | #clock-cells = <0>; | |
| 988 | clock-div = <12>; | |
| 989 | clock-mult = <1>; | |
| 990 | clock-output-names = "hp"; | |
| 991 | }; | |
| 992 | i_clk: i_clk { | |
| 993 | compatible = "fixed-factor-clock"; | |
| 994 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 995 | #clock-cells = <0>; | |
| 996 | clock-div = <2>; | |
| 997 | clock-mult = <1>; | |
| 998 | clock-output-names = "i"; | |
| 999 | }; | |
| 1000 | b_clk: b_clk { | |
| 1001 | compatible = "fixed-factor-clock"; | |
| 1002 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 1003 | #clock-cells = <0>; | |
| 1004 | clock-div = <12>; | |
| 1005 | clock-mult = <1>; | |
| 1006 | clock-output-names = "b"; | |
| 1007 | }; | |
| 1008 | p_clk: p_clk { | |
| 1009 | compatible = "fixed-factor-clock"; | |
| 1010 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 1011 | #clock-cells = <0>; | |
| 1012 | clock-div = <24>; | |
| 1013 | clock-mult = <1>; | |
| 1014 | clock-output-names = "p"; | |
| 1015 | }; | |
| 1016 | cl_clk: cl_clk { | |
| 1017 | compatible = "fixed-factor-clock"; | |
| 1018 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 1019 | #clock-cells = <0>; | |
| 1020 | clock-div = <48>; | |
| 1021 | clock-mult = <1>; | |
| 1022 | clock-output-names = "cl"; | |
| 1023 | }; | |
| 1024 | m2_clk: m2_clk { | |
| 1025 | compatible = "fixed-factor-clock"; | |
| 1026 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 1027 | #clock-cells = <0>; | |
| 1028 | clock-div = <8>; | |
| 1029 | clock-mult = <1>; | |
| 1030 | clock-output-names = "m2"; | |
| 1031 | }; | |
| 1032 | imp_clk: imp_clk { | |
| 1033 | compatible = "fixed-factor-clock"; | |
| 1034 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 1035 | #clock-cells = <0>; | |
| 1036 | clock-div = <4>; | |
| 1037 | clock-mult = <1>; | |
| 1038 | clock-output-names = "imp"; | |
| 1039 | }; | |
| 1040 | rclk_clk: rclk_clk { | |
| 1041 | compatible = "fixed-factor-clock"; | |
| 1042 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 1043 | #clock-cells = <0>; | |
| 1044 | clock-div = <(48 * 1024)>; | |
| 1045 | clock-mult = <1>; | |
| 1046 | clock-output-names = "rclk"; | |
| 1047 | }; | |
| 1048 | oscclk_clk: oscclk_clk { | |
| 1049 | compatible = "fixed-factor-clock"; | |
| 1050 | clocks = <&cpg_clocks R8A7790_CLK_PLL1>; | |
| 1051 | #clock-cells = <0>; | |
| 1052 | clock-div = <(12 * 1024)>; | |
| 1053 | clock-mult = <1>; | |
| 1054 | clock-output-names = "oscclk"; | |
| 1055 | }; | |
| 1056 | zb3_clk: zb3_clk { | |
| 1057 | compatible = "fixed-factor-clock"; | |
| 1058 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
| 1059 | #clock-cells = <0>; | |
| 1060 | clock-div = <4>; | |
| 1061 | clock-mult = <1>; | |
| 1062 | clock-output-names = "zb3"; | |
| 1063 | }; | |
| 1064 | zb3d2_clk: zb3d2_clk { | |
| 1065 | compatible = "fixed-factor-clock"; | |
| 1066 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
| 1067 | #clock-cells = <0>; | |
| 1068 | clock-div = <8>; | |
| 1069 | clock-mult = <1>; | |
| 1070 | clock-output-names = "zb3d2"; | |
| 1071 | }; | |
| 1072 | ddr_clk: ddr_clk { | |
| 1073 | compatible = "fixed-factor-clock"; | |
| 1074 | clocks = <&cpg_clocks R8A7790_CLK_PLL3>; | |
| 1075 | #clock-cells = <0>; | |
| 1076 | clock-div = <8>; | |
| 1077 | clock-mult = <1>; | |
| 1078 | clock-output-names = "ddr"; | |
| 1079 | }; | |
| 1080 | mp_clk: mp_clk { | |
| 1081 | compatible = "fixed-factor-clock"; | |
| 1082 | clocks = <&pll1_div2_clk>; | |
| 1083 | #clock-cells = <0>; | |
| 1084 | clock-div = <15>; | |
| 1085 | clock-mult = <1>; | |
| 1086 | clock-output-names = "mp"; | |
| 1087 | }; | |
| 1088 | cp_clk: cp_clk { | |
| 1089 | compatible = "fixed-factor-clock"; | |
| 1090 | clocks = <&extal_clk>; | |
| 1091 | #clock-cells = <0>; | |
| 1092 | clock-div = <2>; | |
| 1093 | clock-mult = <1>; | |
| 1094 | clock-output-names = "cp"; | |
| 1095 | }; | |
| 1096 | ||
| 1097 | /* Gate clocks */ | |
| 9d90951a LP |
1098 | mstp0_clks: mstp0_clks@e6150130 { |
| 1099 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1100 | reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; | |
| 1101 | clocks = <&mp_clk>; | |
| 1102 | #clock-cells = <1>; | |
| b54010af | 1103 | clock-indices = <R8A7790_CLK_MSIOF0>; |
| 9d90951a LP |
1104 | clock-output-names = "msiof0"; |
| 1105 | }; | |
| 22a1f595 LP |
1106 | mstp1_clks: mstp1_clks@e6150134 { |
| 1107 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1108 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
| 4ba8f246 YH |
1109 | clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>, |
| 1110 | <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>, | |
| 1111 | <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, | |
| 1112 | <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; | |
| 22a1f595 | 1113 | #clock-cells = <1>; |
| b54010af | 1114 | clock-indices = < |
| 4ba8f246 YH |
1115 | R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1 |
| 1116 | R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1 | |
| 1117 | R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC | |
| 1118 | R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0 | |
| 1119 | R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0 | |
| 1120 | R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0 | |
| 1121 | R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S | |
| 22a1f595 LP |
1122 | >; |
| 1123 | clock-output-names = | |
| 4ba8f246 YH |
1124 | "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1", |
| 1125 | "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1", | |
| 1126 | "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0", | |
| 2284ff5f | 1127 | "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy"; |
| 22a1f595 LP |
1128 | }; |
| 1129 | mstp2_clks: mstp2_clks@e6150138 { | |
| 1130 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1131 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
| 1132 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, | |
| c819acda LP |
1133 | <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>, |
| 1134 | <&zs_clk>; | |
| 22a1f595 | 1135 | #clock-cells = <1>; |
| b54010af | 1136 | clock-indices = < |
| 22a1f595 | 1137 | R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0 |
| 9d90951a LP |
1138 | R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1 |
| 1139 | R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2 | |
| c819acda | 1140 | R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0 |
| 22a1f595 LP |
1141 | >; |
| 1142 | clock-output-names = | |
| 9d90951a | 1143 | "scifa2", "scifa1", "scifa0", "msiof2", "scifb0", |
| c819acda LP |
1144 | "scifb1", "msiof1", "msiof3", "scifb2", |
| 1145 | "sys-dmac1", "sys-dmac0"; | |
| 22a1f595 LP |
1146 | }; |
| 1147 | mstp3_clks: mstp3_clks@e615013c { | |
| 1148 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1149 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
| 17465149 WS |
1150 | clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, |
| 1151 | <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, | |
| b02ce79f YS |
1152 | <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, |
| 1153 | <&hp_clk>, <&hp_clk>; | |
| 22a1f595 | 1154 | #clock-cells = <1>; |
| b54010af | 1155 | clock-indices = < |
| 17465149 WS |
1156 | R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 |
| 1157 | R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 | |
| ecafea8c | 1158 | R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 |
| b02ce79f | 1159 | R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 |
| 22a1f595 LP |
1160 | >; |
| 1161 | clock-output-names = | |
| 17465149 WS |
1162 | "iic2", "tpu0", "mmcif1", "sdhi3", |
| 1163 | "sdhi2", "sdhi1", "sdhi0", "mmcif0", | |
| b02ce79f YS |
1164 | "iic0", "pciec", "iic1", "ssusb", "cmt1", |
| 1165 | "usbdmac0", "usbdmac1"; | |
| 22a1f595 LP |
1166 | }; |
| 1167 | mstp5_clks: mstp5_clks@e6150144 { | |
| 1168 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1169 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
| 3453ca9e SS |
1170 | clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>, |
| 1171 | <&extal_clk>, <&p_clk>; | |
| 22a1f595 | 1172 | #clock-cells = <1>; |
| b54010af BD |
1173 | clock-indices = < |
| 1174 | R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 | |
| 3453ca9e SS |
1175 | R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL |
| 1176 | R8A7790_CLK_PWM | |
| b54010af | 1177 | >; |
| 3453ca9e SS |
1178 | clock-output-names = "audmac0", "audmac1", "adsp_mod", |
| 1179 | "thermal", "pwm"; | |
| 22a1f595 LP |
1180 | }; |
| 1181 | mstp7_clks: mstp7_clks@e615014c { | |
| 1182 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1183 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
| 1184 | clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, | |
| 1185 | <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, | |
| 1186 | <&zx_clk>; | |
| 1187 | #clock-cells = <1>; | |
| b54010af | 1188 | clock-indices = < |
| 22a1f595 LP |
1189 | R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1 |
| 1190 | R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0 | |
| 1191 | R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0 | |
| 1192 | R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0 | |
| 1193 | >; | |
| 1194 | clock-output-names = | |
| 1195 | "ehci", "hsusb", "hscif1", "hscif0", "scif1", | |
| 1196 | "scif0", "du2", "du1", "du0", "lvds1", "lvds0"; | |
| 1197 | }; | |
| 1198 | mstp8_clks: mstp8_clks@e6150990 { | |
| 1199 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1200 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
| f6b5dd40 AG |
1201 | clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, |
| 1202 | <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>; | |
| 22a1f595 | 1203 | #clock-cells = <1>; |
| b54010af | 1204 | clock-indices = < |
| f6b5dd40 AG |
1205 | R8A7790_CLK_MLB R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 |
| 1206 | R8A7790_CLK_VIN1 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER | |
| 1207 | R8A7790_CLK_SATA1 R8A7790_CLK_SATA0 | |
| 3f2beaa9 | 1208 | >; |
| bccccc3d | 1209 | clock-output-names = |
| f6b5dd40 AG |
1210 | "mlb", "vin3", "vin2", "vin1", "vin0", "ether", |
| 1211 | "sata1", "sata0"; | |
| 22a1f595 LP |
1212 | }; |
| 1213 | mstp9_clks: mstp9_clks@e6150994 { | |
| 1214 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1215 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
| 81f6883f GU |
1216 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| 1217 | <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
| 1218 | <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>, | |
| 3672b059 | 1219 | <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; |
| 22a1f595 | 1220 | #clock-cells = <1>; |
| b54010af | 1221 | clock-indices = < |
| 81f6883f GU |
1222 | R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3 |
| 1223 | R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0 | |
| 17465149 WS |
1224 | R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS |
| 1225 | R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0 | |
| 22a1f595 | 1226 | >; |
| 91b56ca1 | 1227 | clock-output-names = |
| 81f6883f | 1228 | "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0", |
| 17465149 WS |
1229 | "rcan1", "rcan0", "qspi_mod", "iic3", |
| 1230 | "i2c3", "i2c2", "i2c1", "i2c0"; | |
| 22a1f595 | 1231 | }; |
| bcde3722 KM |
1232 | mstp10_clks: mstp10_clks@e6150998 { |
| 1233 | compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 1234 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | |
| 1235 | clocks = <&p_clk>, | |
| 1236 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
| 1237 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
| 1238 | <&p_clk>, | |
| 1239 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
| 1240 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
| 1241 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
| 1242 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
| 1243 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>, | |
| 1244 | <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>; | |
| 1245 | ||
| 1246 | #clock-cells = <1>; | |
| 1247 | clock-indices = < | |
| 1248 | R8A7790_CLK_SSI_ALL | |
| 1249 | R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5 | |
| 1250 | R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0 | |
| 1251 | R8A7790_CLK_SCU_ALL | |
| 1252 | R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0 | |
| 1253 | R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5 | |
| 1254 | R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0 | |
| 1255 | >; | |
| 1256 | clock-output-names = | |
| 1257 | "ssi-all", | |
| 1258 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | |
| 1259 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | |
| 1260 | "scu-all", | |
| 1261 | "scu-dvc1", "scu-dvc0", | |
| 1262 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", | |
| 1263 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | |
| 1264 | }; | |
| 22a1f595 | 1265 | }; |
| 7053e134 | 1266 | |
| fad6d45c | 1267 | qspi: spi@e6b10000 { |
| 7053e134 GU |
1268 | compatible = "renesas,qspi-r8a7790", "renesas,qspi"; |
| 1269 | reg = <0 0xe6b10000 0 0x2c>; | |
| 7053e134 GU |
1270 | interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>; |
| 1271 | clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>; | |
| 37cf3d61 GU |
1272 | dmas = <&dmac0 0x17>, <&dmac0 0x18>; |
| 1273 | dma-names = "tx", "rx"; | |
| 7053e134 GU |
1274 | num-cs = <1>; |
| 1275 | #address-cells = <1>; | |
| 1276 | #size-cells = <0>; | |
| 1277 | status = "disabled"; | |
| 1278 | }; | |
| ae8a6146 GU |
1279 | |
| 1280 | msiof0: spi@e6e20000 { | |
| 1281 | compatible = "renesas,msiof-r8a7790"; | |
| fbff6688 | 1282 | reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>; |
| ae8a6146 GU |
1283 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
| 1284 | clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>; | |
| fbff6688 GU |
1285 | dmas = <&dmac0 0x51>, <&dmac0 0x52>; |
| 1286 | dma-names = "tx", "rx"; | |
| ae8a6146 GU |
1287 | #address-cells = <1>; |
| 1288 | #size-cells = <0>; | |
| 1289 | status = "disabled"; | |
| 1290 | }; | |
| 1291 | ||
| 1292 | msiof1: spi@e6e10000 { | |
| 1293 | compatible = "renesas,msiof-r8a7790"; | |
| fbff6688 | 1294 | reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>; |
| ae8a6146 GU |
1295 | interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>; |
| 1296 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>; | |
| fbff6688 GU |
1297 | dmas = <&dmac0 0x55>, <&dmac0 0x56>; |
| 1298 | dma-names = "tx", "rx"; | |
| ae8a6146 GU |
1299 | #address-cells = <1>; |
| 1300 | #size-cells = <0>; | |
| 1301 | status = "disabled"; | |
| 1302 | }; | |
| 1303 | ||
| 1304 | msiof2: spi@e6e00000 { | |
| 1305 | compatible = "renesas,msiof-r8a7790"; | |
| fbff6688 | 1306 | reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>; |
| ae8a6146 GU |
1307 | interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>; |
| 1308 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>; | |
| fbff6688 GU |
1309 | dmas = <&dmac0 0x41>, <&dmac0 0x42>; |
| 1310 | dma-names = "tx", "rx"; | |
| ae8a6146 GU |
1311 | #address-cells = <1>; |
| 1312 | #size-cells = <0>; | |
| 1313 | status = "disabled"; | |
| 1314 | }; | |
| 1315 | ||
| 1316 | msiof3: spi@e6c90000 { | |
| 1317 | compatible = "renesas,msiof-r8a7790"; | |
| fbff6688 | 1318 | reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>; |
| ae8a6146 GU |
1319 | interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>; |
| 1320 | clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>; | |
| fbff6688 GU |
1321 | dmas = <&dmac0 0x45>, <&dmac0 0x46>; |
| 1322 | dma-names = "tx", "rx"; | |
| ae8a6146 GU |
1323 | #address-cells = <1>; |
| 1324 | #size-cells = <0>; | |
| 1325 | status = "disabled"; | |
| 1326 | }; | |
| 7df2fd57 | 1327 | |
| 157fcd8a YS |
1328 | xhci: usb@ee000000 { |
| 1329 | compatible = "renesas,xhci-r8a7790"; | |
| 1330 | reg = <0 0xee000000 0 0xc00>; | |
| 1331 | interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>; | |
| 1332 | clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; | |
| 1333 | phys = <&usb2 1>; | |
| 1334 | phy-names = "usb"; | |
| 1335 | status = "disabled"; | |
| 1336 | }; | |
| 1337 | ||
| ff4f3eb8 BD |
1338 | pci0: pci@ee090000 { |
| 1339 | compatible = "renesas,pci-r8a7790"; | |
| 1340 | device_type = "pci"; | |
| 1341 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; | |
| 1342 | reg = <0 0xee090000 0 0xc00>, | |
| 1343 | <0 0xee080000 0 0x1100>; | |
| 1344 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 1345 | status = "disabled"; | |
| 1346 | ||
| 1347 | bus-range = <0 0>; | |
| 1348 | #address-cells = <3>; | |
| 1349 | #size-cells = <2>; | |
| 1350 | #interrupt-cells = <1>; | |
| 1351 | ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; | |
| 1352 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
| 1353 | interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH | |
| 517ec80a GU |
1354 | 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH |
| 1355 | 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>; | |
| 538c40e5 SS |
1356 | |
| 1357 | usb@0,1 { | |
| 1358 | reg = <0x800 0 0 0 0>; | |
| 1359 | device_type = "pci"; | |
| 1360 | phys = <&usb0 0>; | |
| 1361 | phy-names = "usb"; | |
| 1362 | }; | |
| 1363 | ||
| 1364 | usb@0,2 { | |
| 1365 | reg = <0x1000 0 0 0 0>; | |
| 1366 | device_type = "pci"; | |
| 1367 | phys = <&usb0 0>; | |
| 1368 | phy-names = "usb"; | |
| 1369 | }; | |
| ff4f3eb8 BD |
1370 | }; |
| 1371 | ||
| 1372 | pci1: pci@ee0b0000 { | |
| 1373 | compatible = "renesas,pci-r8a7790"; | |
| 1374 | device_type = "pci"; | |
| 1375 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; | |
| 1376 | reg = <0 0xee0b0000 0 0xc00>, | |
| 1377 | <0 0xee0a0000 0 0x1100>; | |
| 1378 | interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; | |
| 1379 | status = "disabled"; | |
| 1380 | ||
| 1381 | bus-range = <1 1>; | |
| 1382 | #address-cells = <3>; | |
| 1383 | #size-cells = <2>; | |
| 1384 | #interrupt-cells = <1>; | |
| 1385 | ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>; | |
| 1386 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
| 1387 | interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH | |
| 517ec80a GU |
1388 | 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH |
| 1389 | 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>; | |
| ff4f3eb8 BD |
1390 | }; |
| 1391 | ||
| 1392 | pci2: pci@ee0d0000 { | |
| 1393 | compatible = "renesas,pci-r8a7790"; | |
| 1394 | device_type = "pci"; | |
| 1395 | clocks = <&mstp7_clks R8A7790_CLK_EHCI>; | |
| 1396 | reg = <0 0xee0d0000 0 0xc00>, | |
| 1397 | <0 0xee0c0000 0 0x1100>; | |
| 1398 | interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 1399 | status = "disabled"; | |
| 1400 | ||
| 1401 | bus-range = <2 2>; | |
| 1402 | #address-cells = <3>; | |
| 1403 | #size-cells = <2>; | |
| 1404 | #interrupt-cells = <1>; | |
| 1405 | ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; | |
| 1406 | interrupt-map-mask = <0xff00 0 0 0x7>; | |
| 1407 | interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH | |
| 517ec80a GU |
1408 | 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH |
| 1409 | 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; | |
| 538c40e5 SS |
1410 | |
| 1411 | usb@0,1 { | |
| 1412 | reg = <0x800 0 0 0 0>; | |
| 1413 | device_type = "pci"; | |
| 1414 | phys = <&usb2 0>; | |
| 1415 | phy-names = "usb"; | |
| 1416 | }; | |
| 1417 | ||
| 1418 | usb@0,2 { | |
| 1419 | reg = <0x1000 0 0 0 0>; | |
| 1420 | device_type = "pci"; | |
| 1421 | phys = <&usb2 0>; | |
| 1422 | phy-names = "usb"; | |
| 1423 | }; | |
| ff4f3eb8 BD |
1424 | }; |
| 1425 | ||
| 745329d2 PE |
1426 | pciec: pcie@fe000000 { |
| 1427 | compatible = "renesas,pcie-r8a7790"; | |
| 1428 | reg = <0 0xfe000000 0 0x80000>; | |
| 1429 | #address-cells = <3>; | |
| 1430 | #size-cells = <2>; | |
| 1431 | bus-range = <0x00 0xff>; | |
| 1432 | device_type = "pci"; | |
| 1433 | ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000 | |
| 1434 | 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000 | |
| 1435 | 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000 | |
| 1436 | 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; | |
| 1437 | /* Map all possible DDR as inbound ranges */ | |
| 1438 | dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000 | |
| 1439 | 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>; | |
| 1440 | interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>, | |
| 1441 | <0 117 IRQ_TYPE_LEVEL_HIGH>, | |
| 1442 | <0 118 IRQ_TYPE_LEVEL_HIGH>; | |
| 1443 | #interrupt-cells = <1>; | |
| 1444 | interrupt-map-mask = <0 0 0 0>; | |
| 1445 | interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>; | |
| 1446 | clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>; | |
| 1447 | clock-names = "pcie", "pcie_bus"; | |
| 1448 | status = "disabled"; | |
| 1449 | }; | |
| 1450 | ||
| 83b4fb6d | 1451 | rcar_sound: rcar_sound@ec500000 { |
| ad63241c KM |
1452 | /* |
| 1453 | * #sound-dai-cells is required | |
| 1454 | * | |
| 1455 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
| 1456 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
| 1457 | */ | |
| 31078ecd | 1458 | compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2"; |
| 7df2fd57 KM |
1459 | reg = <0 0xec500000 0 0x1000>, /* SCU */ |
| 1460 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
| 1461 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
| 1462 | <0 0xec541000 0 0x1280>; /* SSI */ | |
| 1463 | clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>, | |
| 1464 | <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>, | |
| 1465 | <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>, | |
| 1466 | <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>, | |
| 1467 | <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>, | |
| 1468 | <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>, | |
| 1469 | <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>, | |
| 1470 | <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>, | |
| 1471 | <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>, | |
| 1472 | <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>, | |
| 1473 | <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>, | |
| 334d69a2 | 1474 | <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>, |
| 7df2fd57 KM |
1475 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
| 1476 | clock-names = "ssi-all", | |
| 1477 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", | |
| 1478 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", | |
| 1479 | "src.9", "src.8", "src.7", "src.6", "src.5", | |
| 1480 | "src.4", "src.3", "src.2", "src.1", "src.0", | |
| 334d69a2 | 1481 | "dvc.0", "dvc.1", |
| 7df2fd57 KM |
1482 | "clk_a", "clk_b", "clk_c", "clk_i"; |
| 1483 | ||
| 1484 | status = "disabled"; | |
| 1485 | ||
| 334d69a2 KM |
1486 | rcar_sound,dvc { |
| 1487 | dvc0: dvc@0 { }; | |
| 1488 | dvc1: dvc@1 { }; | |
| 1489 | }; | |
| 1490 | ||
| 7df2fd57 | 1491 | rcar_sound,src { |
| d86a3110 KM |
1492 | src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; }; |
| 1493 | src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1494 | src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1495 | src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1496 | src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1497 | src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1498 | src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1499 | src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1500 | src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1501 | src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 7df2fd57 KM |
1502 | }; |
| 1503 | ||
| 1504 | rcar_sound,ssi { | |
| 1505 | ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1506 | ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1507 | ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1508 | ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1509 | ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1510 | ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1511 | ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1512 | ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1513 | ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1514 | ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; | |
| 1515 | }; | |
| 1516 | }; | |
| 70496727 LP |
1517 | |
| 1518 | ipmmu_sy0: mmu@e6280000 { | |
| 1519 | compatible = "renesas,ipmmu-vmsa"; | |
| 1520 | reg = <0 0xe6280000 0 0x1000>; | |
| 1521 | interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>, | |
| 1522 | <0 224 IRQ_TYPE_LEVEL_HIGH>; | |
| 1523 | #iommu-cells = <1>; | |
| 1524 | status = "disabled"; | |
| 1525 | }; | |
| 1526 | ||
| 1527 | ipmmu_sy1: mmu@e6290000 { | |
| 1528 | compatible = "renesas,ipmmu-vmsa"; | |
| 1529 | reg = <0 0xe6290000 0 0x1000>; | |
| 1530 | interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>; | |
| 1531 | #iommu-cells = <1>; | |
| 1532 | status = "disabled"; | |
| 1533 | }; | |
| 1534 | ||
| 1535 | ipmmu_ds: mmu@e6740000 { | |
| 1536 | compatible = "renesas,ipmmu-vmsa"; | |
| 1537 | reg = <0 0xe6740000 0 0x1000>; | |
| 1538 | interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>, | |
| 1539 | <0 199 IRQ_TYPE_LEVEL_HIGH>; | |
| 1540 | #iommu-cells = <1>; | |
| 1541 | status = "disabled"; | |
| 1542 | }; | |
| 1543 | ||
| 1544 | ipmmu_mp: mmu@ec680000 { | |
| 1545 | compatible = "renesas,ipmmu-vmsa"; | |
| 1546 | reg = <0 0xec680000 0 0x1000>; | |
| 1547 | interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>; | |
| 1548 | #iommu-cells = <1>; | |
| 1549 | status = "disabled"; | |
| 1550 | }; | |
| 1551 | ||
| 1552 | ipmmu_mx: mmu@fe951000 { | |
| 1553 | compatible = "renesas,ipmmu-vmsa"; | |
| 1554 | reg = <0 0xfe951000 0 0x1000>; | |
| 1555 | interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, | |
| 1556 | <0 221 IRQ_TYPE_LEVEL_HIGH>; | |
| 1557 | #iommu-cells = <1>; | |
| 1558 | status = "disabled"; | |
| 1559 | }; | |
| 1560 | ||
| 1561 | ipmmu_rt: mmu@ffc80000 { | |
| 1562 | compatible = "renesas,ipmmu-vmsa"; | |
| 1563 | reg = <0 0xffc80000 0 0x1000>; | |
| 1564 | interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>; | |
| 1565 | #iommu-cells = <1>; | |
| 1566 | status = "disabled"; | |
| 1567 | }; | |
| 0468b2d6 | 1568 | }; |