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ARM: shmobile: r8a7791: add USB3.0 device node
[deliverable/linux.git] / arch / arm / boot / dts / r8a7790.dtsi
CommitLineData
0468b2d6
MD		 1/*
2 * Device Tree Source for the r8a7790 SoC
3 *
d8913c67
SS		 4 * Copyright (C) 2013-2014 Renesas Solutions Corp.
5 * Copyright (C) 2014 Cogent Embedded Inc.
0468b2d6
MD		 6 *
7 * This file is licensed under the terms of the GNU General Public License
8 * version 2. This program is licensed "as is" without any warranty of any
9 * kind, whether express or implied.
10 */
11
22a1f595 12#include <dt-bindings/clock/r8a7790-clock.h>
5f75e73c
LP		 13#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h>
15
0468b2d6
MD		 16/ {
17 compatible = "renesas,r8a7790";
18 interrupt-parent = <&gic>;
8585deb1
TY		 19 #address-cells = <2>;
20 #size-cells = <2>;
0468b2d6 21
6b1d7c68
WS		 22 aliases {
23 i2c0 = &i2c0;
24 i2c1 = &i2c1;
25 i2c2 = &i2c2;
26 i2c3 = &i2c3;
05f39916
WS		 27 i2c4 = &iic0;
28 i2c5 = &iic1;
29 i2c6 = &iic2;
30 i2c7 = &iic3;
fad6d45c 31 spi0 = &qspi;
ae8a6146
GU		 32 spi1 = &msiof0;
33 spi2 = &msiof1;
34 spi3 = &msiof2;
35 spi4 = &msiof3;
9f685bfc
BD		 36 vin0 = &vin0;
37 vin1 = &vin1;
38 vin2 = &vin2;
39 vin3 = &vin3;
6b1d7c68
WS		 40 };
41
0468b2d6
MD		 42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
50 clock-frequency = <1300000000>;
b989e138
BC		 51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7790_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1400000 1000000>,
57 <1225000 1000000>,
58 <1050000 1000000>,
59 < 875000 1000000>,
60 < 700000 1000000>,
61 < 350000 1000000>;
0468b2d6 62 };
c1f95979
MD		 63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
68 clock-frequency = <1300000000>;
69 };
70
71 cpu2: cpu@2 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a15";
74 reg = <2>;
75 clock-frequency = <1300000000>;
76 };
77
78 cpu3: cpu@3 {
79 device_type = "cpu";
80 compatible = "arm,cortex-a15";
81 reg = <3>;
82 clock-frequency = <1300000000>;
83 };
2007e74c
MD		 84
85 cpu4: cpu@4 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a7";
88 reg = <0x100>;
89 clock-frequency = <780000000>;
90 };
91
92 cpu5: cpu@5 {
93 device_type = "cpu";
94 compatible = "arm,cortex-a7";
95 reg = <0x101>;
96 clock-frequency = <780000000>;
97 };
98
99 cpu6: cpu@6 {
100 device_type = "cpu";
101 compatible = "arm,cortex-a7";
102 reg = <0x102>;
103 clock-frequency = <780000000>;
104 };
105
106 cpu7: cpu@7 {
107 device_type = "cpu";
108 compatible = "arm,cortex-a7";
109 reg = <0x103>;
110 clock-frequency = <780000000>;
111 };
0468b2d6
MD		 112 };
113
114 gic: interrupt-controller@f1001000 {
115 compatible = "arm,cortex-a15-gic";
116 #interrupt-cells = <3>;
117 #address-cells = <0>;
118 interrupt-controller;
8585deb1
TY		 119 reg = <0 0xf1001000 0 0x1000>,
120 <0 0xf1002000 0 0x1000>,
121 <0 0xf1004000 0 0x2000>,
122 <0 0xf1006000 0 0x2000>;
5f75e73c 123 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
0468b2d6
MD		 124 };
125
23de2278 126 gpio0: gpio@e6050000 {
f98e10c8 127 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 128 reg = <0 0xe6050000 0 0x50>;
5f75e73c 129 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 130 #gpio-cells = <2>;
131 gpio-controller;
132 gpio-ranges = <&pfc 0 0 32>;
133 #interrupt-cells = <2>;
134 interrupt-controller;
81f6883f 135 clocks = <&mstp9_clks R8A7790_CLK_GPIO0>;
f98e10c8
LP		 136 };
137
23de2278 138 gpio1: gpio@e6051000 {
f98e10c8 139 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 140 reg = <0 0xe6051000 0 0x50>;
5f75e73c 141 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 142 #gpio-cells = <2>;
143 gpio-controller;
144 gpio-ranges = <&pfc 0 32 32>;
145 #interrupt-cells = <2>;
146 interrupt-controller;
81f6883f 147 clocks = <&mstp9_clks R8A7790_CLK_GPIO1>;
f98e10c8
LP		 148 };
149
23de2278 150 gpio2: gpio@e6052000 {
f98e10c8 151 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 152 reg = <0 0xe6052000 0 0x50>;
5f75e73c 153 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 154 #gpio-cells = <2>;
155 gpio-controller;
156 gpio-ranges = <&pfc 0 64 32>;
157 #interrupt-cells = <2>;
158 interrupt-controller;
81f6883f 159 clocks = <&mstp9_clks R8A7790_CLK_GPIO2>;
f98e10c8
LP		 160 };
161
23de2278 162 gpio3: gpio@e6053000 {
f98e10c8 163 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 164 reg = <0 0xe6053000 0 0x50>;
5f75e73c 165 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 166 #gpio-cells = <2>;
167 gpio-controller;
168 gpio-ranges = <&pfc 0 96 32>;
169 #interrupt-cells = <2>;
170 interrupt-controller;
81f6883f 171 clocks = <&mstp9_clks R8A7790_CLK_GPIO3>;
f98e10c8
LP		 172 };
173
23de2278 174 gpio4: gpio@e6054000 {
f98e10c8 175 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 176 reg = <0 0xe6054000 0 0x50>;
5f75e73c 177 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 178 #gpio-cells = <2>;
179 gpio-controller;
180 gpio-ranges = <&pfc 0 128 32>;
181 #interrupt-cells = <2>;
182 interrupt-controller;
81f6883f 183 clocks = <&mstp9_clks R8A7790_CLK_GPIO4>;
f98e10c8
LP		 184 };
185
23de2278 186 gpio5: gpio@e6055000 {
f98e10c8 187 compatible = "renesas,gpio-r8a7790", "renesas,gpio-rcar";
23de2278 188 reg = <0 0xe6055000 0 0x50>;
5f75e73c 189 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
f98e10c8
LP		 190 #gpio-cells = <2>;
191 gpio-controller;
192 gpio-ranges = <&pfc 0 160 32>;
193 #interrupt-cells = <2>;
194 interrupt-controller;
81f6883f 195 clocks = <&mstp9_clks R8A7790_CLK_GPIO5>;
f98e10c8
LP		 196 };
197
03e2f56b
MD		 198 thermal@e61f0000 {
199 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal";
200 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
03e2f56b 201 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
d3a439db 202 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>;
03e2f56b
MD		 203 };
204
0468b2d6
MD		 205 timer {
206 compatible = "arm,armv7-timer";
5f75e73c
LP		 207 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
208 <1 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
209 <1 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
210 <1 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
0468b2d6 211 };
8f5ec0a5 212
39cf6d73 213 cmt0: timer@ffca0000 {
37757030 214 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73
LP		 215 reg = <0 0xffca0000 0 0x1004>;
216 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
217 <0 143 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp1_clks R8A7790_CLK_CMT0>;
219 clock-names = "fck";
220
221 renesas,channels-mask = <0x60>;
222
223 status = "disabled";
224 };
225
226 cmt1: timer@e6130000 {
37757030 227 compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
39cf6d73
LP		 228 reg = <0 0xe6130000 0 0x1004>;
229 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
230 <0 121 IRQ_TYPE_LEVEL_HIGH>,
231 <0 122 IRQ_TYPE_LEVEL_HIGH>,
232 <0 123 IRQ_TYPE_LEVEL_HIGH>,
233 <0 124 IRQ_TYPE_LEVEL_HIGH>,
234 <0 125 IRQ_TYPE_LEVEL_HIGH>,
235 <0 126 IRQ_TYPE_LEVEL_HIGH>,
236 <0 127 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&mstp3_clks R8A7790_CLK_CMT1>;
238 clock-names = "fck";
239
240 renesas,channels-mask = <0xff>;
241
242 status = "disabled";
243 };
244
8f5ec0a5 245 irqc0: interrupt-controller@e61c0000 {
220fc352 246 compatible = "renesas,irqc-r8a7790", "renesas,irqc";
8f5ec0a5
MD		 247 #interrupt-cells = <2>;
248 interrupt-controller;
8585deb1 249 reg = <0 0xe61c0000 0 0x200>;
5f75e73c
LP		 250 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
251 <0 1 IRQ_TYPE_LEVEL_HIGH>,
252 <0 2 IRQ_TYPE_LEVEL_HIGH>,
253 <0 3 IRQ_TYPE_LEVEL_HIGH>;
8f5ec0a5 254 };
8c9b1aa4 255
b9fea49c
LP		 256 dmac0: dma-controller@e6700000 {
257 compatible = "renesas,rcar-dmac";
258 reg = <0 0xe6700000 0 0x20000>;
259 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
260 0 200 IRQ_TYPE_LEVEL_HIGH
261 0 201 IRQ_TYPE_LEVEL_HIGH
262 0 202 IRQ_TYPE_LEVEL_HIGH
263 0 203 IRQ_TYPE_LEVEL_HIGH
264 0 204 IRQ_TYPE_LEVEL_HIGH
265 0 205 IRQ_TYPE_LEVEL_HIGH
266 0 206 IRQ_TYPE_LEVEL_HIGH
267 0 207 IRQ_TYPE_LEVEL_HIGH
268 0 208 IRQ_TYPE_LEVEL_HIGH
269 0 209 IRQ_TYPE_LEVEL_HIGH
270 0 210 IRQ_TYPE_LEVEL_HIGH
271 0 211 IRQ_TYPE_LEVEL_HIGH
272 0 212 IRQ_TYPE_LEVEL_HIGH
273 0 213 IRQ_TYPE_LEVEL_HIGH
274 0 214 IRQ_TYPE_LEVEL_HIGH>;
275 interrupt-names = "error",
276 "ch0", "ch1", "ch2", "ch3",
277 "ch4", "ch5", "ch6", "ch7",
278 "ch8", "ch9", "ch10", "ch11",
279 "ch12", "ch13", "ch14";
280 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
281 clock-names = "fck";
282 #dma-cells = <1>;
283 dma-channels = <15>;
284 };
285
286 dmac1: dma-controller@e6720000 {
287 compatible = "renesas,rcar-dmac";
288 reg = <0 0xe6720000 0 0x20000>;
289 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
290 0 216 IRQ_TYPE_LEVEL_HIGH
291 0 217 IRQ_TYPE_LEVEL_HIGH
292 0 218 IRQ_TYPE_LEVEL_HIGH
293 0 219 IRQ_TYPE_LEVEL_HIGH
294 0 308 IRQ_TYPE_LEVEL_HIGH
295 0 309 IRQ_TYPE_LEVEL_HIGH
296 0 310 IRQ_TYPE_LEVEL_HIGH
297 0 311 IRQ_TYPE_LEVEL_HIGH
298 0 312 IRQ_TYPE_LEVEL_HIGH
299 0 313 IRQ_TYPE_LEVEL_HIGH
300 0 314 IRQ_TYPE_LEVEL_HIGH
301 0 315 IRQ_TYPE_LEVEL_HIGH
302 0 316 IRQ_TYPE_LEVEL_HIGH
303 0 317 IRQ_TYPE_LEVEL_HIGH
304 0 318 IRQ_TYPE_LEVEL_HIGH>;
305 interrupt-names = "error",
306 "ch0", "ch1", "ch2", "ch3",
307 "ch4", "ch5", "ch6", "ch7",
308 "ch8", "ch9", "ch10", "ch11",
309 "ch12", "ch13", "ch14";
310 clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
311 clock-names = "fck";
312 #dma-cells = <1>;
313 dma-channels = <15>;
314 };
edd2b9f4
GL		 315 i2c0: i2c@e6508000 {
316 #address-cells = <1>;
317 #size-cells = <0>;
318 compatible = "renesas,i2c-r8a7790";
319 reg = <0 0xe6508000 0 0x40>;
5f75e73c 320 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
2450badf 321 clocks = <&mstp9_clks R8A7790_CLK_I2C0>;
edd2b9f4
GL		 322 status = "disabled";
323 };
324
325 i2c1: i2c@e6518000 {
326 #address-cells = <1>;
327 #size-cells = <0>;
328 compatible = "renesas,i2c-r8a7790";
329 reg = <0 0xe6518000 0 0x40>;
5f75e73c 330 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
2450badf 331 clocks = <&mstp9_clks R8A7790_CLK_I2C1>;
edd2b9f4
GL		 332 status = "disabled";
333 };
334
335 i2c2: i2c@e6530000 {
336 #address-cells = <1>;
337 #size-cells = <0>;
338 compatible = "renesas,i2c-r8a7790";
339 reg = <0 0xe6530000 0 0x40>;
5f75e73c 340 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
2450badf 341 clocks = <&mstp9_clks R8A7790_CLK_I2C2>;
edd2b9f4
GL		 342 status = "disabled";
343 };
344
345 i2c3: i2c@e6540000 {
346 #address-cells = <1>;
347 #size-cells = <0>;
348 compatible = "renesas,i2c-r8a7790";
349 reg = <0 0xe6540000 0 0x40>;
5f75e73c 350 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
2450badf 351 clocks = <&mstp9_clks R8A7790_CLK_I2C3>;
edd2b9f4
GL		 352 status = "disabled";
353 };
354
05f39916
WS		 355 iic0: i2c@e6500000 {
356 #address-cells = <1>;
357 #size-cells = <0>;
358 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
359 reg = <0 0xe6500000 0 0x425>;
360 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
361 clocks = <&mstp3_clks R8A7790_CLK_IIC0>;
362 status = "disabled";
363 };
364
365 iic1: i2c@e6510000 {
366 #address-cells = <1>;
367 #size-cells = <0>;
368 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
369 reg = <0 0xe6510000 0 0x425>;
370 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&mstp3_clks R8A7790_CLK_IIC1>;
372 status = "disabled";
373 };
374
375 iic2: i2c@e6520000 {
376 #address-cells = <1>;
377 #size-cells = <0>;
378 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
379 reg = <0 0xe6520000 0 0x425>;
380 interrupts = <0 176 IRQ_TYPE_LEVEL_HIGH>;
381 clocks = <&mstp3_clks R8A7790_CLK_IIC2>;
382 status = "disabled";
383 };
384
385 iic3: i2c@e60b0000 {
386 #address-cells = <1>;
387 #size-cells = <0>;
388 compatible = "renesas,iic-r8a7790", "renesas,rmobile-iic";
389 reg = <0 0xe60b0000 0 0x425>;
390 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
391 clocks = <&mstp9_clks R8A7790_CLK_IICDVFS>;
392 status = "disabled";
393 };
394
8c9b1aa4 395 mmcif0: mmcif@ee200000 {
063e8560 396 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 397 reg = <0 0xee200000 0 0x80>;
5f75e73c 398 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 399 clocks = <&mstp3_clks R8A7790_CLK_MMCIF0>;
8c9b1aa4
GL		 400 reg-io-width = <4>;
401 status = "disabled";
402 };
403
b718aa44 404 mmcif1: mmc@ee220000 {
063e8560 405 compatible = "renesas,mmcif-r8a7790", "renesas,sh-mmcif";
8c9b1aa4 406 reg = <0 0xee220000 0 0x80>;
5f75e73c 407 interrupts = <0 170 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 408 clocks = <&mstp3_clks R8A7790_CLK_MMCIF1>;
8c9b1aa4
GL		 409 reg-io-width = <4>;
410 status = "disabled";
411 };
412
9694c778
LP		 413 pfc: pfc@e6060000 {
414 compatible = "renesas,pfc-r8a7790";
415 reg = <0 0xe6060000 0 0x250>;
416 };
55689bfa 417
b718aa44 418 sdhi0: sd@ee100000 {
df1d0584 419 compatible = "renesas,sdhi-r8a7790";
d721a15c 420 reg = <0 0xee100000 0 0x200>;
5f75e73c 421 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 422 clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
8c9b1aa4
GL		 423 cap-sd-highspeed;
424 status = "disabled";
425 };
426
b718aa44 427 sdhi1: sd@ee120000 {
df1d0584 428 compatible = "renesas,sdhi-r8a7790";
d721a15c 429 reg = <0 0xee120000 0 0x200>;
5f75e73c 430 interrupts = <0 166 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 431 clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
8c9b1aa4
GL		 432 cap-sd-highspeed;
433 status = "disabled";
434 };
435
b718aa44 436 sdhi2: sd@ee140000 {
df1d0584 437 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 438 reg = <0 0xee140000 0 0x100>;
5f75e73c 439 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 440 clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
8c9b1aa4
GL		 441 cap-sd-highspeed;
442 status = "disabled";
443 };
444
b718aa44 445 sdhi3: sd@ee160000 {
df1d0584 446 compatible = "renesas,sdhi-r8a7790";
8c9b1aa4 447 reg = <0 0xee160000 0 0x100>;
5f75e73c 448 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
72197ca7 449 clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
8c9b1aa4
GL		 450 cap-sd-highspeed;
451 status = "disabled";
452 };
22a1f595 453
597af20f 454 scifa0: serial@e6c40000 {
59d2b517 455 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 456 reg = <0 0xe6c40000 0 64>;
1f4c745b 457 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 458 clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
459 clock-names = "sci_ick";
460 status = "disabled";
461 };
462
463 scifa1: serial@e6c50000 {
59d2b517 464 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 465 reg = <0 0xe6c50000 0 64>;
1f4c745b 466 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 467 clocks = <&mstp2_clks R8A7790_CLK_SCIFA1>;
468 clock-names = "sci_ick";
469 status = "disabled";
470 };
471
472 scifa2: serial@e6c60000 {
59d2b517 473 compatible = "renesas,scifa-r8a7790", "renesas,scifa";
597af20f 474 reg = <0 0xe6c60000 0 64>;
1f4c745b 475 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 476 clocks = <&mstp2_clks R8A7790_CLK_SCIFA2>;
477 clock-names = "sci_ick";
478 status = "disabled";
479 };
480
481 scifb0: serial@e6c20000 {
59d2b517 482 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 483 reg = <0 0xe6c20000 0 64>;
1f4c745b 484 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 485 clocks = <&mstp2_clks R8A7790_CLK_SCIFB0>;
486 clock-names = "sci_ick";
487 status = "disabled";
488 };
489
490 scifb1: serial@e6c30000 {
59d2b517 491 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 492 reg = <0 0xe6c30000 0 64>;
1f4c745b 493 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 494 clocks = <&mstp2_clks R8A7790_CLK_SCIFB1>;
495 clock-names = "sci_ick";
496 status = "disabled";
497 };
498
499 scifb2: serial@e6ce0000 {
59d2b517 500 compatible = "renesas,scifb-r8a7790", "renesas,scifb";
597af20f 501 reg = <0 0xe6ce0000 0 64>;
1f4c745b 502 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 503 clocks = <&mstp2_clks R8A7790_CLK_SCIFB2>;
504 clock-names = "sci_ick";
505 status = "disabled";
506 };
507
508 scif0: serial@e6e60000 {
59d2b517 509 compatible = "renesas,scif-r8a7790", "renesas,scif";
597af20f 510 reg = <0 0xe6e60000 0 64>;
1f4c745b 511 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 512 clocks = <&mstp7_clks R8A7790_CLK_SCIF0>;
513 clock-names = "sci_ick";
514 status = "disabled";
515 };
516
517 scif1: serial@e6e68000 {
59d2b517 518 compatible = "renesas,scif-r8a7790", "renesas,scif";
597af20f 519 reg = <0 0xe6e68000 0 64>;
1f4c745b 520 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 521 clocks = <&mstp7_clks R8A7790_CLK_SCIF1>;
522 clock-names = "sci_ick";
523 status = "disabled";
524 };
525
526 hscif0: serial@e62c0000 {
59d2b517 527 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
597af20f 528 reg = <0 0xe62c0000 0 96>;
1f4c745b 529 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 530 clocks = <&mstp7_clks R8A7790_CLK_HSCIF0>;
531 clock-names = "sci_ick";
532 status = "disabled";
533 };
534
535 hscif1: serial@e62c8000 {
59d2b517 536 compatible = "renesas,hscif-r8a7790", "renesas,hscif";
597af20f 537 reg = <0 0xe62c8000 0 96>;
1f4c745b 538 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
597af20f
LP		 539 clocks = <&mstp7_clks R8A7790_CLK_HSCIF1>;
540 clock-names = "sci_ick";
541 status = "disabled";
542 };
543
d8913c67
SS		 544 ether: ethernet@ee700000 {
545 compatible = "renesas,ether-r8a7790";
546 reg = <0 0xee700000 0 0x400>;
547 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
548 clocks = <&mstp8_clks R8A7790_CLK_ETHER>;
549 phy-mode = "rmii";
550 #address-cells = <1>;
551 #size-cells = <0>;
552 status = "disabled";
553 };
554
cde630f7
VB		 555 sata0: sata@ee300000 {
556 compatible = "renesas,sata-r8a7790";
557 reg = <0 0xee300000 0 0x2000>;
cde630f7
VB		 558 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
559 clocks = <&mstp8_clks R8A7790_CLK_SATA0>;
560 status = "disabled";
561 };
562
563 sata1: sata@ee500000 {
564 compatible = "renesas,sata-r8a7790";
565 reg = <0 0xee500000 0 0x2000>;
cde630f7
VB		 566 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
567 clocks = <&mstp8_clks R8A7790_CLK_SATA1>;
568 status = "disabled";
569 };
570
e089f657
SS		 571 usbphy: usb-phy@e6590100 {
572 compatible = "renesas,usb-phy-r8a7790";
573 reg = <0 0xe6590100 0 0x100>;
574 #address-cells = <1>;
575 #size-cells = <0>;
576 clocks = <&mstp7_clks R8A7790_CLK_HSUSB>;
577 clock-names = "usbhs";
578 status = "disabled";
579
580 usb0: usb-channel@0 {
581 reg = <0>;
582 #phy-cells = <1>;
583 };
584 usb2: usb-channel@2 {
585 reg = <2>;
586 #phy-cells = <1>;
587 };
588 };
589
9f685bfc
BD		 590 vin0: video@e6ef0000 {
591 compatible = "renesas,vin-r8a7790";
592 clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
593 reg = <0 0xe6ef0000 0 0x1000>;
594 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
595 status = "disabled";
596 };
597
598 vin1: video@e6ef1000 {
599 compatible = "renesas,vin-r8a7790";
600 clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
601 reg = <0 0xe6ef1000 0 0x1000>;
602 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
603 status = "disabled";
604 };
605
606 vin2: video@e6ef2000 {
607 compatible = "renesas,vin-r8a7790";
608 clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
609 reg = <0 0xe6ef2000 0 0x1000>;
610 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
611 status = "disabled";
612 };
613
614 vin3: video@e6ef3000 {
615 compatible = "renesas,vin-r8a7790";
616 clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
617 reg = <0 0xe6ef3000 0 0x1000>;
618 interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
619 status = "disabled";
620 };
621
3ac6a83c
LP		 622 vsp1@fe920000 {
623 compatible = "renesas,vsp1";
624 reg = <0 0xfe920000 0 0x8000>;
625 interrupts = <0 266 IRQ_TYPE_LEVEL_HIGH>;
626 clocks = <&mstp1_clks R8A7790_CLK_VSP1_R>;
627
628 renesas,has-sru;
629 renesas,#rpf = <5>;
630 renesas,#uds = <1>;
631 renesas,#wpf = <4>;
632 };
633
634 vsp1@fe928000 {
635 compatible = "renesas,vsp1";
636 reg = <0 0xfe928000 0 0x8000>;
637 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
638 clocks = <&mstp1_clks R8A7790_CLK_VSP1_S>;
639
640 renesas,has-lut;
641 renesas,has-sru;
642 renesas,#rpf = <5>;
643 renesas,#uds = <3>;
644 renesas,#wpf = <4>;
645 };
646
647 vsp1@fe930000 {
648 compatible = "renesas,vsp1";
649 reg = <0 0xfe930000 0 0x8000>;
650 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU0>;
652
653 renesas,has-lif;
654 renesas,has-lut;
655 renesas,#rpf = <4>;
656 renesas,#uds = <1>;
657 renesas,#wpf = <4>;
658 };
659
660 vsp1@fe938000 {
661 compatible = "renesas,vsp1";
662 reg = <0 0xfe938000 0 0x8000>;
663 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
664 clocks = <&mstp1_clks R8A7790_CLK_VSP1_DU1>;
665
666 renesas,has-lif;
667 renesas,has-lut;
668 renesas,#rpf = <4>;
669 renesas,#uds = <1>;
670 renesas,#wpf = <4>;
671 };
672
673 du: display@feb00000 {
674 compatible = "renesas,du-r8a7790";
675 reg = <0 0xfeb00000 0 0x70000>,
676 <0 0xfeb90000 0 0x1c>,
677 <0 0xfeb94000 0 0x1c>;
678 reg-names = "du", "lvds.0", "lvds.1";
679 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
680 <0 268 IRQ_TYPE_LEVEL_HIGH>,
681 <0 269 IRQ_TYPE_LEVEL_HIGH>;
682 clocks = <&mstp7_clks R8A7790_CLK_DU0>,
683 <&mstp7_clks R8A7790_CLK_DU1>,
684 <&mstp7_clks R8A7790_CLK_DU2>,
685 <&mstp7_clks R8A7790_CLK_LVDS0>,
686 <&mstp7_clks R8A7790_CLK_LVDS1>;
687 clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";
688 status = "disabled";
689
690 ports {
691 #address-cells = <1>;
692 #size-cells = <0>;
693
694 port@0 {
695 reg = <0>;
696 du_out_rgb: endpoint {
697 };
698 };
699 port@1 {
700 reg = <1>;
701 du_out_lvds0: endpoint {
702 };
703 };
704 port@2 {
705 reg = <2>;
706 du_out_lvds1: endpoint {
707 };
708 };
709 };
710 };
711
22a1f595
LP		 712 clocks {
713 #address-cells = <2>;
714 #size-cells = <2>;
715 ranges;
716
717 /* External root clock */
718 extal_clk: extal_clk {
719 compatible = "fixed-clock";
720 #clock-cells = <0>;
721 /* This value must be overriden by the board. */
722 clock-frequency = <0>;
723 clock-output-names = "extal";
724 };
725
51d17918
PE		 726 /* External PCIe clock - can be overridden by the board */
727 pcie_bus_clk: pcie_bus_clk {
728 compatible = "fixed-clock";
729 #clock-cells = <0>;
730 clock-frequency = <100000000>;
731 clock-output-names = "pcie_bus";
732 status = "disabled";
733 };
734
c7c2ec3a
KM		 735 /*
736 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
737 * default. Boards that provide audio clocks should override them.
738 */
739 audio_clk_a: audio_clk_a {
740 compatible = "fixed-clock";
741 #clock-cells = <0>;
742 clock-frequency = <0>;
743 clock-output-names = "audio_clk_a";
744 };
745 audio_clk_b: audio_clk_b {
746 compatible = "fixed-clock";
747 #clock-cells = <0>;
748 clock-frequency = <0>;
749 clock-output-names = "audio_clk_b";
750 };
751 audio_clk_c: audio_clk_c {
752 compatible = "fixed-clock";
753 #clock-cells = <0>;
754 clock-frequency = <0>;
755 clock-output-names = "audio_clk_c";
756 };
757
22a1f595
LP		 758 /* Special CPG clocks */
759 cpg_clocks: cpg_clocks@e6150000 {
760 compatible = "renesas,r8a7790-cpg-clocks",
761 "renesas,rcar-gen2-cpg-clocks";
762 reg = <0 0xe6150000 0 0x1000>;
763 clocks = <&extal_clk>;
764 #clock-cells = <1>;
765 clock-output-names = "main", "pll0", "pll1", "pll3",
766 "lb", "qspi", "sdh", "sd0", "sd1",
767 "z";
768 };
769
770 /* Variable factor clocks */
771 sd2_clk: sd2_clk@e6150078 {
772 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
773 reg = <0 0xe6150078 0 4>;
774 clocks = <&pll1_div2_clk>;
775 #clock-cells = <0>;
776 clock-output-names = "sd2";
777 };
778 sd3_clk: sd3_clk@e615007c {
779 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
780 reg = <0 0xe615007c 0 4>;
781 clocks = <&pll1_div2_clk>;
782 #clock-cells = <0>;
783 clock-output-names = "sd3";
784 };
785 mmc0_clk: mmc0_clk@e6150240 {
786 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
787 reg = <0 0xe6150240 0 4>;
788 clocks = <&pll1_div2_clk>;
789 #clock-cells = <0>;
790 clock-output-names = "mmc0";
791 };
792 mmc1_clk: mmc1_clk@e6150244 {
793 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
794 reg = <0 0xe6150244 0 4>;
795 clocks = <&pll1_div2_clk>;
796 #clock-cells = <0>;
797 clock-output-names = "mmc1";
798 };
799 ssp_clk: ssp_clk@e6150248 {
800 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
801 reg = <0 0xe6150248 0 4>;
802 clocks = <&pll1_div2_clk>;
803 #clock-cells = <0>;
804 clock-output-names = "ssp";
805 };
806 ssprs_clk: ssprs_clk@e615024c {
807 compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
808 reg = <0 0xe615024c 0 4>;
809 clocks = <&pll1_div2_clk>;
810 #clock-cells = <0>;
811 clock-output-names = "ssprs";
812 };
813
814 /* Fixed factor clocks */
815 pll1_div2_clk: pll1_div2_clk {
816 compatible = "fixed-factor-clock";
817 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
818 #clock-cells = <0>;
819 clock-div = <2>;
820 clock-mult = <1>;
821 clock-output-names = "pll1_div2";
822 };
823 z2_clk: z2_clk {
824 compatible = "fixed-factor-clock";
825 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
826 #clock-cells = <0>;
827 clock-div = <2>;
828 clock-mult = <1>;
829 clock-output-names = "z2";
830 };
831 zg_clk: zg_clk {
832 compatible = "fixed-factor-clock";
833 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
834 #clock-cells = <0>;
835 clock-div = <3>;
836 clock-mult = <1>;
837 clock-output-names = "zg";
838 };
839 zx_clk: zx_clk {
840 compatible = "fixed-factor-clock";
841 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
842 #clock-cells = <0>;
843 clock-div = <3>;
844 clock-mult = <1>;
845 clock-output-names = "zx";
846 };
847 zs_clk: zs_clk {
848 compatible = "fixed-factor-clock";
849 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
850 #clock-cells = <0>;
851 clock-div = <6>;
852 clock-mult = <1>;
853 clock-output-names = "zs";
854 };
855 hp_clk: hp_clk {
856 compatible = "fixed-factor-clock";
857 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
858 #clock-cells = <0>;
859 clock-div = <12>;
860 clock-mult = <1>;
861 clock-output-names = "hp";
862 };
863 i_clk: i_clk {
864 compatible = "fixed-factor-clock";
865 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
866 #clock-cells = <0>;
867 clock-div = <2>;
868 clock-mult = <1>;
869 clock-output-names = "i";
870 };
871 b_clk: b_clk {
872 compatible = "fixed-factor-clock";
873 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
874 #clock-cells = <0>;
875 clock-div = <12>;
876 clock-mult = <1>;
877 clock-output-names = "b";
878 };
879 p_clk: p_clk {
880 compatible = "fixed-factor-clock";
881 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
882 #clock-cells = <0>;
883 clock-div = <24>;
884 clock-mult = <1>;
885 clock-output-names = "p";
886 };
887 cl_clk: cl_clk {
888 compatible = "fixed-factor-clock";
889 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
890 #clock-cells = <0>;
891 clock-div = <48>;
892 clock-mult = <1>;
893 clock-output-names = "cl";
894 };
895 m2_clk: m2_clk {
896 compatible = "fixed-factor-clock";
897 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
898 #clock-cells = <0>;
899 clock-div = <8>;
900 clock-mult = <1>;
901 clock-output-names = "m2";
902 };
903 imp_clk: imp_clk {
904 compatible = "fixed-factor-clock";
905 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
906 #clock-cells = <0>;
907 clock-div = <4>;
908 clock-mult = <1>;
909 clock-output-names = "imp";
910 };
911 rclk_clk: rclk_clk {
912 compatible = "fixed-factor-clock";
913 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
914 #clock-cells = <0>;
915 clock-div = <(48 * 1024)>;
916 clock-mult = <1>;
917 clock-output-names = "rclk";
918 };
919 oscclk_clk: oscclk_clk {
920 compatible = "fixed-factor-clock";
921 clocks = <&cpg_clocks R8A7790_CLK_PLL1>;
922 #clock-cells = <0>;
923 clock-div = <(12 * 1024)>;
924 clock-mult = <1>;
925 clock-output-names = "oscclk";
926 };
927 zb3_clk: zb3_clk {
928 compatible = "fixed-factor-clock";
929 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
930 #clock-cells = <0>;
931 clock-div = <4>;
932 clock-mult = <1>;
933 clock-output-names = "zb3";
934 };
935 zb3d2_clk: zb3d2_clk {
936 compatible = "fixed-factor-clock";
937 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
938 #clock-cells = <0>;
939 clock-div = <8>;
940 clock-mult = <1>;
941 clock-output-names = "zb3d2";
942 };
943 ddr_clk: ddr_clk {
944 compatible = "fixed-factor-clock";
945 clocks = <&cpg_clocks R8A7790_CLK_PLL3>;
946 #clock-cells = <0>;
947 clock-div = <8>;
948 clock-mult = <1>;
949 clock-output-names = "ddr";
950 };
951 mp_clk: mp_clk {
952 compatible = "fixed-factor-clock";
953 clocks = <&pll1_div2_clk>;
954 #clock-cells = <0>;
955 clock-div = <15>;
956 clock-mult = <1>;
957 clock-output-names = "mp";
958 };
959 cp_clk: cp_clk {
960 compatible = "fixed-factor-clock";
961 clocks = <&extal_clk>;
962 #clock-cells = <0>;
963 clock-div = <2>;
964 clock-mult = <1>;
965 clock-output-names = "cp";
966 };
967
968 /* Gate clocks */
9d90951a
LP		 969 mstp0_clks: mstp0_clks@e6150130 {
970 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
971 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
972 clocks = <&mp_clk>;
973 #clock-cells = <1>;
974 renesas,clock-indices = <R8A7790_CLK_MSIOF0>;
975 clock-output-names = "msiof0";
976 };
22a1f595
LP		 977 mstp1_clks: mstp1_clks@e6150134 {
978 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
979 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
4ba8f246
YH		 980 clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
981 <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>, <&zs_clk>,
982 <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
983 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
22a1f595
LP		 984 #clock-cells = <1>;
985 renesas,clock-indices = <
4ba8f246
YH		 986 R8A7790_CLK_VCP1 R8A7790_CLK_VCP0 R8A7790_CLK_VPC1
987 R8A7790_CLK_VPC0 R8A7790_CLK_JPU R8A7790_CLK_SSP1
988 R8A7790_CLK_TMU1 R8A7790_CLK_3DG R8A7790_CLK_2DDMAC
989 R8A7790_CLK_FDP1_2 R8A7790_CLK_FDP1_1 R8A7790_CLK_FDP1_0
990 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2 R8A7790_CLK_CMT0
991 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1 R8A7790_CLK_VSP1_DU0
992 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
22a1f595
LP		 993 >;
994 clock-output-names =
4ba8f246
YH		 995 "vcp1", "vcp0", "vpc1", "vpc0", "jpu", "ssp1",
996 "tmu1", "3dg", "2ddmac", "fdp1-2", "fdp1-1",
997 "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
2284ff5f 998 "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
22a1f595
LP		 999 };
1000 mstp2_clks: mstp2_clks@e6150138 {
1001 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1002 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1003 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
c819acda
LP		 1004 <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&zs_clk>,
1005 <&zs_clk>;
22a1f595
LP		 1006 #clock-cells = <1>;
1007 renesas,clock-indices = <
1008 R8A7790_CLK_SCIFA2 R8A7790_CLK_SCIFA1 R8A7790_CLK_SCIFA0
9d90951a
LP		 1009 R8A7790_CLK_MSIOF2 R8A7790_CLK_SCIFB0 R8A7790_CLK_SCIFB1
1010 R8A7790_CLK_MSIOF1 R8A7790_CLK_MSIOF3 R8A7790_CLK_SCIFB2
c819acda 1011 R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
22a1f595
LP		 1012 >;
1013 clock-output-names =
9d90951a 1014 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
c819acda
LP		 1015 "scifb1", "msiof1", "msiof3", "scifb2",
1016 "sys-dmac1", "sys-dmac0";
22a1f595
LP		 1017 };
1018 mstp3_clks: mstp3_clks@e615013c {
1019 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1020 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
17465149
WS		 1021 clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
1022 <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
ecafea8c 1023 <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>;
22a1f595
LP		 1024 #clock-cells = <1>;
1025 renesas,clock-indices = <
17465149
WS		 1026 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
1027 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
ecafea8c 1028 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
22a1f595
LP		 1029 >;
1030 clock-output-names =
17465149
WS		 1031 "iic2", "tpu0", "mmcif1", "sdhi3",
1032 "sdhi2", "sdhi1", "sdhi0", "mmcif0",
ecafea8c 1033 "iic0", "pciec", "iic1", "ssusb", "cmt1";
22a1f595
LP		 1034 };
1035 mstp5_clks: mstp5_clks@e6150144 {
1036 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1037 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1038 clocks = <&extal_clk>, <&p_clk>;
1039 #clock-cells = <1>;
1040 renesas,clock-indices = <R8A7790_CLK_THERMAL R8A7790_CLK_PWM>;
1041 clock-output-names = "thermal", "pwm";
1042 };
1043 mstp7_clks: mstp7_clks@e615014c {
1044 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1045 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
1046 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1047 <&p_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>, <&zx_clk>,
1048 <&zx_clk>;
1049 #clock-cells = <1>;
1050 renesas,clock-indices = <
1051 R8A7790_CLK_EHCI R8A7790_CLK_HSUSB R8A7790_CLK_HSCIF1
1052 R8A7790_CLK_HSCIF0 R8A7790_CLK_SCIF1 R8A7790_CLK_SCIF0
1053 R8A7790_CLK_DU2 R8A7790_CLK_DU1 R8A7790_CLK_DU0
1054 R8A7790_CLK_LVDS1 R8A7790_CLK_LVDS0
1055 >;
1056 clock-output-names =
1057 "ehci", "hsusb", "hscif1", "hscif0", "scif1",
1058 "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
1059 };
1060 mstp8_clks: mstp8_clks@e6150990 {
1061 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1062 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
bccccc3d
LP		 1063 clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, <&p_clk>,
1064 <&zs_clk>, <&zs_clk>;
22a1f595 1065 #clock-cells = <1>;
3f2beaa9
LP		 1066 renesas,clock-indices = <
1067 R8A7790_CLK_VIN3 R8A7790_CLK_VIN2 R8A7790_CLK_VIN1
bccccc3d
LP		 1068 R8A7790_CLK_VIN0 R8A7790_CLK_ETHER R8A7790_CLK_SATA1
1069 R8A7790_CLK_SATA0
3f2beaa9 1070 >;
bccccc3d
LP		 1071 clock-output-names =
1072 "vin3", "vin2", "vin1", "vin0", "ether", "sata1", "sata0";
22a1f595
LP		 1073 };
1074 mstp9_clks: mstp9_clks@e6150994 {
1075 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1076 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
81f6883f
GU		 1077 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
1078 <&cp_clk>, <&cp_clk>, <&cp_clk>,
1079 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7790_CLK_QSPI>, <&cp_clk>,
3672b059 1080 <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
22a1f595
LP		 1081 #clock-cells = <1>;
1082 renesas,clock-indices = <
81f6883f
GU		 1083 R8A7790_CLK_GPIO5 R8A7790_CLK_GPIO4 R8A7790_CLK_GPIO3
1084 R8A7790_CLK_GPIO2 R8A7790_CLK_GPIO1 R8A7790_CLK_GPIO0
17465149
WS		 1085 R8A7790_CLK_RCAN1 R8A7790_CLK_RCAN0 R8A7790_CLK_QSPI_MOD R8A7790_CLK_IICDVFS
1086 R8A7790_CLK_I2C3 R8A7790_CLK_I2C2 R8A7790_CLK_I2C1 R8A7790_CLK_I2C0
22a1f595 1087 >;
91b56ca1 1088 clock-output-names =
81f6883f 1089 "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
17465149
WS		 1090 "rcan1", "rcan0", "qspi_mod", "iic3",
1091 "i2c3", "i2c2", "i2c1", "i2c0";
22a1f595 1092 };
bcde3722
KM		 1093 mstp10_clks: mstp10_clks@e6150998 {
1094 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1095 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1096 clocks = <&p_clk>,
1097 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1098 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1099 <&p_clk>,
1100 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1101 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1102 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1103 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1104 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>,
1105 <&mstp10_clks R8A7790_CLK_SCU_ALL>, <&mstp10_clks R8A7790_CLK_SCU_ALL>;
1106
1107 #clock-cells = <1>;
1108 clock-indices = <
1109 R8A7790_CLK_SSI_ALL
1110 R8A7790_CLK_SSI9 R8A7790_CLK_SSI8 R8A7790_CLK_SSI7 R8A7790_CLK_SSI6 R8A7790_CLK_SSI5
1111 R8A7790_CLK_SSI4 R8A7790_CLK_SSI3 R8A7790_CLK_SSI2 R8A7790_CLK_SSI1 R8A7790_CLK_SSI0
1112 R8A7790_CLK_SCU_ALL
1113 R8A7790_CLK_SCU_DVC1 R8A7790_CLK_SCU_DVC0
1114 R8A7790_CLK_SCU_SRC9 R8A7790_CLK_SCU_SRC8 R8A7790_CLK_SCU_SRC7 R8A7790_CLK_SCU_SRC6 R8A7790_CLK_SCU_SRC5
1115 R8A7790_CLK_SCU_SRC4 R8A7790_CLK_SCU_SRC3 R8A7790_CLK_SCU_SRC2 R8A7790_CLK_SCU_SRC1 R8A7790_CLK_SCU_SRC0
1116 >;
1117 clock-output-names =
1118 "ssi-all",
1119 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1120 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1121 "scu-all",
1122 "scu-dvc1", "scu-dvc0",
1123 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1124 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1125 };
22a1f595 1126 };
7053e134 1127
fad6d45c 1128 qspi: spi@e6b10000 {
7053e134
GU		 1129 compatible = "renesas,qspi-r8a7790", "renesas,qspi";
1130 reg = <0 0xe6b10000 0 0x2c>;
7053e134
GU		 1131 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1132 clocks = <&mstp9_clks R8A7790_CLK_QSPI_MOD>;
37cf3d61
GU		 1133 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1134 dma-names = "tx", "rx";
7053e134
GU		 1135 num-cs = <1>;
1136 #address-cells = <1>;
1137 #size-cells = <0>;
1138 status = "disabled";
1139 };
ae8a6146
GU		 1140
1141 msiof0: spi@e6e20000 {
1142 compatible = "renesas,msiof-r8a7790";
fbff6688 1143 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
ae8a6146
GU		 1144 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1145 clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
fbff6688
GU		 1146 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1147 dma-names = "tx", "rx";
ae8a6146
GU		 1148 #address-cells = <1>;
1149 #size-cells = <0>;
1150 status = "disabled";
1151 };
1152
1153 msiof1: spi@e6e10000 {
1154 compatible = "renesas,msiof-r8a7790";
fbff6688 1155 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
ae8a6146
GU		 1156 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1157 clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
fbff6688
GU		 1158 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1159 dma-names = "tx", "rx";
ae8a6146
GU		 1160 #address-cells = <1>;
1161 #size-cells = <0>;
1162 status = "disabled";
1163 };
1164
1165 msiof2: spi@e6e00000 {
1166 compatible = "renesas,msiof-r8a7790";
fbff6688 1167 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
ae8a6146
GU		 1168 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1169 clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
fbff6688
GU		 1170 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1171 dma-names = "tx", "rx";
ae8a6146
GU		 1172 #address-cells = <1>;
1173 #size-cells = <0>;
1174 status = "disabled";
1175 };
1176
1177 msiof3: spi@e6c90000 {
1178 compatible = "renesas,msiof-r8a7790";
fbff6688 1179 reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
ae8a6146
GU		 1180 interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
1181 clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
fbff6688
GU		 1182 dmas = <&dmac0 0x45>, <&dmac0 0x46>;
1183 dma-names = "tx", "rx";
ae8a6146
GU		 1184 #address-cells = <1>;
1185 #size-cells = <0>;
1186 status = "disabled";
1187 };
7df2fd57 1188
157fcd8a
YS		 1189 xhci: usb@ee000000 {
1190 compatible = "renesas,xhci-r8a7790";
1191 reg = <0 0xee000000 0 0xc00>;
1192 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
1194 phys = <&usb2 1>;
1195 phy-names = "usb";
1196 status = "disabled";
1197 };
1198
ff4f3eb8
BD		 1199 pci0: pci@ee090000 {
1200 compatible = "renesas,pci-r8a7790";
1201 device_type = "pci";
1202 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1203 reg = <0 0xee090000 0 0xc00>,
1204 <0 0xee080000 0 0x1100>;
1205 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1206 status = "disabled";
1207
1208 bus-range = <0 0>;
1209 #address-cells = <3>;
1210 #size-cells = <2>;
1211 #interrupt-cells = <1>;
1212 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1213 interrupt-map-mask = <0xff00 0 0 0x7>;
1214 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1215 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1216 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1217
1218 usb@0,1 {
1219 reg = <0x800 0 0 0 0>;
1220 device_type = "pci";
1221 phys = <&usb0 0>;
1222 phy-names = "usb";
1223 };
1224
1225 usb@0,2 {
1226 reg = <0x1000 0 0 0 0>;
1227 device_type = "pci";
1228 phys = <&usb0 0>;
1229 phy-names = "usb";
1230 };
ff4f3eb8
BD		 1231 };
1232
1233 pci1: pci@ee0b0000 {
1234 compatible = "renesas,pci-r8a7790";
1235 device_type = "pci";
1236 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1237 reg = <0 0xee0b0000 0 0xc00>,
1238 <0 0xee0a0000 0 0x1100>;
1239 interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>;
1240 status = "disabled";
1241
1242 bus-range = <1 1>;
1243 #address-cells = <3>;
1244 #size-cells = <2>;
1245 #interrupt-cells = <1>;
1246 ranges = <0x02000000 0 0xee0a0000 0 0xee0a0000 0 0x00010000>;
1247 interrupt-map-mask = <0xff00 0 0 0x7>;
1248 interrupt-map = <0x0000 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1249 0x0800 0 0 1 &gic 0 112 IRQ_TYPE_LEVEL_HIGH
1250 0x1000 0 0 2 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>;
ff4f3eb8
BD		 1251 };
1252
1253 pci2: pci@ee0d0000 {
1254 compatible = "renesas,pci-r8a7790";
1255 device_type = "pci";
1256 clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
1257 reg = <0 0xee0d0000 0 0xc00>,
1258 <0 0xee0c0000 0 0x1100>;
1259 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1260 status = "disabled";
1261
1262 bus-range = <2 2>;
1263 #address-cells = <3>;
1264 #size-cells = <2>;
1265 #interrupt-cells = <1>;
1266 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1267 interrupt-map-mask = <0xff00 0 0 0x7>;
1268 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
517ec80a
GU		 1269 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1270 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
538c40e5
SS		 1271
1272 usb@0,1 {
1273 reg = <0x800 0 0 0 0>;
1274 device_type = "pci";
1275 phys = <&usb2 0>;
1276 phy-names = "usb";
1277 };
1278
1279 usb@0,2 {
1280 reg = <0x1000 0 0 0 0>;
1281 device_type = "pci";
1282 phys = <&usb2 0>;
1283 phy-names = "usb";
1284 };
ff4f3eb8
BD		 1285 };
1286
745329d2
PE		 1287 pciec: pcie@fe000000 {
1288 compatible = "renesas,pcie-r8a7790";
1289 reg = <0 0xfe000000 0 0x80000>;
1290 #address-cells = <3>;
1291 #size-cells = <2>;
1292 bus-range = <0x00 0xff>;
1293 device_type = "pci";
1294 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1295 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1296 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1297 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1298 /* Map all possible DDR as inbound ranges */
1299 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1300 0x43000000 1 0x80000000 1 0x80000000 0 0x80000000>;
1301 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1302 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1303 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1304 #interrupt-cells = <1>;
1305 interrupt-map-mask = <0 0 0 0>;
1306 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1307 clocks = <&mstp3_clks R8A7790_CLK_PCIEC>, <&pcie_bus_clk>;
1308 clock-names = "pcie", "pcie_bus";
1309 status = "disabled";
1310 };
1311
7df2fd57
KM		 1312 rcar_sound: rcar_sound@0xec500000 {
1313 #sound-dai-cells = <1>;
1314 compatible = "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
7df2fd57
KM		 1315 reg = <0 0xec500000 0 0x1000>, /* SCU */
1316 <0 0xec5a0000 0 0x100>, /* ADG */
1317 <0 0xec540000 0 0x1000>, /* SSIU */
1318 <0 0xec541000 0 0x1280>; /* SSI */
1319 clocks = <&mstp10_clks R8A7790_CLK_SSI_ALL>,
1320 <&mstp10_clks R8A7790_CLK_SSI9>, <&mstp10_clks R8A7790_CLK_SSI8>,
1321 <&mstp10_clks R8A7790_CLK_SSI7>, <&mstp10_clks R8A7790_CLK_SSI6>,
1322 <&mstp10_clks R8A7790_CLK_SSI5>, <&mstp10_clks R8A7790_CLK_SSI4>,
1323 <&mstp10_clks R8A7790_CLK_SSI3>, <&mstp10_clks R8A7790_CLK_SSI2>,
1324 <&mstp10_clks R8A7790_CLK_SSI1>, <&mstp10_clks R8A7790_CLK_SSI0>,
1325 <&mstp10_clks R8A7790_CLK_SCU_SRC9>, <&mstp10_clks R8A7790_CLK_SCU_SRC8>,
1326 <&mstp10_clks R8A7790_CLK_SCU_SRC7>, <&mstp10_clks R8A7790_CLK_SCU_SRC6>,
1327 <&mstp10_clks R8A7790_CLK_SCU_SRC5>, <&mstp10_clks R8A7790_CLK_SCU_SRC4>,
1328 <&mstp10_clks R8A7790_CLK_SCU_SRC3>, <&mstp10_clks R8A7790_CLK_SCU_SRC2>,
1329 <&mstp10_clks R8A7790_CLK_SCU_SRC1>, <&mstp10_clks R8A7790_CLK_SCU_SRC0>,
334d69a2 1330 <&mstp10_clks R8A7790_CLK_SCU_DVC0>, <&mstp10_clks R8A7790_CLK_SCU_DVC1>,
7df2fd57
KM		 1331 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1332 clock-names = "ssi-all",
1333 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1334 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1335 "src.9", "src.8", "src.7", "src.6", "src.5",
1336 "src.4", "src.3", "src.2", "src.1", "src.0",
334d69a2 1337 "dvc.0", "dvc.1",
7df2fd57
KM		 1338 "clk_a", "clk_b", "clk_c", "clk_i";
1339
1340 status = "disabled";
1341
334d69a2
KM		 1342 rcar_sound,dvc {
1343 dvc0: dvc@0 { };
1344 dvc1: dvc@1 { };
1345 };
1346
7df2fd57
KM		 1347 rcar_sound,src {
1348 src0: src@0 { };
1349 src1: src@1 { };
1350 src2: src@2 { };
1351 src3: src@3 { };
1352 src4: src@4 { };
1353 src5: src@5 { };
1354 src6: src@6 { };
1355 src7: src@7 { };
1356 src8: src@8 { };
1357 src9: src@9 { };
1358 };
1359
1360 rcar_sound,ssi {
1361 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1362 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1363 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1364 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1365 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1366 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1367 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1368 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1369 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1370 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1371 };
1372 };
0468b2d6 1373};
Linux kernel - Deliverables
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