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ARM: shmobile: r8a7790: tidyup SDHI register size on DTSI
[deliverable/linux.git] / arch / arm / boot / dts / r8a7791.dtsi
CommitLineData
0d0771ab
HN		 1/*
2 * Device Tree Source for the r8a7791 SoC
3 *
e4d2fd9e 4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
2e5d55ce
SS		 5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
6 * Copyright (C) 2014 Cogent Embedded Inc.
0d0771ab
HN		 7 *
8 * This file is licensed under the terms of the GNU General Public License
9 * version 2. This program is licensed "as is" without any warranty of any
10 * kind, whether express or implied.
11 */
12
59e79895 13#include <dt-bindings/clock/r8a7791-clock.h>
5f75e73c
LP		 14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
0d0771ab
HN		 17/ {
18 compatible = "renesas,r8a7791";
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
22
5bd3de7b
WS		 23 aliases {
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 i2c2 = &i2c2;
27 i2c3 = &i2c3;
28 i2c4 = &i2c4;
29 i2c5 = &i2c5;
36408d9d
WS		 30 i2c6 = &i2c6;
31 i2c7 = &i2c7;
32 i2c8 = &i2c8;
6f3e4ee3 33 spi0 = &qspi;
7713d3ab
GU		 34 spi1 = &msiof0;
35 spi2 = &msiof1;
36 spi3 = &msiof2;
0b8d1d57
SS		 37 vin0 = &vin0;
38 vin1 = &vin1;
39 vin2 = &vin2;
5bd3de7b
WS		 40 };
41
0d0771ab
HN		 42 cpus {
43 #address-cells = <1>;
44 #size-cells = <0>;
45
46 cpu0: cpu@0 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a15";
49 reg = <0>;
896b79df 50 clock-frequency = <1500000000>;
a57004ec
GI		 51 voltage-tolerance = <1>; /* 1% */
52 clocks = <&cpg_clocks R8A7791_CLK_Z>;
53 clock-latency = <300000>; /* 300 us */
54
55 /* kHz - uV - OPPs unknown yet */
56 operating-points = <1500000 1000000>,
57 <1312500 1000000>,
58 <1125000 1000000>,
59 < 937500 1000000>,
60 < 750000 1000000>,
61 < 375000 1000000>;
0d0771ab 62 };
15ab426c
MD		 63
64 cpu1: cpu@1 {
65 device_type = "cpu";
66 compatible = "arm,cortex-a15";
67 reg = <1>;
896b79df 68 clock-frequency = <1500000000>;
15ab426c 69 };
0d0771ab
HN		 70 };
71
72 gic: interrupt-controller@f1001000 {
73 compatible = "arm,cortex-a15-gic";
74 #interrupt-cells = <3>;
75 #address-cells = <0>;
76 interrupt-controller;
77 reg = <0 0xf1001000 0 0x1000>,
78 <0 0xf1002000 0 0x1000>,
79 <0 0xf1004000 0 0x2000>,
80 <0 0xf1006000 0 0x2000>;
aa5404fc 81 interrupts = <1 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
0d0771ab 82 };
d77db73e 83
89fbba12 84 gpio0: gpio@e6050000 {
ab87e3fc 85 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 86 reg = <0 0xe6050000 0 0x50>;
5f75e73c 87 interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 88 #gpio-cells = <2>;
89 gpio-controller;
90 gpio-ranges = <&pfc 0 0 32>;
91 #interrupt-cells = <2>;
92 interrupt-controller;
4faf9c5e 93 clocks = <&mstp9_clks R8A7791_CLK_GPIO0>;
ab87e3fc
MD		 94 };
95
89fbba12 96 gpio1: gpio@e6051000 {
ab87e3fc 97 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 98 reg = <0 0xe6051000 0 0x50>;
5f75e73c 99 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 100 #gpio-cells = <2>;
101 gpio-controller;
102 gpio-ranges = <&pfc 0 32 32>;
103 #interrupt-cells = <2>;
104 interrupt-controller;
4faf9c5e 105 clocks = <&mstp9_clks R8A7791_CLK_GPIO1>;
ab87e3fc
MD		 106 };
107
89fbba12 108 gpio2: gpio@e6052000 {
ab87e3fc 109 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 110 reg = <0 0xe6052000 0 0x50>;
5f75e73c 111 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 112 #gpio-cells = <2>;
113 gpio-controller;
114 gpio-ranges = <&pfc 0 64 32>;
115 #interrupt-cells = <2>;
116 interrupt-controller;
4faf9c5e 117 clocks = <&mstp9_clks R8A7791_CLK_GPIO2>;
ab87e3fc
MD		 118 };
119
89fbba12 120 gpio3: gpio@e6053000 {
ab87e3fc 121 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 122 reg = <0 0xe6053000 0 0x50>;
5f75e73c 123 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 124 #gpio-cells = <2>;
125 gpio-controller;
126 gpio-ranges = <&pfc 0 96 32>;
127 #interrupt-cells = <2>;
128 interrupt-controller;
4faf9c5e 129 clocks = <&mstp9_clks R8A7791_CLK_GPIO3>;
ab87e3fc
MD		 130 };
131
89fbba12 132 gpio4: gpio@e6054000 {
ab87e3fc 133 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 134 reg = <0 0xe6054000 0 0x50>;
5f75e73c 135 interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 136 #gpio-cells = <2>;
137 gpio-controller;
138 gpio-ranges = <&pfc 0 128 32>;
139 #interrupt-cells = <2>;
140 interrupt-controller;
4faf9c5e 141 clocks = <&mstp9_clks R8A7791_CLK_GPIO4>;
ab87e3fc
MD		 142 };
143
89fbba12 144 gpio5: gpio@e6055000 {
ab87e3fc 145 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 146 reg = <0 0xe6055000 0 0x50>;
5f75e73c 147 interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 148 #gpio-cells = <2>;
149 gpio-controller;
150 gpio-ranges = <&pfc 0 160 32>;
151 #interrupt-cells = <2>;
152 interrupt-controller;
4faf9c5e 153 clocks = <&mstp9_clks R8A7791_CLK_GPIO5>;
ab87e3fc
MD		 154 };
155
89fbba12 156 gpio6: gpio@e6055400 {
ab87e3fc 157 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 158 reg = <0 0xe6055400 0 0x50>;
5f75e73c 159 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 160 #gpio-cells = <2>;
161 gpio-controller;
162 gpio-ranges = <&pfc 0 192 32>;
163 #interrupt-cells = <2>;
164 interrupt-controller;
4faf9c5e 165 clocks = <&mstp9_clks R8A7791_CLK_GPIO6>;
ab87e3fc
MD		 166 };
167
89fbba12 168 gpio7: gpio@e6055800 {
ab87e3fc 169 compatible = "renesas,gpio-r8a7791", "renesas,gpio-rcar";
89fbba12 170 reg = <0 0xe6055800 0 0x50>;
5f75e73c 171 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
ab87e3fc
MD		 172 #gpio-cells = <2>;
173 gpio-controller;
174 gpio-ranges = <&pfc 0 224 26>;
175 #interrupt-cells = <2>;
176 interrupt-controller;
4faf9c5e 177 clocks = <&mstp9_clks R8A7791_CLK_GPIO7>;
ab87e3fc
MD		 178 };
179
d103f4d3
MD		 180 thermal@e61f0000 {
181 compatible = "renesas,thermal-r8a7791", "renesas,rcar-thermal";
182 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>;
d103f4d3 183 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>;
563bc8eb 184 clocks = <&mstp5_clks R8A7791_CLK_THERMAL>;
d103f4d3
MD		 185 };
186
03586acf
MD		 187 timer {
188 compatible = "arm,armv7-timer";
aa5404fc
GU		 189 interrupts = <1 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
190 <1 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
191 <1 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
192 <1 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
03586acf
MD		 193 };
194
ceaa1894 195 cmt0: timer@ffca0000 {
4217f323 196 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
ceaa1894
LP		 197 reg = <0 0xffca0000 0 0x1004>;
198 interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
199 <0 143 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&mstp1_clks R8A7791_CLK_CMT0>;
201 clock-names = "fck";
202
203 renesas,channels-mask = <0x60>;
204
205 status = "disabled";
206 };
207
208 cmt1: timer@e6130000 {
4217f323 209 compatible = "renesas,cmt-48-r8a7791", "renesas,cmt-48-gen2";
ceaa1894
LP		 210 reg = <0 0xe6130000 0 0x1004>;
211 interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
212 <0 121 IRQ_TYPE_LEVEL_HIGH>,
213 <0 122 IRQ_TYPE_LEVEL_HIGH>,
214 <0 123 IRQ_TYPE_LEVEL_HIGH>,
215 <0 124 IRQ_TYPE_LEVEL_HIGH>,
216 <0 125 IRQ_TYPE_LEVEL_HIGH>,
217 <0 126 IRQ_TYPE_LEVEL_HIGH>,
218 <0 127 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&mstp3_clks R8A7791_CLK_CMT1>;
220 clock-names = "fck";
221
222 renesas,channels-mask = <0xff>;
223
224 status = "disabled";
225 };
226
d77db73e 227 irqc0: interrupt-controller@e61c0000 {
26041b06 228 compatible = "renesas,irqc-r8a7791", "renesas,irqc";
d77db73e
MD		 229 #interrupt-cells = <2>;
230 interrupt-controller;
231 reg = <0 0xe61c0000 0 0x200>;
5f75e73c
LP		 232 interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>,
233 <0 1 IRQ_TYPE_LEVEL_HIGH>,
234 <0 2 IRQ_TYPE_LEVEL_HIGH>,
235 <0 3 IRQ_TYPE_LEVEL_HIGH>,
236 <0 12 IRQ_TYPE_LEVEL_HIGH>,
237 <0 13 IRQ_TYPE_LEVEL_HIGH>,
238 <0 14 IRQ_TYPE_LEVEL_HIGH>,
239 <0 15 IRQ_TYPE_LEVEL_HIGH>,
240 <0 16 IRQ_TYPE_LEVEL_HIGH>,
241 <0 17 IRQ_TYPE_LEVEL_HIGH>;
d77db73e 242 };
55146927 243
fde8feef
LP		 244 dmac0: dma-controller@e6700000 {
245 compatible = "renesas,rcar-dmac";
246 reg = <0 0xe6700000 0 0x20000>;
247 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
248 0 200 IRQ_TYPE_LEVEL_HIGH
249 0 201 IRQ_TYPE_LEVEL_HIGH
250 0 202 IRQ_TYPE_LEVEL_HIGH
251 0 203 IRQ_TYPE_LEVEL_HIGH
252 0 204 IRQ_TYPE_LEVEL_HIGH
253 0 205 IRQ_TYPE_LEVEL_HIGH
254 0 206 IRQ_TYPE_LEVEL_HIGH
255 0 207 IRQ_TYPE_LEVEL_HIGH
256 0 208 IRQ_TYPE_LEVEL_HIGH
257 0 209 IRQ_TYPE_LEVEL_HIGH
258 0 210 IRQ_TYPE_LEVEL_HIGH
259 0 211 IRQ_TYPE_LEVEL_HIGH
260 0 212 IRQ_TYPE_LEVEL_HIGH
261 0 213 IRQ_TYPE_LEVEL_HIGH
262 0 214 IRQ_TYPE_LEVEL_HIGH>;
263 interrupt-names = "error",
264 "ch0", "ch1", "ch2", "ch3",
265 "ch4", "ch5", "ch6", "ch7",
266 "ch8", "ch9", "ch10", "ch11",
267 "ch12", "ch13", "ch14";
268 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC0>;
269 clock-names = "fck";
270 #dma-cells = <1>;
271 dma-channels = <15>;
272 };
273
274 dmac1: dma-controller@e6720000 {
275 compatible = "renesas,rcar-dmac";
276 reg = <0 0xe6720000 0 0x20000>;
277 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
278 0 216 IRQ_TYPE_LEVEL_HIGH
279 0 217 IRQ_TYPE_LEVEL_HIGH
280 0 218 IRQ_TYPE_LEVEL_HIGH
281 0 219 IRQ_TYPE_LEVEL_HIGH
282 0 308 IRQ_TYPE_LEVEL_HIGH
283 0 309 IRQ_TYPE_LEVEL_HIGH
284 0 310 IRQ_TYPE_LEVEL_HIGH
285 0 311 IRQ_TYPE_LEVEL_HIGH
286 0 312 IRQ_TYPE_LEVEL_HIGH
287 0 313 IRQ_TYPE_LEVEL_HIGH
288 0 314 IRQ_TYPE_LEVEL_HIGH
289 0 315 IRQ_TYPE_LEVEL_HIGH
290 0 316 IRQ_TYPE_LEVEL_HIGH
291 0 317 IRQ_TYPE_LEVEL_HIGH
292 0 318 IRQ_TYPE_LEVEL_HIGH>;
293 interrupt-names = "error",
294 "ch0", "ch1", "ch2", "ch3",
295 "ch4", "ch5", "ch6", "ch7",
296 "ch8", "ch9", "ch10", "ch11",
297 "ch12", "ch13", "ch14";
298 clocks = <&mstp2_clks R8A7791_CLK_SYS_DMAC1>;
299 clock-names = "fck";
300 #dma-cells = <1>;
301 dma-channels = <15>;
302 };
303
8994fff6
KM		 304 audma0: dma-controller@ec700000 {
305 compatible = "renesas,rcar-dmac";
306 reg = <0 0xec700000 0 0x10000>;
307 interrupts = <0 346 IRQ_TYPE_LEVEL_HIGH
308 0 320 IRQ_TYPE_LEVEL_HIGH
309 0 321 IRQ_TYPE_LEVEL_HIGH
310 0 322 IRQ_TYPE_LEVEL_HIGH
311 0 323 IRQ_TYPE_LEVEL_HIGH
312 0 324 IRQ_TYPE_LEVEL_HIGH
313 0 325 IRQ_TYPE_LEVEL_HIGH
314 0 326 IRQ_TYPE_LEVEL_HIGH
315 0 327 IRQ_TYPE_LEVEL_HIGH
316 0 328 IRQ_TYPE_LEVEL_HIGH
317 0 329 IRQ_TYPE_LEVEL_HIGH
318 0 330 IRQ_TYPE_LEVEL_HIGH
319 0 331 IRQ_TYPE_LEVEL_HIGH
320 0 332 IRQ_TYPE_LEVEL_HIGH>;
321 interrupt-names = "error",
322 "ch0", "ch1", "ch2", "ch3",
323 "ch4", "ch5", "ch6", "ch7",
324 "ch8", "ch9", "ch10", "ch11",
325 "ch12";
326 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC0>;
327 clock-names = "fck";
328 #dma-cells = <1>;
329 dma-channels = <13>;
330 };
331
332 audma1: dma-controller@ec720000 {
333 compatible = "renesas,rcar-dmac";
334 reg = <0 0xec720000 0 0x10000>;
335 interrupts = <0 347 IRQ_TYPE_LEVEL_HIGH
336 0 333 IRQ_TYPE_LEVEL_HIGH
337 0 334 IRQ_TYPE_LEVEL_HIGH
338 0 335 IRQ_TYPE_LEVEL_HIGH
339 0 336 IRQ_TYPE_LEVEL_HIGH
340 0 337 IRQ_TYPE_LEVEL_HIGH
341 0 338 IRQ_TYPE_LEVEL_HIGH
342 0 339 IRQ_TYPE_LEVEL_HIGH
343 0 340 IRQ_TYPE_LEVEL_HIGH
344 0 341 IRQ_TYPE_LEVEL_HIGH
345 0 342 IRQ_TYPE_LEVEL_HIGH
346 0 343 IRQ_TYPE_LEVEL_HIGH
347 0 344 IRQ_TYPE_LEVEL_HIGH
348 0 345 IRQ_TYPE_LEVEL_HIGH>;
349 interrupt-names = "error",
350 "ch0", "ch1", "ch2", "ch3",
351 "ch4", "ch5", "ch6", "ch7",
352 "ch8", "ch9", "ch10", "ch11",
353 "ch12";
354 clocks = <&mstp5_clks R8A7791_CLK_AUDIO_DMAC1>;
355 clock-names = "fck";
356 #dma-cells = <1>;
357 dma-channels = <13>;
358 };
359
40c6d9f0
KM		 360 audmapp: dma-controller@ec740000 {
361 compatible = "renesas,rcar-audmapp";
362 #dma-cells = <1>;
363
364 reg = <0 0xec740000 0 0x200>;
365 };
366
36408d9d 367 /* The memory map in the User's Manual maps the cores to bus numbers */
5bd3de7b
WS		 368 i2c0: i2c@e6508000 {
369 #address-cells = <1>;
370 #size-cells = <0>;
371 compatible = "renesas,i2c-r8a7791";
372 reg = <0 0xe6508000 0 0x40>;
373 interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
374 clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
375 status = "disabled";
376 };
377
378 i2c1: i2c@e6518000 {
379 #address-cells = <1>;
380 #size-cells = <0>;
381 compatible = "renesas,i2c-r8a7791";
382 reg = <0 0xe6518000 0 0x40>;
383 interrupts = <0 288 IRQ_TYPE_LEVEL_HIGH>;
384 clocks = <&mstp9_clks R8A7791_CLK_I2C1>;
385 status = "disabled";
386 };
387
388 i2c2: i2c@e6530000 {
389 #address-cells = <1>;
390 #size-cells = <0>;
391 compatible = "renesas,i2c-r8a7791";
392 reg = <0 0xe6530000 0 0x40>;
393 interrupts = <0 286 IRQ_TYPE_LEVEL_HIGH>;
394 clocks = <&mstp9_clks R8A7791_CLK_I2C2>;
395 status = "disabled";
396 };
397
398 i2c3: i2c@e6540000 {
399 #address-cells = <1>;
400 #size-cells = <0>;
401 compatible = "renesas,i2c-r8a7791";
402 reg = <0 0xe6540000 0 0x40>;
403 interrupts = <0 290 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&mstp9_clks R8A7791_CLK_I2C3>;
405 status = "disabled";
406 };
407
408 i2c4: i2c@e6520000 {
409 #address-cells = <1>;
410 #size-cells = <0>;
411 compatible = "renesas,i2c-r8a7791";
412 reg = <0 0xe6520000 0 0x40>;
413 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
414 clocks = <&mstp9_clks R8A7791_CLK_I2C4>;
415 status = "disabled";
416 };
417
418 i2c5: i2c@e6528000 {
36408d9d 419 /* doesn't need pinmux */
5bd3de7b
WS		 420 #address-cells = <1>;
421 #size-cells = <0>;
422 compatible = "renesas,i2c-r8a7791";
423 reg = <0 0xe6528000 0 0x40>;
424 interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
425 clocks = <&mstp9_clks R8A7791_CLK_I2C5>;
426 status = "disabled";
427 };
428
36408d9d
WS		 429 i2c6: i2c@e60b0000 {
430 /* doesn't need pinmux */
431 #address-cells = <1>;
432 #size-cells = <0>;
433 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
434 reg = <0 0xe60b0000 0 0x425>;
435 interrupts = <0 173 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&mstp9_clks R8A7791_CLK_IICDVFS>;
3f58c54b
WS		 437 dmas = <&dmac0 0x77>, <&dmac0 0x78>;
438 dma-names = "tx", "rx";
36408d9d
WS		 439 status = "disabled";
440 };
441
442 i2c7: i2c@e6500000 {
443 #address-cells = <1>;
444 #size-cells = <0>;
445 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
446 reg = <0 0xe6500000 0 0x425>;
447 interrupts = <0 174 IRQ_TYPE_LEVEL_HIGH>;
448 clocks = <&mstp3_clks R8A7791_CLK_IIC0>;
3f58c54b
WS		 449 dmas = <&dmac0 0x61>, <&dmac0 0x62>;
450 dma-names = "tx", "rx";
36408d9d
WS		 451 status = "disabled";
452 };
453
454 i2c8: i2c@e6510000 {
455 #address-cells = <1>;
456 #size-cells = <0>;
457 compatible = "renesas,iic-r8a7791", "renesas,rmobile-iic";
458 reg = <0 0xe6510000 0 0x425>;
459 interrupts = <0 175 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&mstp3_clks R8A7791_CLK_IIC1>;
3f58c54b
WS		 461 dmas = <&dmac0 0x65>, <&dmac0 0x66>;
462 dma-names = "tx", "rx";
36408d9d
WS		 463 status = "disabled";
464 };
465
55146927
MD		 466 pfc: pfc@e6060000 {
467 compatible = "renesas,pfc-r8a7791";
468 reg = <0 0xe6060000 0 0x250>;
469 #gpio-range-cells = <3>;
470 };
59e79895 471
8edae499
LP		 472 mmcif0: mmc@ee200000 {
473 compatible = "renesas,mmcif-r8a7791", "renesas,sh-mmcif";
474 reg = <0 0xee200000 0 0x80>;
475 interrupts = <0 169 IRQ_TYPE_LEVEL_HIGH>;
476 clocks = <&mstp3_clks R8A7791_CLK_MMCIF0>;
16b355b4
LP		 477 dmas = <&dmac0 0xd1>, <&dmac0 0xd2>;
478 dma-names = "tx", "rx";
8edae499
LP		 479 reg-io-width = <4>;
480 status = "disabled";
481 };
482
b7ed8a0d
MD		 483 sdhi0: sd@ee100000 {
484 compatible = "renesas,sdhi-r8a7791";
485 reg = <0 0xee100000 0 0x200>;
b7ed8a0d
MD		 486 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
487 clocks = <&mstp3_clks R8A7791_CLK_SDHI0>;
ae67fa2f
LP		 488 dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
489 dma-names = "tx", "rx";
b7ed8a0d
MD		 490 status = "disabled";
491 };
492
493 sdhi1: sd@ee140000 {
494 compatible = "renesas,sdhi-r8a7791";
495 reg = <0 0xee140000 0 0x100>;
b7ed8a0d
MD		 496 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
497 clocks = <&mstp3_clks R8A7791_CLK_SDHI1>;
ae67fa2f
LP		 498 dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
499 dma-names = "tx", "rx";
b7ed8a0d
MD		 500 status = "disabled";
501 };
502
503 sdhi2: sd@ee160000 {
504 compatible = "renesas,sdhi-r8a7791";
505 reg = <0 0xee160000 0 0x100>;
b7ed8a0d
MD		 506 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
507 clocks = <&mstp3_clks R8A7791_CLK_SDHI2>;
ae67fa2f
LP		 508 dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
509 dma-names = "tx", "rx";
b7ed8a0d
MD		 510 status = "disabled";
511 };
512
9640cf25
LP		 513 scifa0: serial@e6c40000 {
514 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
515 reg = <0 0xe6c40000 0 64>;
9640cf25
LP		 516 interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
517 clocks = <&mstp2_clks R8A7791_CLK_SCIFA0>;
518 clock-names = "sci_ick";
519 status = "disabled";
520 };
521
522 scifa1: serial@e6c50000 {
523 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 524 reg = <0 0xe6c50000 0 64>;
525 interrupts = <0 145 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&mstp2_clks R8A7791_CLK_SCIFA1>;
527 clock-names = "sci_ick";
528 status = "disabled";
529 };
530
531 scifa2: serial@e6c60000 {
532 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 533 reg = <0 0xe6c60000 0 64>;
534 interrupts = <0 151 IRQ_TYPE_LEVEL_HIGH>;
535 clocks = <&mstp2_clks R8A7791_CLK_SCIFA2>;
536 clock-names = "sci_ick";
537 status = "disabled";
538 };
539
540 scifa3: serial@e6c70000 {
541 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 542 reg = <0 0xe6c70000 0 64>;
543 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>;
544 clocks = <&mstp11_clks R8A7791_CLK_SCIFA3>;
545 clock-names = "sci_ick";
546 status = "disabled";
547 };
548
549 scifa4: serial@e6c78000 {
550 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 551 reg = <0 0xe6c78000 0 64>;
552 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>;
553 clocks = <&mstp11_clks R8A7791_CLK_SCIFA4>;
554 clock-names = "sci_ick";
555 status = "disabled";
556 };
557
558 scifa5: serial@e6c80000 {
559 compatible = "renesas,scifa-r8a7791", "renesas,scifa";
9640cf25
LP		 560 reg = <0 0xe6c80000 0 64>;
561 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
562 clocks = <&mstp11_clks R8A7791_CLK_SCIFA5>;
563 clock-names = "sci_ick";
564 status = "disabled";
565 };
566
567 scifb0: serial@e6c20000 {
568 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 569 reg = <0 0xe6c20000 0 64>;
570 interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>;
571 clocks = <&mstp2_clks R8A7791_CLK_SCIFB0>;
572 clock-names = "sci_ick";
573 status = "disabled";
574 };
575
576 scifb1: serial@e6c30000 {
577 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 578 reg = <0 0xe6c30000 0 64>;
579 interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&mstp2_clks R8A7791_CLK_SCIFB1>;
581 clock-names = "sci_ick";
582 status = "disabled";
583 };
584
585 scifb2: serial@e6ce0000 {
586 compatible = "renesas,scifb-r8a7791", "renesas,scifb";
9640cf25
LP		 587 reg = <0 0xe6ce0000 0 64>;
588 interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>;
589 clocks = <&mstp2_clks R8A7791_CLK_SCIFB2>;
590 clock-names = "sci_ick";
591 status = "disabled";
592 };
593
594 scif0: serial@e6e60000 {
595 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 596 reg = <0 0xe6e60000 0 64>;
597 interrupts = <0 152 IRQ_TYPE_LEVEL_HIGH>;
598 clocks = <&mstp7_clks R8A7791_CLK_SCIF0>;
599 clock-names = "sci_ick";
600 status = "disabled";
601 };
602
603 scif1: serial@e6e68000 {
604 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 605 reg = <0 0xe6e68000 0 64>;
606 interrupts = <0 153 IRQ_TYPE_LEVEL_HIGH>;
607 clocks = <&mstp7_clks R8A7791_CLK_SCIF1>;
608 clock-names = "sci_ick";
609 status = "disabled";
610 };
611
612 scif2: serial@e6e58000 {
613 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 614 reg = <0 0xe6e58000 0 64>;
615 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
616 clocks = <&mstp7_clks R8A7791_CLK_SCIF2>;
617 clock-names = "sci_ick";
618 status = "disabled";
619 };
620
621 scif3: serial@e6ea8000 {
622 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 623 reg = <0 0xe6ea8000 0 64>;
624 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
625 clocks = <&mstp7_clks R8A7791_CLK_SCIF3>;
626 clock-names = "sci_ick";
627 status = "disabled";
628 };
629
630 scif4: serial@e6ee0000 {
631 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 632 reg = <0 0xe6ee0000 0 64>;
633 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&mstp7_clks R8A7791_CLK_SCIF4>;
635 clock-names = "sci_ick";
636 status = "disabled";
637 };
638
639 scif5: serial@e6ee8000 {
640 compatible = "renesas,scif-r8a7791", "renesas,scif";
9640cf25
LP		 641 reg = <0 0xe6ee8000 0 64>;
642 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
643 clocks = <&mstp7_clks R8A7791_CLK_SCIF5>;
644 clock-names = "sci_ick";
645 status = "disabled";
646 };
647
648 hscif0: serial@e62c0000 {
649 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 650 reg = <0 0xe62c0000 0 96>;
651 interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
652 clocks = <&mstp7_clks R8A7791_CLK_HSCIF0>;
653 clock-names = "sci_ick";
654 status = "disabled";
655 };
656
657 hscif1: serial@e62c8000 {
658 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 659 reg = <0 0xe62c8000 0 96>;
660 interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&mstp7_clks R8A7791_CLK_HSCIF1>;
662 clock-names = "sci_ick";
663 status = "disabled";
664 };
665
666 hscif2: serial@e62d0000 {
667 compatible = "renesas,hscif-r8a7791", "renesas,hscif";
9640cf25
LP		 668 reg = <0 0xe62d0000 0 96>;
669 interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&mstp7_clks R8A7791_CLK_HSCIF2>;
671 clock-names = "sci_ick";
672 status = "disabled";
673 };
674
2e5d55ce
SS		 675 ether: ethernet@ee700000 {
676 compatible = "renesas,ether-r8a7791";
677 reg = <0 0xee700000 0 0x400>;
678 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&mstp8_clks R8A7791_CLK_ETHER>;
680 phy-mode = "rmii";
681 #address-cells = <1>;
682 #size-cells = <0>;
683 status = "disabled";
684 };
685
b8532c69
VB		 686 sata0: sata@ee300000 {
687 compatible = "renesas,sata-r8a7791";
688 reg = <0 0xee300000 0 0x2000>;
b8532c69
VB		 689 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
690 clocks = <&mstp8_clks R8A7791_CLK_SATA0>;
691 status = "disabled";
692 };
693
694 sata1: sata@ee500000 {
695 compatible = "renesas,sata-r8a7791";
696 reg = <0 0xee500000 0 0x2000>;
b8532c69
VB		 697 interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&mstp8_clks R8A7791_CLK_SATA1>;
699 status = "disabled";
700 };
701
1c1fee7c
YS		 702 hsusb: usb@e6590000 {
703 compatible = "renesas,usbhs-r8a7791";
704 reg = <0 0xe6590000 0 0x100>;
705 interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
706 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
707 renesas,buswait = <4>;
708 phys = <&usb0 1>;
709 phy-names = "usb";
710 status = "disabled";
711 };
712
3b7e530d
SS		 713 usbphy: usb-phy@e6590100 {
714 compatible = "renesas,usb-phy-r8a7791";
715 reg = <0 0xe6590100 0 0x100>;
716 #address-cells = <1>;
717 #size-cells = <0>;
718 clocks = <&mstp7_clks R8A7791_CLK_HSUSB>;
719 clock-names = "usbhs";
720 status = "disabled";
721
722 usb0: usb-channel@0 {
723 reg = <0>;
724 #phy-cells = <1>;
725 };
726 usb2: usb-channel@2 {
727 reg = <2>;
728 #phy-cells = <1>;
729 };
730 };
731
0b8d1d57
SS		 732 vin0: video@e6ef0000 {
733 compatible = "renesas,vin-r8a7791";
734 clocks = <&mstp8_clks R8A7791_CLK_VIN0>;
735 reg = <0 0xe6ef0000 0 0x1000>;
736 interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
737 status = "disabled";
738 };
739
740 vin1: video@e6ef1000 {
741 compatible = "renesas,vin-r8a7791";
742 clocks = <&mstp8_clks R8A7791_CLK_VIN1>;
743 reg = <0 0xe6ef1000 0 0x1000>;
744 interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
745 status = "disabled";
746 };
747
748 vin2: video@e6ef2000 {
749 compatible = "renesas,vin-r8a7791";
750 clocks = <&mstp8_clks R8A7791_CLK_VIN2>;
751 reg = <0 0xe6ef2000 0 0x1000>;
752 interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
753 status = "disabled";
754 };
755
8eefac2d
LP		 756 vsp1@fe928000 {
757 compatible = "renesas,vsp1";
758 reg = <0 0xfe928000 0 0x8000>;
759 interrupts = <0 267 IRQ_TYPE_LEVEL_HIGH>;
760 clocks = <&mstp1_clks R8A7791_CLK_VSP1_S>;
761
762 renesas,has-lut;
763 renesas,has-sru;
764 renesas,#rpf = <5>;
765 renesas,#uds = <3>;
766 renesas,#wpf = <4>;
767 };
768
769 vsp1@fe930000 {
770 compatible = "renesas,vsp1";
771 reg = <0 0xfe930000 0 0x8000>;
772 interrupts = <0 246 IRQ_TYPE_LEVEL_HIGH>;
773 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU0>;
774
775 renesas,has-lif;
776 renesas,has-lut;
777 renesas,#rpf = <4>;
778 renesas,#uds = <1>;
779 renesas,#wpf = <4>;
780 };
781
782 vsp1@fe938000 {
783 compatible = "renesas,vsp1";
784 reg = <0 0xfe938000 0 0x8000>;
785 interrupts = <0 247 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&mstp1_clks R8A7791_CLK_VSP1_DU1>;
787
788 renesas,has-lif;
789 renesas,has-lut;
790 renesas,#rpf = <4>;
791 renesas,#uds = <1>;
792 renesas,#wpf = <4>;
793 };
794
795 du: display@feb00000 {
796 compatible = "renesas,du-r8a7791";
797 reg = <0 0xfeb00000 0 0x40000>,
798 <0 0xfeb90000 0 0x1c>;
799 reg-names = "du", "lvds.0";
800 interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
801 <0 268 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&mstp7_clks R8A7791_CLK_DU0>,
803 <&mstp7_clks R8A7791_CLK_DU1>,
804 <&mstp7_clks R8A7791_CLK_LVDS0>;
805 clock-names = "du.0", "du.1", "lvds.0";
806 status = "disabled";
807
808 ports {
809 #address-cells = <1>;
810 #size-cells = <0>;
811
812 port@0 {
813 reg = <0>;
814 du_out_rgb: endpoint {
815 };
816 };
817 port@1 {
818 reg = <1>;
819 du_out_lvds0: endpoint {
820 };
821 };
822 };
823 };
824
3cf01884
SS		 825 can0: can@e6e80000 {
826 compatible = "renesas,can-r8a7791";
827 reg = <0 0xe6e80000 0 0x1000>;
828 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
830 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
831 clock-names = "clkp1", "clkp2", "can_clk";
832 status = "disabled";
833 };
834
835 can1: can@e6e88000 {
836 compatible = "renesas,can-r8a7791";
837 reg = <0 0xe6e88000 0 0x1000>;
838 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
839 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
840 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
841 clock-names = "clkp1", "clkp2", "can_clk";
842 status = "disabled";
843 };
844
59e79895
LP		 845 clocks {
846 #address-cells = <2>;
847 #size-cells = <2>;
848 ranges;
849
850 /* External root clock */
851 extal_clk: extal_clk {
852 compatible = "fixed-clock";
853 #clock-cells = <0>;
854 /* This value must be overriden by the board. */
855 clock-frequency = <0>;
856 clock-output-names = "extal";
857 };
858
0d3dbde8
KM		 859 /*
860 * The external audio clocks are configured as 0 Hz fixed frequency clocks by
861 * default. Boards that provide audio clocks should override them.
862 */
863 audio_clk_a: audio_clk_a {
864 compatible = "fixed-clock";
865 #clock-cells = <0>;
866 clock-frequency = <0>;
867 clock-output-names = "audio_clk_a";
868 };
869 audio_clk_b: audio_clk_b {
870 compatible = "fixed-clock";
871 #clock-cells = <0>;
872 clock-frequency = <0>;
873 clock-output-names = "audio_clk_b";
874 };
875 audio_clk_c: audio_clk_c {
876 compatible = "fixed-clock";
877 #clock-cells = <0>;
878 clock-frequency = <0>;
879 clock-output-names = "audio_clk_c";
880 };
881
66c405e7
PE		 882 /* External PCIe clock - can be overridden by the board */
883 pcie_bus_clk: pcie_bus_clk {
884 compatible = "fixed-clock";
885 #clock-cells = <0>;
886 clock-frequency = <100000000>;
887 clock-output-names = "pcie_bus";
888 status = "disabled";
889 };
890
b324252c
SS		 891 /* External USB clock - can be overridden by the board */
892 usb_extal_clk: usb_extal_clk {
893 compatible = "fixed-clock";
894 #clock-cells = <0>;
895 clock-frequency = <48000000>;
896 clock-output-names = "usb_extal";
897 };
898
899 /* External CAN clock */
900 can_clk: can_clk {
901 compatible = "fixed-clock";
902 #clock-cells = <0>;
903 /* This value must be overridden by the board. */
904 clock-frequency = <0>;
905 clock-output-names = "can_clk";
906 status = "disabled";
907 };
908
59e79895
LP		 909 /* Special CPG clocks */
910 cpg_clocks: cpg_clocks@e6150000 {
911 compatible = "renesas,r8a7791-cpg-clocks",
912 "renesas,rcar-gen2-cpg-clocks";
913 reg = <0 0xe6150000 0 0x1000>;
b324252c 914 clocks = <&extal_clk &usb_extal_clk>;
59e79895
LP		 915 #clock-cells = <1>;
916 clock-output-names = "main", "pll0", "pll1", "pll3",
b324252c 917 "lb", "qspi", "sdh", "sd0", "z",
ae65a8ae 918 "rcan", "adsp";
59e79895
LP		 919 };
920
921 /* Variable factor clocks */
2ea0d4ec 922 sd2_clk: sd2_clk@e6150078 {
59e79895
LP		 923 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
924 reg = <0 0xe6150078 0 4>;
925 clocks = <&pll1_div2_clk>;
926 #clock-cells = <0>;
2ea0d4ec 927 clock-output-names = "sd2";
59e79895 928 };
2ea0d4ec 929 sd3_clk: sd3_clk@e615026c {
59e79895 930 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
c9b22772 931 reg = <0 0xe615026c 0 4>;
59e79895
LP		 932 clocks = <&pll1_div2_clk>;
933 #clock-cells = <0>;
2ea0d4ec 934 clock-output-names = "sd3";
59e79895
LP		 935 };
936 mmc0_clk: mmc0_clk@e6150240 {
937 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
938 reg = <0 0xe6150240 0 4>;
939 clocks = <&pll1_div2_clk>;
940 #clock-cells = <0>;
941 clock-output-names = "mmc0";
942 };
943 ssp_clk: ssp_clk@e6150248 {
944 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
945 reg = <0 0xe6150248 0 4>;
946 clocks = <&pll1_div2_clk>;
947 #clock-cells = <0>;
948 clock-output-names = "ssp";
949 };
950 ssprs_clk: ssprs_clk@e615024c {
951 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
952 reg = <0 0xe615024c 0 4>;
953 clocks = <&pll1_div2_clk>;
954 #clock-cells = <0>;
955 clock-output-names = "ssprs";
956 };
957
958 /* Fixed factor clocks */
959 pll1_div2_clk: pll1_div2_clk {
960 compatible = "fixed-factor-clock";
961 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
962 #clock-cells = <0>;
963 clock-div = <2>;
964 clock-mult = <1>;
965 clock-output-names = "pll1_div2";
966 };
967 zg_clk: zg_clk {
968 compatible = "fixed-factor-clock";
969 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
970 #clock-cells = <0>;
971 clock-div = <3>;
972 clock-mult = <1>;
973 clock-output-names = "zg";
974 };
975 zx_clk: zx_clk {
976 compatible = "fixed-factor-clock";
977 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
978 #clock-cells = <0>;
979 clock-div = <3>;
980 clock-mult = <1>;
981 clock-output-names = "zx";
982 };
983 zs_clk: zs_clk {
984 compatible = "fixed-factor-clock";
985 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
986 #clock-cells = <0>;
987 clock-div = <6>;
988 clock-mult = <1>;
989 clock-output-names = "zs";
990 };
991 hp_clk: hp_clk {
992 compatible = "fixed-factor-clock";
993 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
994 #clock-cells = <0>;
995 clock-div = <12>;
996 clock-mult = <1>;
997 clock-output-names = "hp";
998 };
999 i_clk: i_clk {
1000 compatible = "fixed-factor-clock";
1001 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1002 #clock-cells = <0>;
1003 clock-div = <2>;
1004 clock-mult = <1>;
1005 clock-output-names = "i";
1006 };
1007 b_clk: b_clk {
1008 compatible = "fixed-factor-clock";
1009 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1010 #clock-cells = <0>;
1011 clock-div = <12>;
1012 clock-mult = <1>;
1013 clock-output-names = "b";
1014 };
1015 p_clk: p_clk {
1016 compatible = "fixed-factor-clock";
1017 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1018 #clock-cells = <0>;
1019 clock-div = <24>;
1020 clock-mult = <1>;
1021 clock-output-names = "p";
1022 };
1023 cl_clk: cl_clk {
1024 compatible = "fixed-factor-clock";
1025 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1026 #clock-cells = <0>;
1027 clock-div = <48>;
1028 clock-mult = <1>;
1029 clock-output-names = "cl";
1030 };
1031 m2_clk: m2_clk {
1032 compatible = "fixed-factor-clock";
1033 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1034 #clock-cells = <0>;
1035 clock-div = <8>;
1036 clock-mult = <1>;
1037 clock-output-names = "m2";
1038 };
1039 imp_clk: imp_clk {
1040 compatible = "fixed-factor-clock";
1041 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1042 #clock-cells = <0>;
1043 clock-div = <4>;
1044 clock-mult = <1>;
1045 clock-output-names = "imp";
1046 };
1047 rclk_clk: rclk_clk {
1048 compatible = "fixed-factor-clock";
1049 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1050 #clock-cells = <0>;
1051 clock-div = <(48 * 1024)>;
1052 clock-mult = <1>;
1053 clock-output-names = "rclk";
1054 };
1055 oscclk_clk: oscclk_clk {
1056 compatible = "fixed-factor-clock";
1057 clocks = <&cpg_clocks R8A7791_CLK_PLL1>;
1058 #clock-cells = <0>;
1059 clock-div = <(12 * 1024)>;
1060 clock-mult = <1>;
1061 clock-output-names = "oscclk";
1062 };
1063 zb3_clk: zb3_clk {
1064 compatible = "fixed-factor-clock";
1065 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1066 #clock-cells = <0>;
1067 clock-div = <4>;
1068 clock-mult = <1>;
1069 clock-output-names = "zb3";
1070 };
1071 zb3d2_clk: zb3d2_clk {
1072 compatible = "fixed-factor-clock";
1073 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1074 #clock-cells = <0>;
1075 clock-div = <8>;
1076 clock-mult = <1>;
1077 clock-output-names = "zb3d2";
1078 };
1079 ddr_clk: ddr_clk {
1080 compatible = "fixed-factor-clock";
1081 clocks = <&cpg_clocks R8A7791_CLK_PLL3>;
1082 #clock-cells = <0>;
1083 clock-div = <8>;
1084 clock-mult = <1>;
1085 clock-output-names = "ddr";
1086 };
1087 mp_clk: mp_clk {
1088 compatible = "fixed-factor-clock";
1089 clocks = <&pll1_div2_clk>;
1090 #clock-cells = <0>;
1091 clock-div = <15>;
1092 clock-mult = <1>;
1093 clock-output-names = "mp";
1094 };
1095 cp_clk: cp_clk {
1096 compatible = "fixed-factor-clock";
1097 clocks = <&extal_clk>;
1098 #clock-cells = <0>;
1099 clock-div = <2>;
1100 clock-mult = <1>;
1101 clock-output-names = "cp";
1102 };
1103
1104 /* Gate clocks */
cded80f8
LP		 1105 mstp0_clks: mstp0_clks@e6150130 {
1106 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1107 reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
1108 clocks = <&mp_clk>;
1109 #clock-cells = <1>;
cb0bf851 1110 clock-indices = <R8A7791_CLK_MSIOF0>;
cded80f8
LP		 1111 clock-output-names = "msiof0";
1112 };
59e79895
LP		 1113 mstp1_clks: mstp1_clks@e6150134 {
1114 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1115 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
74d89d25
YH		 1116 clocks = <&zs_clk>, <&zs_clk>, <&m2_clk>, <&zs_clk>, <&p_clk>,
1117 <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
1118 <&p_clk>, <&rclk_clk>, <&cp_clk>, <&zs_clk>, <&zs_clk>,
1119 <&zs_clk>;
59e79895 1120 #clock-cells = <1>;
cb0bf851 1121 clock-indices = <
74d89d25
YH		 1122 R8A7791_CLK_VCP0 R8A7791_CLK_VPC0 R8A7791_CLK_JPU
1123 R8A7791_CLK_SSP1 R8A7791_CLK_TMU1 R8A7791_CLK_3DG
1124 R8A7791_CLK_2DDMAC R8A7791_CLK_FDP1_1 R8A7791_CLK_FDP1_0
1125 R8A7791_CLK_TMU3 R8A7791_CLK_TMU2 R8A7791_CLK_CMT0
1126 R8A7791_CLK_TMU0 R8A7791_CLK_VSP1_DU1 R8A7791_CLK_VSP1_DU0
1127 R8A7791_CLK_VSP1_S
59e79895
LP		 1128 >;
1129 clock-output-names =
74d89d25
YH		 1130 "vcp0", "vpc0", "jpu", "ssp1", "tmu1", "3dg",
1131 "2ddmac", "fdp1-1", "fdp1-0", "tmu3", "tmu2", "cmt0",
1132 "tmu0", "vsp1-du1", "vsp1-du0", "vsp1-sy";
59e79895
LP		 1133 };
1134 mstp2_clks: mstp2_clks@e6150138 {
1135 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1136 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
1137 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
4e074bc8
GU		 1138 <&mp_clk>, <&mp_clk>, <&mp_clk>,
1139 <&zs_clk>, <&zs_clk>;
59e79895 1140 #clock-cells = <1>;
cb0bf851 1141 clock-indices = <
59e79895 1142 R8A7791_CLK_SCIFA2 R8A7791_CLK_SCIFA1 R8A7791_CLK_SCIFA0
cded80f8
LP		 1143 R8A7791_CLK_MSIOF2 R8A7791_CLK_SCIFB0 R8A7791_CLK_SCIFB1
1144 R8A7791_CLK_MSIOF1 R8A7791_CLK_SCIFB2
4e074bc8 1145 R8A7791_CLK_SYS_DMAC1 R8A7791_CLK_SYS_DMAC0
59e79895
LP		 1146 >;
1147 clock-output-names =
0c002ef8 1148 "scifa2", "scifa1", "scifa0", "msiof2", "scifb0",
4e074bc8
GU		 1149 "scifb1", "msiof1", "scifb2",
1150 "sys-dmac1", "sys-dmac0";
59e79895
LP		 1151 };
1152 mstp3_clks: mstp3_clks@e615013c {
1153 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1154 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
2ea0d4ec 1155 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
b9473d9f
YS		 1156 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1157 <&hp_clk>, <&hp_clk>;
59e79895 1158 #clock-cells = <1>;
cb0bf851 1159 clock-indices = <
c08691b5 1160 R8A7791_CLK_TPU0 R8A7791_CLK_SDHI2 R8A7791_CLK_SDHI1 R8A7791_CLK_SDHI0
4bfb3767
PE		 1161 R8A7791_CLK_MMCIF0 R8A7791_CLK_IIC0 R8A7791_CLK_PCIEC R8A7791_CLK_IIC1
1162 R8A7791_CLK_SSUSB R8A7791_CLK_CMT1
b9473d9f 1163 R8A7791_CLK_USBDMAC0 R8A7791_CLK_USBDMAC1
59e79895
LP		 1164 >;
1165 clock-output-names =
c08691b5 1166 "tpu0", "sdhi2", "sdhi1", "sdhi0",
b9473d9f
YS		 1167 "mmcif0", "i2c7", "pciec", "i2c8", "ssusb", "cmt1",
1168 "usbdmac0", "usbdmac1";
59e79895
LP		 1169 };
1170 mstp5_clks: mstp5_clks@e6150144 {
1171 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1172 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
ae65a8ae
SS		 1173 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1174 <&extal_clk>, <&p_clk>;
59e79895 1175 #clock-cells = <1>;
cb0bf851
BD		 1176 clock-indices = <
1177 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
ae65a8ae
SS		 1178 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1179 R8A7791_CLK_PWM
cb0bf851 1180 >;
ae65a8ae
SS		 1181 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1182 "thermal", "pwm";
59e79895
LP		 1183 };
1184 mstp7_clks: mstp7_clks@e615014c {
1185 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1186 reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
6225b99a 1187 clocks = <&mp_clk>, <&mp_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, <&zs_clk>,
59e79895
LP		 1188 <&zs_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1189 <&zx_clk>, <&zx_clk>, <&zx_clk>;
1190 #clock-cells = <1>;
cb0bf851 1191 clock-indices = <
6225b99a 1192 R8A7791_CLK_EHCI R8A7791_CLK_HSUSB R8A7791_CLK_HSCIF2 R8A7791_CLK_SCIF5
59e79895
LP		 1193 R8A7791_CLK_SCIF4 R8A7791_CLK_HSCIF1 R8A7791_CLK_HSCIF0
1194 R8A7791_CLK_SCIF3 R8A7791_CLK_SCIF2 R8A7791_CLK_SCIF1
1195 R8A7791_CLK_SCIF0 R8A7791_CLK_DU1 R8A7791_CLK_DU0
1196 R8A7791_CLK_LVDS0
1197 >;
1198 clock-output-names =
6225b99a 1199 "ehci", "hsusb", "hscif2", "scif5", "scif4", "hscif1", "hscif0",
59e79895
LP		 1200 "scif3", "scif2", "scif1", "scif0", "du1", "du0", "lvds0";
1201 };
1202 mstp8_clks: mstp8_clks@e6150990 {
1203 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1204 reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
2fd4e094 1205 clocks = <&zg_clk>, <&hp_clk>, <&zg_clk>, <&zg_clk>,
7408d306 1206 <&zg_clk>, <&p_clk>, <&zs_clk>, <&zs_clk>;
59e79895 1207 #clock-cells = <1>;
cb0bf851 1208 clock-indices = <
7408d306 1209 R8A7791_CLK_IPMMU_SGX R8A7791_CLK_MLB
09c98346 1210 R8A7791_CLK_VIN2 R8A7791_CLK_VIN1 R8A7791_CLK_VIN0
65f05c38 1211 R8A7791_CLK_ETHER R8A7791_CLK_SATA1 R8A7791_CLK_SATA0
09c98346 1212 >;
65f05c38 1213 clock-output-names =
7408d306
AG		 1214 "ipmmu_sgx", "mlb", "vin2", "vin1", "vin0", "ether",
1215 "sata1", "sata0";
59e79895
LP		 1216 };
1217 mstp9_clks: mstp9_clks@e6150994 {
1218 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1219 reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
4faf9c5e
GU		 1220 clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1221 <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
1222 <&p_clk>, <&p_clk>, <&cpg_clocks R8A7791_CLK_QSPI>, <&hp_clk>,
11b48db9
LP		 1223 <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
1224 <&hp_clk>, <&hp_clk>;
59e79895 1225 #clock-cells = <1>;
cb0bf851 1226 clock-indices = <
4faf9c5e
GU		 1227 R8A7791_CLK_GPIO7 R8A7791_CLK_GPIO6 R8A7791_CLK_GPIO5 R8A7791_CLK_GPIO4
1228 R8A7791_CLK_GPIO3 R8A7791_CLK_GPIO2 R8A7791_CLK_GPIO1 R8A7791_CLK_GPIO0
c08691b5
WS		 1229 R8A7791_CLK_RCAN1 R8A7791_CLK_RCAN0 R8A7791_CLK_QSPI_MOD R8A7791_CLK_I2C5
1230 R8A7791_CLK_IICDVFS R8A7791_CLK_I2C4 R8A7791_CLK_I2C3 R8A7791_CLK_I2C2
1231 R8A7791_CLK_I2C1 R8A7791_CLK_I2C0
59e79895
LP		 1232 >;
1233 clock-output-names =
4faf9c5e
GU		 1234 "gpio7", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio1", "gpio0",
1235 "rcan1", "rcan0", "qspi_mod", "i2c5", "i2c6", "i2c4", "i2c3", "i2c2",
1236 "i2c1", "i2c0";
59e79895 1237 };
ee914152
KM		 1238 mstp10_clks: mstp10_clks@e6150998 {
1239 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1240 reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
1241 clocks = <&p_clk>,
1242 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1243 <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>,
1244 <&p_clk>,
1245 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1246 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1247 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1248 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1249 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>,
1250 <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>;
1251
1252 #clock-cells = <1>;
1253 clock-indices = <
1254 R8A7791_CLK_SSI_ALL
1255 R8A7791_CLK_SSI9 R8A7791_CLK_SSI8 R8A7791_CLK_SSI7 R8A7791_CLK_SSI6 R8A7791_CLK_SSI5
1256 R8A7791_CLK_SSI4 R8A7791_CLK_SSI3 R8A7791_CLK_SSI2 R8A7791_CLK_SSI1 R8A7791_CLK_SSI0
1257 R8A7791_CLK_SCU_ALL
1258 R8A7791_CLK_SCU_DVC1 R8A7791_CLK_SCU_DVC0
1259 R8A7791_CLK_SCU_SRC9 R8A7791_CLK_SCU_SRC8 R8A7791_CLK_SCU_SRC7 R8A7791_CLK_SCU_SRC6 R8A7791_CLK_SCU_SRC5
1260 R8A7791_CLK_SCU_SRC4 R8A7791_CLK_SCU_SRC3 R8A7791_CLK_SCU_SRC2 R8A7791_CLK_SCU_SRC1 R8A7791_CLK_SCU_SRC0
1261 >;
1262 clock-output-names =
1263 "ssi-all",
1264 "ssi9", "ssi8", "ssi7", "ssi6", "ssi5",
1265 "ssi4", "ssi3", "ssi2", "ssi1", "ssi0",
1266 "scu-all",
1267 "scu-dvc1", "scu-dvc0",
1268 "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5",
1269 "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0";
1270 };
59e79895
LP		 1271 mstp11_clks: mstp11_clks@e615099c {
1272 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1273 reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>;
1274 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>;
1275 #clock-cells = <1>;
cb0bf851 1276 clock-indices = <
59e79895
LP		 1277 R8A7791_CLK_SCIFA3 R8A7791_CLK_SCIFA4 R8A7791_CLK_SCIFA5
1278 >;
1279 clock-output-names = "scifa3", "scifa4", "scifa5";
1280 };
1281 };
4d5b59cd 1282
6f3e4ee3 1283 qspi: spi@e6b10000 {
4d5b59cd
GU		 1284 compatible = "renesas,qspi-r8a7791", "renesas,qspi";
1285 reg = <0 0xe6b10000 0 0x2c>;
4d5b59cd
GU		 1286 interrupts = <0 184 IRQ_TYPE_LEVEL_HIGH>;
1287 clocks = <&mstp9_clks R8A7791_CLK_QSPI_MOD>;
591f2fa4
GU		 1288 dmas = <&dmac0 0x17>, <&dmac0 0x18>;
1289 dma-names = "tx", "rx";
4d5b59cd
GU		 1290 num-cs = <1>;
1291 #address-cells = <1>;
1292 #size-cells = <0>;
1293 status = "disabled";
1294 };
7713d3ab
GU		 1295
1296 msiof0: spi@e6e20000 {
1297 compatible = "renesas,msiof-r8a7791";
a5ce27f5 1298 reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
7713d3ab
GU		 1299 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
1300 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
a5ce27f5
GU		 1301 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
1302 dma-names = "tx", "rx";
7713d3ab
GU		 1303 #address-cells = <1>;
1304 #size-cells = <0>;
1305 status = "disabled";
1306 };
1307
1308 msiof1: spi@e6e10000 {
1309 compatible = "renesas,msiof-r8a7791";
a5ce27f5 1310 reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
7713d3ab
GU		 1311 interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
1312 clocks = <&mstp2_clks R8A7791_CLK_MSIOF1>;
a5ce27f5
GU		 1313 dmas = <&dmac0 0x55>, <&dmac0 0x56>;
1314 dma-names = "tx", "rx";
7713d3ab
GU		 1315 #address-cells = <1>;
1316 #size-cells = <0>;
1317 status = "disabled";
1318 };
1319
1320 msiof2: spi@e6e00000 {
1321 compatible = "renesas,msiof-r8a7791";
a5ce27f5 1322 reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
7713d3ab
GU		 1323 interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
1324 clocks = <&mstp2_clks R8A7791_CLK_MSIOF2>;
a5ce27f5
GU		 1325 dmas = <&dmac0 0x41>, <&dmac0 0x42>;
1326 dma-names = "tx", "rx";
7713d3ab
GU		 1327 #address-cells = <1>;
1328 #size-cells = <0>;
1329 status = "disabled";
1330 };
811cdfae 1331
c196931e
YS		 1332 xhci: usb@ee000000 {
1333 compatible = "renesas,xhci-r8a7791";
1334 reg = <0 0xee000000 0 0xc00>;
1335 interrupts = <0 101 IRQ_TYPE_LEVEL_HIGH>;
1336 clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
1337 phys = <&usb2 1>;
1338 phy-names = "usb";
1339 status = "disabled";
1340 };
1341
aace0809
SS		 1342 pci0: pci@ee090000 {
1343 compatible = "renesas,pci-r8a7791";
1344 device_type = "pci";
1345 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1346 reg = <0 0xee090000 0 0xc00>,
1347 <0 0xee080000 0 0x1100>;
1348 interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
1349 status = "disabled";
1350
1351 bus-range = <0 0>;
1352 #address-cells = <3>;
1353 #size-cells = <2>;
1354 #interrupt-cells = <1>;
1355 ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>;
1356 interrupt-map-mask = <0xff00 0 0 0x7>;
1357 interrupt-map = <0x0000 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1358 0x0800 0 0 1 &gic 0 108 IRQ_TYPE_LEVEL_HIGH
1359 0x1000 0 0 2 &gic 0 108 IRQ_TYPE_LEVEL_HIGH>;
e1bce124
SS		 1360
1361 usb@0,1 {
1362 reg = <0x800 0 0 0 0>;
1363 device_type = "pci";
1364 phys = <&usb0 0>;
1365 phy-names = "usb";
1366 };
1367
1368 usb@0,2 {
1369 reg = <0x1000 0 0 0 0>;
1370 device_type = "pci";
1371 phys = <&usb0 0>;
1372 phy-names = "usb";
1373 };
aace0809
SS		 1374 };
1375
1376 pci1: pci@ee0d0000 {
1377 compatible = "renesas,pci-r8a7791";
1378 device_type = "pci";
1379 clocks = <&mstp7_clks R8A7791_CLK_EHCI>;
1380 reg = <0 0xee0d0000 0 0xc00>,
1381 <0 0xee0c0000 0 0x1100>;
1382 interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>;
1383 status = "disabled";
1384
1385 bus-range = <1 1>;
1386 #address-cells = <3>;
1387 #size-cells = <2>;
1388 #interrupt-cells = <1>;
1389 ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>;
1390 interrupt-map-mask = <0xff00 0 0 0x7>;
1391 interrupt-map = <0x0000 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1392 0x0800 0 0 1 &gic 0 113 IRQ_TYPE_LEVEL_HIGH
1393 0x1000 0 0 2 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
e1bce124
SS		 1394
1395 usb@0,1 {
1396 reg = <0x800 0 0 0 0>;
1397 device_type = "pci";
1398 phys = <&usb2 0>;
1399 phy-names = "usb";
1400 };
1401
1402 usb@0,2 {
1403 reg = <0x1000 0 0 0 0>;
1404 device_type = "pci";
1405 phys = <&usb2 0>;
1406 phy-names = "usb";
1407 };
aace0809
SS		 1408 };
1409
811cdfae
PE		 1410 pciec: pcie@fe000000 {
1411 compatible = "renesas,pcie-r8a7791";
1412 reg = <0 0xfe000000 0 0x80000>;
1413 #address-cells = <3>;
1414 #size-cells = <2>;
1415 bus-range = <0x00 0xff>;
1416 device_type = "pci";
1417 ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
1418 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
1419 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
1420 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
1421 /* Map all possible DDR as inbound ranges */
1422 dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000
1423 0x43000000 2 0x00000000 2 0x00000000 1 0x00000000>;
1424 interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>,
1425 <0 117 IRQ_TYPE_LEVEL_HIGH>,
1426 <0 118 IRQ_TYPE_LEVEL_HIGH>;
1427 #interrupt-cells = <1>;
1428 interrupt-map-mask = <0 0 0 0>;
1429 interrupt-map = <0 0 0 0 &gic 0 116 IRQ_TYPE_LEVEL_HIGH>;
1430 clocks = <&mstp3_clks R8A7791_CLK_PCIEC>, <&pcie_bus_clk>;
1431 clock-names = "pcie", "pcie_bus";
1432 status = "disabled";
1433 };
09abd1fd 1434
f1951852
LP		 1435 ipmmu_sy0: mmu@e6280000 {
1436 compatible = "renesas,ipmmu-vmsa";
1437 reg = <0 0xe6280000 0 0x1000>;
1438 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1439 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1440 #iommu-cells = <1>;
1441 status = "disabled";
1442 };
1443
1444 ipmmu_sy1: mmu@e6290000 {
1445 compatible = "renesas,ipmmu-vmsa";
1446 reg = <0 0xe6290000 0 0x1000>;
1447 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1448 #iommu-cells = <1>;
1449 status = "disabled";
1450 };
1451
1452 ipmmu_ds: mmu@e6740000 {
1453 compatible = "renesas,ipmmu-vmsa";
1454 reg = <0 0xe6740000 0 0x1000>;
1455 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1456 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1457 #iommu-cells = <1>;
1458 status = "disabled";
1459 };
1460
1461 ipmmu_mp: mmu@ec680000 {
1462 compatible = "renesas,ipmmu-vmsa";
1463 reg = <0 0xec680000 0 0x1000>;
1464 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1465 #iommu-cells = <1>;
1466 status = "disabled";
1467 };
1468
1469 ipmmu_mx: mmu@fe951000 {
1470 compatible = "renesas,ipmmu-vmsa";
1471 reg = <0 0xfe951000 0 0x1000>;
1472 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1473 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1474 #iommu-cells = <1>;
1475 status = "disabled";
1476 };
1477
1478 ipmmu_rt: mmu@ffc80000 {
1479 compatible = "renesas,ipmmu-vmsa";
1480 reg = <0 0xffc80000 0 0x1000>;
1481 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1482 #iommu-cells = <1>;
1483 status = "disabled";
1484 };
1485
1486 ipmmu_gp: mmu@e62a0000 {
1487 compatible = "renesas,ipmmu-vmsa";
1488 reg = <0 0xe62a0000 0 0x1000>;
1489 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1490 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1491 #iommu-cells = <1>;
1492 status = "disabled";
1493 };
1494
6b83dc1d 1495 rcar_sound: rcar_sound@ec500000 {
d2b541c9
KM		 1496 /*
1497 * #sound-dai-cells is required
1498 *
1499 * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
1500 * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
1501 */
f49cd2b3 1502 compatible = "renesas,rcar_sound-r8a7791", "renesas,rcar_sound-gen2";
09abd1fd
KM		 1503 reg = <0 0xec500000 0 0x1000>, /* SCU */
1504 <0 0xec5a0000 0 0x100>, /* ADG */
1505 <0 0xec540000 0 0x1000>, /* SSIU */
1506 <0 0xec541000 0 0x1280>; /* SSI */
1507 clocks = <&mstp10_clks R8A7791_CLK_SSI_ALL>,
1508 <&mstp10_clks R8A7791_CLK_SSI9>, <&mstp10_clks R8A7791_CLK_SSI8>,
1509 <&mstp10_clks R8A7791_CLK_SSI7>, <&mstp10_clks R8A7791_CLK_SSI6>,
1510 <&mstp10_clks R8A7791_CLK_SSI5>, <&mstp10_clks R8A7791_CLK_SSI4>,
1511 <&mstp10_clks R8A7791_CLK_SSI3>, <&mstp10_clks R8A7791_CLK_SSI2>,
1512 <&mstp10_clks R8A7791_CLK_SSI1>, <&mstp10_clks R8A7791_CLK_SSI0>,
1513 <&mstp10_clks R8A7791_CLK_SCU_SRC9>, <&mstp10_clks R8A7791_CLK_SCU_SRC8>,
1514 <&mstp10_clks R8A7791_CLK_SCU_SRC7>, <&mstp10_clks R8A7791_CLK_SCU_SRC6>,
1515 <&mstp10_clks R8A7791_CLK_SCU_SRC5>, <&mstp10_clks R8A7791_CLK_SCU_SRC4>,
1516 <&mstp10_clks R8A7791_CLK_SCU_SRC3>, <&mstp10_clks R8A7791_CLK_SCU_SRC2>,
1517 <&mstp10_clks R8A7791_CLK_SCU_SRC1>, <&mstp10_clks R8A7791_CLK_SCU_SRC0>,
150c8ad4 1518 <&mstp10_clks R8A7791_CLK_SCU_DVC0>, <&mstp10_clks R8A7791_CLK_SCU_DVC1>,
09abd1fd
KM		 1519 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>;
1520 clock-names = "ssi-all",
1521 "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5",
1522 "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0",
1523 "src.9", "src.8", "src.7", "src.6", "src.5",
1524 "src.4", "src.3", "src.2", "src.1", "src.0",
150c8ad4 1525 "dvc.0", "dvc.1",
09abd1fd
KM		 1526 "clk_a", "clk_b", "clk_c", "clk_i";
1527
1528 status = "disabled";
1529
150c8ad4
KM		 1530 rcar_sound,dvc {
1531 dvc0: dvc@0 { };
1532 dvc1: dvc@1 { };
1533 };
1534
09abd1fd 1535 rcar_sound,src {
8856102d
KM		 1536 src0: src@0 { interrupts = <0 352 IRQ_TYPE_LEVEL_HIGH>; };
1537 src1: src@1 { interrupts = <0 353 IRQ_TYPE_LEVEL_HIGH>; };
1538 src2: src@2 { interrupts = <0 354 IRQ_TYPE_LEVEL_HIGH>; };
1539 src3: src@3 { interrupts = <0 355 IRQ_TYPE_LEVEL_HIGH>; };
1540 src4: src@4 { interrupts = <0 356 IRQ_TYPE_LEVEL_HIGH>; };
1541 src5: src@5 { interrupts = <0 357 IRQ_TYPE_LEVEL_HIGH>; };
1542 src6: src@6 { interrupts = <0 358 IRQ_TYPE_LEVEL_HIGH>; };
1543 src7: src@7 { interrupts = <0 359 IRQ_TYPE_LEVEL_HIGH>; };
1544 src8: src@8 { interrupts = <0 360 IRQ_TYPE_LEVEL_HIGH>; };
1545 src9: src@9 { interrupts = <0 361 IRQ_TYPE_LEVEL_HIGH>; };
09abd1fd
KM		 1546 };
1547
1548 rcar_sound,ssi {
1549 ssi0: ssi@0 { interrupts = <0 370 IRQ_TYPE_LEVEL_HIGH>; };
1550 ssi1: ssi@1 { interrupts = <0 371 IRQ_TYPE_LEVEL_HIGH>; };
1551 ssi2: ssi@2 { interrupts = <0 372 IRQ_TYPE_LEVEL_HIGH>; };
1552 ssi3: ssi@3 { interrupts = <0 373 IRQ_TYPE_LEVEL_HIGH>; };
1553 ssi4: ssi@4 { interrupts = <0 374 IRQ_TYPE_LEVEL_HIGH>; };
1554 ssi5: ssi@5 { interrupts = <0 375 IRQ_TYPE_LEVEL_HIGH>; };
1555 ssi6: ssi@6 { interrupts = <0 376 IRQ_TYPE_LEVEL_HIGH>; };
1556 ssi7: ssi@7 { interrupts = <0 377 IRQ_TYPE_LEVEL_HIGH>; };
1557 ssi8: ssi@8 { interrupts = <0 378 IRQ_TYPE_LEVEL_HIGH>; };
1558 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1559 };
1560 };
0d0771ab 1561};
Linux kernel - Deliverables
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