projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 4018fba4 SS |
1 | /* |
| 2 | * Device Tree Source for the Blanche board | |
| 3 | * | |
| 4 | * Copyright (C) 2014 Renesas Electronics Corporation | |
| 5 | * Copyright (C) 2016 Cogent Embedded, Inc. | |
| 6 | * | |
| 7 | * This file is licensed under the terms of the GNU General Public License | |
| 8 | * version 2. This program is licensed "as is" without any warranty of any | |
| 9 | * kind, whether express or implied. | |
| 10 | */ | |
| 11 | ||
| 12 | /dts-v1/; | |
| 13 | #include "r8a7792.dtsi" | |
| 14 | ||
| 15 | / { | |
| 16 | model = "Blanche"; | |
| 17 | compatible = "renesas,blanche", "renesas,r8a7792"; | |
| 18 | ||
| 19 | aliases { | |
| 20 | serial0 = &scif0; | |
| 21 | serial1 = &scif3; | |
| 22 | }; | |
| 23 | ||
| 24 | chosen { | |
| f80b6dfd | 25 | bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp"; |
| 4018fba4 SS |
26 | stdout-path = "serial0:115200n8"; |
| 27 | }; | |
| 28 | ||
| 29 | memory@40000000 { | |
| 30 | device_type = "memory"; | |
| 31 | reg = <0 0x40000000 0 0x40000000>; | |
| 32 | }; | |
| f80b6dfd SS |
33 | |
| 34 | d3_3v: regulator-3v3 { | |
| 35 | compatible = "regulator-fixed"; | |
| 36 | regulator-name = "D3.3V"; | |
| 37 | regulator-min-microvolt = <3300000>; | |
| 38 | regulator-max-microvolt = <3300000>; | |
| 39 | regulator-boot-on; | |
| 40 | regulator-always-on; | |
| 41 | }; | |
| 42 | ||
| 43 | ethernet@18000000 { | |
| 44 | compatible = "smsc,lan89218", "smsc,lan9115"; | |
| 45 | reg = <0 0x18000000 0 0x100>; | |
| 46 | phy-mode = "mii"; | |
| 47 | interrupt-parent = <&irqc>; | |
| 48 | interrupts = <0 IRQ_TYPE_EDGE_FALLING>; | |
| 49 | smsc,irq-push-pull; | |
| 50 | reg-io-width = <4>; | |
| 51 | vddvario-supply = <&d3_3v>; | |
| 52 | vdd33a-supply = <&d3_3v>; | |
| 53 | }; | |
| 4018fba4 SS |
54 | }; |
| 55 | ||
| 56 | &extal_clk { | |
| 57 | clock-frequency = <20000000>; | |
| 58 | }; | |
| 59 | ||
| 2cd452d1 SS |
60 | &pfc { |
| 61 | scif0_pins: scif0 { | |
| 62 | groups = "scif0_data"; | |
| 63 | function = "scif0"; | |
| 64 | }; | |
| 65 | ||
| 66 | scif3_pins: scif3 { | |
| 67 | groups = "scif3_data"; | |
| 68 | function = "scif3"; | |
| 69 | }; | |
| 70 | }; | |
| 71 | ||
| 4018fba4 | 72 | &scif0 { |
| 2cd452d1 SS |
73 | pinctrl-0 = <&scif0_pins>; |
| 74 | pinctrl-names = "default"; | |
| 75 | ||
| 4018fba4 SS |
76 | status = "okay"; |
| 77 | }; | |
| 78 | ||
| 79 | &scif3 { | |
| 2cd452d1 SS |
80 | pinctrl-0 = <&scif3_pins>; |
| 81 | pinctrl-names = "default"; | |
| 82 | ||
| 4018fba4 SS |
83 | status = "okay"; |
| 84 | }; |