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0e03e8ae UH |
1 | /* |
2 | * Device Tree Source for the r8a7793 SoC | |
3 | * | |
4 | * Copyright (C) 2014-2015 Renesas Electronics Corporation | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | #include <dt-bindings/clock/r8a7793-clock.h> | |
12 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
13 | #include <dt-bindings/interrupt-controller/irq.h> | |
a7ede1ab | 14 | #include <dt-bindings/power/r8a7793-sysc.h> |
0e03e8ae UH |
15 | |
16 | / { | |
17 | compatible = "renesas,r8a7793"; | |
18 | interrupt-parent = <&gic>; | |
19 | #address-cells = <2>; | |
20 | #size-cells = <2>; | |
21 | ||
469352ad | 22 | aliases { |
7aed17f4 LP |
23 | i2c0 = &i2c0; |
24 | i2c1 = &i2c1; | |
25 | i2c2 = &i2c2; | |
26 | i2c3 = &i2c3; | |
27 | i2c4 = &i2c4; | |
28 | i2c5 = &i2c5; | |
29 | i2c6 = &i2c6; | |
30 | i2c7 = &i2c7; | |
31 | i2c8 = &i2c8; | |
469352ad SH |
32 | spi0 = &qspi; |
33 | }; | |
34 | ||
0e03e8ae UH |
35 | cpus { |
36 | #address-cells = <1>; | |
37 | #size-cells = <0>; | |
65b133cd | 38 | enable-method = "renesas,apmu"; |
0e03e8ae UH |
39 | |
40 | cpu0: cpu@0 { | |
41 | device_type = "cpu"; | |
42 | compatible = "arm,cortex-a15"; | |
43 | reg = <0>; | |
44 | clock-frequency = <1500000000>; | |
45 | voltage-tolerance = <1>; /* 1% */ | |
46 | clocks = <&cpg_clocks R8A7793_CLK_Z>; | |
47 | clock-latency = <300000>; /* 300 us */ | |
a7ede1ab | 48 | power-domains = <&sysc R8A7793_PD_CA15_CPU0>; |
0e03e8ae UH |
49 | |
50 | /* kHz - uV - OPPs unknown yet */ | |
51 | operating-points = <1500000 1000000>, | |
52 | <1312500 1000000>, | |
53 | <1125000 1000000>, | |
54 | < 937500 1000000>, | |
55 | < 750000 1000000>, | |
56 | < 375000 1000000>; | |
fdd0dbd8 | 57 | next-level-cache = <&L2_CA15>; |
0e03e8ae | 58 | }; |
ad53f5f0 | 59 | |
65b133cd MD |
60 | cpu1: cpu@1 { |
61 | device_type = "cpu"; | |
62 | compatible = "arm,cortex-a15"; | |
63 | reg = <1>; | |
64 | clock-frequency = <1500000000>; | |
65 | power-domains = <&sysc R8A7793_PD_CA15_CPU1>; | |
66 | }; | |
67 | ||
ad53f5f0 GU |
68 | L2_CA15: cache-controller@0 { |
69 | compatible = "cache"; | |
70 | reg = <0>; | |
71 | power-domains = <&sysc R8A7793_PD_CA15_SCU>; | |
72 | cache-unified; | |
73 | cache-level = <2>; | |
74 | }; | |
0e03e8ae UH |
75 | }; |
76 | ||
65b133cd MD |
77 | apmu@e6152000 { |
78 | compatible = "renesas,r8a7793-apmu", "renesas,apmu"; | |
79 | reg = <0 0xe6152000 0 0x188>; | |
80 | cpus = <&cpu0 &cpu1>; | |
81 | }; | |
82 | ||
57f9156b KM |
83 | thermal-zones { |
84 | cpu_thermal: cpu-thermal { | |
85 | polling-delay-passive = <0>; | |
86 | polling-delay = <0>; | |
87 | ||
88 | thermal-sensors = <&thermal>; | |
89 | ||
90 | trips { | |
91 | cpu-crit { | |
92 | temperature = <115000>; | |
93 | hysteresis = <0>; | |
94 | type = "critical"; | |
95 | }; | |
96 | }; | |
97 | cooling-maps { | |
98 | }; | |
99 | }; | |
100 | }; | |
101 | ||
0e03e8ae | 102 | gic: interrupt-controller@f1001000 { |
5b3b3268 | 103 | compatible = "arm,gic-400"; |
0e03e8ae UH |
104 | #interrupt-cells = <3>; |
105 | #address-cells = <0>; | |
106 | interrupt-controller; | |
107 | reg = <0 0xf1001000 0 0x1000>, | |
108 | <0 0xf1002000 0 0x1000>, | |
109 | <0 0xf1004000 0 0x2000>, | |
110 | <0 0xf1006000 0 0x2000>; | |
214e8481 | 111 | interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; |
0e03e8ae UH |
112 | }; |
113 | ||
d96011d0 MD |
114 | gpio0: gpio@e6050000 { |
115 | compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; | |
116 | reg = <0 0xe6050000 0 0x50>; | |
214e8481 | 117 | interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
d96011d0 MD |
118 | #gpio-cells = <2>; |
119 | gpio-controller; | |
120 | gpio-ranges = <&pfc 0 0 32>; | |
121 | #interrupt-cells = <2>; | |
122 | interrupt-controller; | |
123 | clocks = <&mstp9_clks R8A7793_CLK_GPIO0>; | |
f1ba73ea | 124 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
d96011d0 MD |
125 | }; |
126 | ||
127 | gpio1: gpio@e6051000 { | |
128 | compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; | |
129 | reg = <0 0xe6051000 0 0x50>; | |
214e8481 | 130 | interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
d96011d0 MD |
131 | #gpio-cells = <2>; |
132 | gpio-controller; | |
133 | gpio-ranges = <&pfc 0 32 26>; | |
134 | #interrupt-cells = <2>; | |
135 | interrupt-controller; | |
136 | clocks = <&mstp9_clks R8A7793_CLK_GPIO1>; | |
f1ba73ea | 137 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
d96011d0 MD |
138 | }; |
139 | ||
140 | gpio2: gpio@e6052000 { | |
141 | compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; | |
142 | reg = <0 0xe6052000 0 0x50>; | |
214e8481 | 143 | interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
d96011d0 MD |
144 | #gpio-cells = <2>; |
145 | gpio-controller; | |
146 | gpio-ranges = <&pfc 0 64 32>; | |
147 | #interrupt-cells = <2>; | |
148 | interrupt-controller; | |
149 | clocks = <&mstp9_clks R8A7793_CLK_GPIO2>; | |
f1ba73ea | 150 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
d96011d0 MD |
151 | }; |
152 | ||
153 | gpio3: gpio@e6053000 { | |
154 | compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; | |
155 | reg = <0 0xe6053000 0 0x50>; | |
214e8481 | 156 | interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
d96011d0 MD |
157 | #gpio-cells = <2>; |
158 | gpio-controller; | |
159 | gpio-ranges = <&pfc 0 96 32>; | |
160 | #interrupt-cells = <2>; | |
161 | interrupt-controller; | |
162 | clocks = <&mstp9_clks R8A7793_CLK_GPIO3>; | |
f1ba73ea | 163 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
d96011d0 MD |
164 | }; |
165 | ||
166 | gpio4: gpio@e6054000 { | |
167 | compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; | |
168 | reg = <0 0xe6054000 0 0x50>; | |
214e8481 | 169 | interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
d96011d0 MD |
170 | #gpio-cells = <2>; |
171 | gpio-controller; | |
172 | gpio-ranges = <&pfc 0 128 32>; | |
173 | #interrupt-cells = <2>; | |
174 | interrupt-controller; | |
175 | clocks = <&mstp9_clks R8A7793_CLK_GPIO4>; | |
f1ba73ea | 176 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
d96011d0 MD |
177 | }; |
178 | ||
179 | gpio5: gpio@e6055000 { | |
180 | compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; | |
181 | reg = <0 0xe6055000 0 0x50>; | |
214e8481 | 182 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
d96011d0 MD |
183 | #gpio-cells = <2>; |
184 | gpio-controller; | |
185 | gpio-ranges = <&pfc 0 160 32>; | |
186 | #interrupt-cells = <2>; | |
187 | interrupt-controller; | |
188 | clocks = <&mstp9_clks R8A7793_CLK_GPIO5>; | |
f1ba73ea | 189 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
d96011d0 MD |
190 | }; |
191 | ||
192 | gpio6: gpio@e6055400 { | |
193 | compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; | |
194 | reg = <0 0xe6055400 0 0x50>; | |
214e8481 | 195 | interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
d96011d0 MD |
196 | #gpio-cells = <2>; |
197 | gpio-controller; | |
198 | gpio-ranges = <&pfc 0 192 32>; | |
199 | #interrupt-cells = <2>; | |
200 | interrupt-controller; | |
201 | clocks = <&mstp9_clks R8A7793_CLK_GPIO6>; | |
f1ba73ea | 202 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
d96011d0 MD |
203 | }; |
204 | ||
205 | gpio7: gpio@e6055800 { | |
206 | compatible = "renesas,gpio-r8a7793", "renesas,gpio-rcar"; | |
207 | reg = <0 0xe6055800 0 0x50>; | |
214e8481 | 208 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
d96011d0 MD |
209 | #gpio-cells = <2>; |
210 | gpio-controller; | |
211 | gpio-ranges = <&pfc 0 224 26>; | |
212 | #interrupt-cells = <2>; | |
213 | interrupt-controller; | |
214 | clocks = <&mstp9_clks R8A7793_CLK_GPIO7>; | |
f1ba73ea | 215 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
d96011d0 MD |
216 | }; |
217 | ||
57f9156b KM |
218 | thermal: thermal@e61f0000 { |
219 | compatible = "renesas,thermal-r8a7793", | |
220 | "renesas,rcar-gen2-thermal", | |
221 | "renesas,rcar-thermal"; | |
0fddfb5b | 222 | reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; |
214e8481 | 223 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
0fddfb5b | 224 | clocks = <&mstp5_clks R8A7793_CLK_THERMAL>; |
f1ba73ea | 225 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
57f9156b | 226 | #thermal-sensor-cells = <0>; |
0fddfb5b SH |
227 | }; |
228 | ||
0e03e8ae UH |
229 | timer { |
230 | compatible = "arm,armv7-timer"; | |
214e8481 SH |
231 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, |
232 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
233 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, | |
234 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; | |
0e03e8ae UH |
235 | }; |
236 | ||
237 | cmt0: timer@ffca0000 { | |
238 | compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; | |
239 | reg = <0 0xffca0000 0 0x1004>; | |
214e8481 SH |
240 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
241 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
0e03e8ae UH |
242 | clocks = <&mstp1_clks R8A7793_CLK_CMT0>; |
243 | clock-names = "fck"; | |
f1ba73ea | 244 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
0e03e8ae UH |
245 | |
246 | renesas,channels-mask = <0x60>; | |
247 | ||
248 | status = "disabled"; | |
249 | }; | |
250 | ||
251 | cmt1: timer@e6130000 { | |
252 | compatible = "renesas,cmt-48-r8a7793", "renesas,cmt-48-gen2"; | |
253 | reg = <0 0xe6130000 0 0x1004>; | |
214e8481 SH |
254 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, |
255 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
256 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, | |
257 | <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, | |
258 | <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, | |
259 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, | |
260 | <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, | |
261 | <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
0e03e8ae UH |
262 | clocks = <&mstp3_clks R8A7793_CLK_CMT1>; |
263 | clock-names = "fck"; | |
f1ba73ea | 264 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
0e03e8ae UH |
265 | |
266 | renesas,channels-mask = <0xff>; | |
267 | ||
268 | status = "disabled"; | |
269 | }; | |
270 | ||
271 | irqc0: interrupt-controller@e61c0000 { | |
272 | compatible = "renesas,irqc-r8a7793", "renesas,irqc"; | |
273 | #interrupt-cells = <2>; | |
274 | interrupt-controller; | |
275 | reg = <0 0xe61c0000 0 0x200>; | |
214e8481 SH |
276 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
277 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
278 | <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
279 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
280 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, | |
281 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, | |
282 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, | |
283 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, | |
284 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, | |
285 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
0e03e8ae | 286 | clocks = <&mstp4_clks R8A7793_CLK_IRQC>; |
f1ba73ea | 287 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
0e03e8ae UH |
288 | }; |
289 | ||
cefe5a56 SH |
290 | dmac0: dma-controller@e6700000 { |
291 | compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; | |
292 | reg = <0 0xe6700000 0 0x20000>; | |
214e8481 SH |
293 | interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH |
294 | GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH | |
295 | GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH | |
296 | GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH | |
297 | GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH | |
298 | GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH | |
299 | GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH | |
300 | GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH | |
301 | GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH | |
302 | GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH | |
303 | GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH | |
304 | GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH | |
305 | GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH | |
306 | GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH | |
307 | GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH | |
308 | GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; | |
cefe5a56 SH |
309 | interrupt-names = "error", |
310 | "ch0", "ch1", "ch2", "ch3", | |
311 | "ch4", "ch5", "ch6", "ch7", | |
312 | "ch8", "ch9", "ch10", "ch11", | |
313 | "ch12", "ch13", "ch14"; | |
314 | clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC0>; | |
315 | clock-names = "fck"; | |
f1ba73ea | 316 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
cefe5a56 SH |
317 | #dma-cells = <1>; |
318 | dma-channels = <15>; | |
319 | }; | |
320 | ||
321 | dmac1: dma-controller@e6720000 { | |
322 | compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; | |
323 | reg = <0 0xe6720000 0 0x20000>; | |
214e8481 SH |
324 | interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
325 | GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH | |
326 | GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH | |
327 | GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH | |
328 | GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH | |
329 | GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH | |
330 | GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH | |
331 | GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH | |
332 | GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH | |
333 | GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH | |
334 | GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH | |
335 | GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH | |
336 | GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH | |
337 | GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH | |
338 | GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH | |
339 | GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; | |
cefe5a56 SH |
340 | interrupt-names = "error", |
341 | "ch0", "ch1", "ch2", "ch3", | |
342 | "ch4", "ch5", "ch6", "ch7", | |
343 | "ch8", "ch9", "ch10", "ch11", | |
344 | "ch12", "ch13", "ch14"; | |
345 | clocks = <&mstp2_clks R8A7793_CLK_SYS_DMAC1>; | |
346 | clock-names = "fck"; | |
f1ba73ea | 347 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
cefe5a56 SH |
348 | #dma-cells = <1>; |
349 | dma-channels = <15>; | |
350 | }; | |
351 | ||
6708eb73 SH |
352 | audma0: dma-controller@ec700000 { |
353 | compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; | |
354 | reg = <0 0xec700000 0 0x10000>; | |
355 | interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH | |
356 | GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH | |
357 | GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH | |
358 | GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH | |
359 | GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH | |
360 | GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH | |
361 | GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH | |
362 | GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH | |
363 | GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH | |
364 | GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH | |
365 | GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH | |
366 | GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH | |
367 | GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH | |
368 | GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; | |
369 | interrupt-names = "error", | |
370 | "ch0", "ch1", "ch2", "ch3", | |
371 | "ch4", "ch5", "ch6", "ch7", | |
372 | "ch8", "ch9", "ch10", "ch11", | |
373 | "ch12"; | |
374 | clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC0>; | |
375 | clock-names = "fck"; | |
f1ba73ea | 376 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
6708eb73 SH |
377 | #dma-cells = <1>; |
378 | dma-channels = <13>; | |
379 | }; | |
380 | ||
381 | audma1: dma-controller@ec720000 { | |
382 | compatible = "renesas,dmac-r8a7793", "renesas,rcar-dmac"; | |
383 | reg = <0 0xec720000 0 0x10000>; | |
384 | interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH | |
385 | GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH | |
386 | GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH | |
387 | GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH | |
388 | GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH | |
389 | GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH | |
390 | GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH | |
391 | GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH | |
392 | GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH | |
393 | GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH | |
394 | GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH | |
395 | GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH | |
396 | GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH | |
397 | GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; | |
398 | interrupt-names = "error", | |
399 | "ch0", "ch1", "ch2", "ch3", | |
400 | "ch4", "ch5", "ch6", "ch7", | |
401 | "ch8", "ch9", "ch10", "ch11", | |
402 | "ch12"; | |
403 | clocks = <&mstp5_clks R8A7793_CLK_AUDIO_DMAC1>; | |
404 | clock-names = "fck"; | |
f1ba73ea | 405 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
6708eb73 SH |
406 | #dma-cells = <1>; |
407 | dma-channels = <13>; | |
408 | }; | |
409 | ||
7aed17f4 LP |
410 | /* The memory map in the User's Manual maps the cores to bus numbers */ |
411 | i2c0: i2c@e6508000 { | |
412 | #address-cells = <1>; | |
413 | #size-cells = <0>; | |
414 | compatible = "renesas,i2c-r8a7793"; | |
415 | reg = <0 0xe6508000 0 0x40>; | |
214e8481 | 416 | interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 417 | clocks = <&mstp9_clks R8A7793_CLK_I2C0>; |
f1ba73ea | 418 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
419 | i2c-scl-internal-delay-ns = <6>; |
420 | status = "disabled"; | |
421 | }; | |
422 | ||
423 | i2c1: i2c@e6518000 { | |
424 | #address-cells = <1>; | |
425 | #size-cells = <0>; | |
426 | compatible = "renesas,i2c-r8a7793"; | |
427 | reg = <0 0xe6518000 0 0x40>; | |
214e8481 | 428 | interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 429 | clocks = <&mstp9_clks R8A7793_CLK_I2C1>; |
f1ba73ea | 430 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
431 | i2c-scl-internal-delay-ns = <6>; |
432 | status = "disabled"; | |
433 | }; | |
434 | ||
435 | i2c2: i2c@e6530000 { | |
436 | #address-cells = <1>; | |
437 | #size-cells = <0>; | |
438 | compatible = "renesas,i2c-r8a7793"; | |
439 | reg = <0 0xe6530000 0 0x40>; | |
214e8481 | 440 | interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 441 | clocks = <&mstp9_clks R8A7793_CLK_I2C2>; |
f1ba73ea | 442 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
443 | i2c-scl-internal-delay-ns = <6>; |
444 | status = "disabled"; | |
445 | }; | |
446 | ||
447 | i2c3: i2c@e6540000 { | |
448 | #address-cells = <1>; | |
449 | #size-cells = <0>; | |
450 | compatible = "renesas,i2c-r8a7793"; | |
451 | reg = <0 0xe6540000 0 0x40>; | |
214e8481 | 452 | interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 453 | clocks = <&mstp9_clks R8A7793_CLK_I2C3>; |
f1ba73ea | 454 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
455 | i2c-scl-internal-delay-ns = <6>; |
456 | status = "disabled"; | |
457 | }; | |
458 | ||
459 | i2c4: i2c@e6520000 { | |
460 | #address-cells = <1>; | |
461 | #size-cells = <0>; | |
462 | compatible = "renesas,i2c-r8a7793"; | |
463 | reg = <0 0xe6520000 0 0x40>; | |
214e8481 | 464 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 465 | clocks = <&mstp9_clks R8A7793_CLK_I2C4>; |
f1ba73ea | 466 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
467 | i2c-scl-internal-delay-ns = <6>; |
468 | status = "disabled"; | |
469 | }; | |
470 | ||
471 | i2c5: i2c@e6528000 { | |
472 | /* doesn't need pinmux */ | |
473 | #address-cells = <1>; | |
474 | #size-cells = <0>; | |
475 | compatible = "renesas,i2c-r8a7793"; | |
476 | reg = <0 0xe6528000 0 0x40>; | |
214e8481 | 477 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 478 | clocks = <&mstp9_clks R8A7793_CLK_I2C5>; |
f1ba73ea | 479 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
480 | i2c-scl-internal-delay-ns = <110>; |
481 | status = "disabled"; | |
482 | }; | |
483 | ||
484 | i2c6: i2c@e60b0000 { | |
485 | /* doesn't need pinmux */ | |
486 | #address-cells = <1>; | |
487 | #size-cells = <0>; | |
488 | compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; | |
489 | reg = <0 0xe60b0000 0 0x425>; | |
214e8481 | 490 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 491 | clocks = <&mstp9_clks R8A7793_CLK_IICDVFS>; |
a858cd49 NS |
492 | dmas = <&dmac0 0x77>, <&dmac0 0x78>, |
493 | <&dmac1 0x77>, <&dmac1 0x78>; | |
494 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 495 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
496 | status = "disabled"; |
497 | }; | |
498 | ||
499 | i2c7: i2c@e6500000 { | |
500 | #address-cells = <1>; | |
501 | #size-cells = <0>; | |
502 | compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; | |
503 | reg = <0 0xe6500000 0 0x425>; | |
214e8481 | 504 | interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 505 | clocks = <&mstp3_clks R8A7793_CLK_IIC0>; |
a858cd49 NS |
506 | dmas = <&dmac0 0x61>, <&dmac0 0x62>, |
507 | <&dmac1 0x61>, <&dmac1 0x62>; | |
508 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 509 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
510 | status = "disabled"; |
511 | }; | |
512 | ||
513 | i2c8: i2c@e6510000 { | |
514 | #address-cells = <1>; | |
515 | #size-cells = <0>; | |
516 | compatible = "renesas,iic-r8a7793", "renesas,rmobile-iic"; | |
517 | reg = <0 0xe6510000 0 0x425>; | |
214e8481 | 518 | interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; |
7aed17f4 | 519 | clocks = <&mstp3_clks R8A7793_CLK_IIC1>; |
a858cd49 NS |
520 | dmas = <&dmac0 0x65>, <&dmac0 0x66>, |
521 | <&dmac1 0x65>, <&dmac1 0x66>; | |
522 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 523 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
7aed17f4 LP |
524 | status = "disabled"; |
525 | }; | |
526 | ||
c26455c7 SH |
527 | pfc: pfc@e6060000 { |
528 | compatible = "renesas,pfc-r8a7793"; | |
529 | reg = <0 0xe6060000 0 0x250>; | |
c26455c7 SH |
530 | }; |
531 | ||
fc9ee228 UH |
532 | sdhi0: sd@ee100000 { |
533 | compatible = "renesas,sdhi-r8a7793"; | |
534 | reg = <0 0xee100000 0 0x328>; | |
535 | interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; | |
536 | clocks = <&mstp3_clks R8A7793_CLK_SDHI0>; | |
a858cd49 NS |
537 | dmas = <&dmac0 0xcd>, <&dmac0 0xce>, |
538 | <&dmac1 0xcd>, <&dmac1 0xce>; | |
539 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 540 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
fc9ee228 UH |
541 | status = "disabled"; |
542 | }; | |
543 | ||
544 | sdhi1: sd@ee140000 { | |
545 | compatible = "renesas,sdhi-r8a7793"; | |
546 | reg = <0 0xee140000 0 0x100>; | |
547 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; | |
548 | clocks = <&mstp3_clks R8A7793_CLK_SDHI1>; | |
a858cd49 NS |
549 | dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, |
550 | <&dmac1 0xc1>, <&dmac1 0xc2>; | |
551 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 552 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
fc9ee228 UH |
553 | status = "disabled"; |
554 | }; | |
555 | ||
556 | sdhi2: sd@ee160000 { | |
557 | compatible = "renesas,sdhi-r8a7793"; | |
558 | reg = <0 0xee160000 0 0x100>; | |
559 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; | |
560 | clocks = <&mstp3_clks R8A7793_CLK_SDHI2>; | |
a858cd49 NS |
561 | dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, |
562 | <&dmac1 0xd3>, <&dmac1 0xd4>; | |
563 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 564 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
fc9ee228 UH |
565 | status = "disabled"; |
566 | }; | |
567 | ||
d9739aab UH |
568 | mmcif0: mmc@ee200000 { |
569 | compatible = "renesas,mmcif-r8a7793", "renesas,sh-mmcif"; | |
570 | reg = <0 0xee200000 0 0x80>; | |
571 | interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; | |
572 | clocks = <&mstp3_clks R8A7793_CLK_MMCIF0>; | |
a858cd49 NS |
573 | dmas = <&dmac0 0xd1>, <&dmac0 0xd2>, |
574 | <&dmac1 0xd1>, <&dmac1 0xd2>; | |
575 | dma-names = "tx", "rx", "tx", "rx"; | |
d9739aab UH |
576 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
577 | reg-io-width = <4>; | |
578 | status = "disabled"; | |
579 | max-frequency = <97500000>; | |
580 | }; | |
581 | ||
222ca783 | 582 | scifa0: serial@e6c40000 { |
3ffc90a3 GU |
583 | compatible = "renesas,scifa-r8a7793", |
584 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
222ca783 | 585 | reg = <0 0xe6c40000 0 64>; |
214e8481 | 586 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 587 | clocks = <&mstp2_clks R8A7793_CLK_SCIFA0>; |
48f27c19 | 588 | clock-names = "fck"; |
a858cd49 NS |
589 | dmas = <&dmac0 0x21>, <&dmac0 0x22>, |
590 | <&dmac1 0x21>, <&dmac1 0x22>; | |
591 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 592 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
593 | status = "disabled"; |
594 | }; | |
595 | ||
596 | scifa1: serial@e6c50000 { | |
3ffc90a3 GU |
597 | compatible = "renesas,scifa-r8a7793", |
598 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
222ca783 | 599 | reg = <0 0xe6c50000 0 64>; |
214e8481 | 600 | interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 601 | clocks = <&mstp2_clks R8A7793_CLK_SCIFA1>; |
48f27c19 | 602 | clock-names = "fck"; |
a858cd49 NS |
603 | dmas = <&dmac0 0x25>, <&dmac0 0x26>, |
604 | <&dmac1 0x25>, <&dmac1 0x26>; | |
605 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 606 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
607 | status = "disabled"; |
608 | }; | |
609 | ||
610 | scifa2: serial@e6c60000 { | |
3ffc90a3 GU |
611 | compatible = "renesas,scifa-r8a7793", |
612 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
222ca783 | 613 | reg = <0 0xe6c60000 0 64>; |
214e8481 | 614 | interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 615 | clocks = <&mstp2_clks R8A7793_CLK_SCIFA2>; |
48f27c19 | 616 | clock-names = "fck"; |
a858cd49 NS |
617 | dmas = <&dmac0 0x27>, <&dmac0 0x28>, |
618 | <&dmac1 0x27>, <&dmac1 0x28>; | |
619 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 620 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
621 | status = "disabled"; |
622 | }; | |
623 | ||
624 | scifa3: serial@e6c70000 { | |
3ffc90a3 GU |
625 | compatible = "renesas,scifa-r8a7793", |
626 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
222ca783 | 627 | reg = <0 0xe6c70000 0 64>; |
214e8481 | 628 | interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 629 | clocks = <&mstp11_clks R8A7793_CLK_SCIFA3>; |
48f27c19 | 630 | clock-names = "fck"; |
a858cd49 NS |
631 | dmas = <&dmac0 0x1b>, <&dmac0 0x1c>, |
632 | <&dmac1 0x1b>, <&dmac1 0x1c>; | |
633 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 634 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
635 | status = "disabled"; |
636 | }; | |
637 | ||
638 | scifa4: serial@e6c78000 { | |
3ffc90a3 GU |
639 | compatible = "renesas,scifa-r8a7793", |
640 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
222ca783 | 641 | reg = <0 0xe6c78000 0 64>; |
214e8481 | 642 | interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 643 | clocks = <&mstp11_clks R8A7793_CLK_SCIFA4>; |
48f27c19 | 644 | clock-names = "fck"; |
a858cd49 NS |
645 | dmas = <&dmac0 0x1f>, <&dmac0 0x20>, |
646 | <&dmac1 0x1f>, <&dmac1 0x20>; | |
647 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 648 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
649 | status = "disabled"; |
650 | }; | |
651 | ||
652 | scifa5: serial@e6c80000 { | |
3ffc90a3 GU |
653 | compatible = "renesas,scifa-r8a7793", |
654 | "renesas,rcar-gen2-scifa", "renesas,scifa"; | |
222ca783 | 655 | reg = <0 0xe6c80000 0 64>; |
214e8481 | 656 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 657 | clocks = <&mstp11_clks R8A7793_CLK_SCIFA5>; |
48f27c19 | 658 | clock-names = "fck"; |
a858cd49 NS |
659 | dmas = <&dmac0 0x23>, <&dmac0 0x24>, |
660 | <&dmac1 0x23>, <&dmac1 0x24>; | |
661 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 662 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
663 | status = "disabled"; |
664 | }; | |
665 | ||
666 | scifb0: serial@e6c20000 { | |
3ffc90a3 GU |
667 | compatible = "renesas,scifb-r8a7793", |
668 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
222ca783 | 669 | reg = <0 0xe6c20000 0 64>; |
214e8481 | 670 | interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 671 | clocks = <&mstp2_clks R8A7793_CLK_SCIFB0>; |
48f27c19 | 672 | clock-names = "fck"; |
a858cd49 NS |
673 | dmas = <&dmac0 0x3d>, <&dmac0 0x3e>, |
674 | <&dmac1 0x3d>, <&dmac1 0x3e>; | |
675 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 676 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
677 | status = "disabled"; |
678 | }; | |
679 | ||
680 | scifb1: serial@e6c30000 { | |
3ffc90a3 GU |
681 | compatible = "renesas,scifb-r8a7793", |
682 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
222ca783 | 683 | reg = <0 0xe6c30000 0 64>; |
214e8481 | 684 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 685 | clocks = <&mstp2_clks R8A7793_CLK_SCIFB1>; |
48f27c19 | 686 | clock-names = "fck"; |
a858cd49 NS |
687 | dmas = <&dmac0 0x19>, <&dmac0 0x1a>, |
688 | <&dmac1 0x19>, <&dmac1 0x1a>; | |
689 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 690 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
691 | status = "disabled"; |
692 | }; | |
693 | ||
694 | scifb2: serial@e6ce0000 { | |
3ffc90a3 GU |
695 | compatible = "renesas,scifb-r8a7793", |
696 | "renesas,rcar-gen2-scifb", "renesas,scifb"; | |
222ca783 | 697 | reg = <0 0xe6ce0000 0 64>; |
214e8481 | 698 | interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; |
222ca783 | 699 | clocks = <&mstp2_clks R8A7793_CLK_SCIFB2>; |
48f27c19 | 700 | clock-names = "fck"; |
a858cd49 NS |
701 | dmas = <&dmac0 0x1d>, <&dmac0 0x1e>, |
702 | <&dmac1 0x1d>, <&dmac1 0x1e>; | |
703 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 704 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
705 | status = "disabled"; |
706 | }; | |
707 | ||
0e03e8ae | 708 | scif0: serial@e6e60000 { |
3ffc90a3 GU |
709 | compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", |
710 | "renesas,scif"; | |
0e03e8ae | 711 | reg = <0 0xe6e60000 0 64>; |
214e8481 | 712 | interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
713 | clocks = <&mstp7_clks R8A7793_CLK_SCIF0>, <&zs_clk>, |
714 | <&scif_clk>; | |
715 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
716 | dmas = <&dmac0 0x29>, <&dmac0 0x2a>, |
717 | <&dmac1 0x29>, <&dmac1 0x2a>; | |
718 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 719 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
0e03e8ae UH |
720 | status = "disabled"; |
721 | }; | |
722 | ||
723 | scif1: serial@e6e68000 { | |
3ffc90a3 GU |
724 | compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", |
725 | "renesas,scif"; | |
0e03e8ae | 726 | reg = <0 0xe6e68000 0 64>; |
214e8481 | 727 | interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
728 | clocks = <&mstp7_clks R8A7793_CLK_SCIF1>, <&zs_clk>, |
729 | <&scif_clk>; | |
730 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
731 | dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, |
732 | <&dmac1 0x2d>, <&dmac1 0x2e>; | |
733 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 734 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
0e03e8ae UH |
735 | status = "disabled"; |
736 | }; | |
737 | ||
222ca783 | 738 | scif2: serial@e6e58000 { |
3ffc90a3 GU |
739 | compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", |
740 | "renesas,scif"; | |
222ca783 | 741 | reg = <0 0xe6e58000 0 64>; |
214e8481 | 742 | interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
743 | clocks = <&mstp7_clks R8A7793_CLK_SCIF2>, <&zs_clk>, |
744 | <&scif_clk>; | |
745 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
746 | dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, |
747 | <&dmac1 0x2b>, <&dmac1 0x2c>; | |
748 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 749 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
750 | status = "disabled"; |
751 | }; | |
752 | ||
753 | scif3: serial@e6ea8000 { | |
3ffc90a3 GU |
754 | compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", |
755 | "renesas,scif"; | |
222ca783 | 756 | reg = <0 0xe6ea8000 0 64>; |
214e8481 | 757 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
758 | clocks = <&mstp7_clks R8A7793_CLK_SCIF3>, <&zs_clk>, |
759 | <&scif_clk>; | |
760 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
761 | dmas = <&dmac0 0x2f>, <&dmac0 0x30>, |
762 | <&dmac1 0x2f>, <&dmac1 0x30>; | |
763 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 764 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
765 | status = "disabled"; |
766 | }; | |
767 | ||
768 | scif4: serial@e6ee0000 { | |
3ffc90a3 GU |
769 | compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", |
770 | "renesas,scif"; | |
222ca783 | 771 | reg = <0 0xe6ee0000 0 64>; |
214e8481 | 772 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
773 | clocks = <&mstp7_clks R8A7793_CLK_SCIF4>, <&zs_clk>, |
774 | <&scif_clk>; | |
775 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
776 | dmas = <&dmac0 0xfb>, <&dmac0 0xfc>, |
777 | <&dmac1 0xfb>, <&dmac1 0xfc>; | |
778 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 779 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
780 | status = "disabled"; |
781 | }; | |
782 | ||
783 | scif5: serial@e6ee8000 { | |
3ffc90a3 GU |
784 | compatible = "renesas,scif-r8a7793", "renesas,rcar-gen2-scif", |
785 | "renesas,scif"; | |
222ca783 | 786 | reg = <0 0xe6ee8000 0 64>; |
214e8481 | 787 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
788 | clocks = <&mstp7_clks R8A7793_CLK_SCIF5>, <&zs_clk>, |
789 | <&scif_clk>; | |
790 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
791 | dmas = <&dmac0 0xfd>, <&dmac0 0xfe>, |
792 | <&dmac1 0xfd>, <&dmac1 0xfe>; | |
793 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 794 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
795 | status = "disabled"; |
796 | }; | |
797 | ||
798 | hscif0: serial@e62c0000 { | |
3ffc90a3 GU |
799 | compatible = "renesas,hscif-r8a7793", |
800 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
222ca783 | 801 | reg = <0 0xe62c0000 0 96>; |
214e8481 | 802 | interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
803 | clocks = <&mstp7_clks R8A7793_CLK_HSCIF0>, <&zs_clk>, |
804 | <&scif_clk>; | |
805 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
806 | dmas = <&dmac0 0x39>, <&dmac0 0x3a>, |
807 | <&dmac1 0x39>, <&dmac1 0x3a>; | |
808 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 809 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
810 | status = "disabled"; |
811 | }; | |
812 | ||
813 | hscif1: serial@e62c8000 { | |
3ffc90a3 GU |
814 | compatible = "renesas,hscif-r8a7793", |
815 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
222ca783 | 816 | reg = <0 0xe62c8000 0 96>; |
214e8481 | 817 | interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
818 | clocks = <&mstp7_clks R8A7793_CLK_HSCIF1>, <&zs_clk>, |
819 | <&scif_clk>; | |
820 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
821 | dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, |
822 | <&dmac1 0x4d>, <&dmac1 0x4e>; | |
823 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 824 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
825 | status = "disabled"; |
826 | }; | |
827 | ||
828 | hscif2: serial@e62d0000 { | |
3ffc90a3 GU |
829 | compatible = "renesas,hscif-r8a7793", |
830 | "renesas,rcar-gen2-hscif", "renesas,hscif"; | |
222ca783 | 831 | reg = <0 0xe62d0000 0 96>; |
214e8481 | 832 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
166d8ca6 GU |
833 | clocks = <&mstp7_clks R8A7793_CLK_HSCIF2>, <&zs_clk>, |
834 | <&scif_clk>; | |
835 | clock-names = "fck", "brg_int", "scif_clk"; | |
a858cd49 NS |
836 | dmas = <&dmac0 0x3b>, <&dmac0 0x3c>, |
837 | <&dmac1 0x3b>, <&dmac1 0x3c>; | |
838 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 839 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
222ca783 SH |
840 | status = "disabled"; |
841 | }; | |
842 | ||
0e03e8ae UH |
843 | ether: ethernet@ee700000 { |
844 | compatible = "renesas,ether-r8a7793"; | |
845 | reg = <0 0xee700000 0 0x400>; | |
214e8481 | 846 | interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; |
0e03e8ae | 847 | clocks = <&mstp8_clks R8A7793_CLK_ETHER>; |
f1ba73ea | 848 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
0e03e8ae UH |
849 | phy-mode = "rmii"; |
850 | #address-cells = <1>; | |
851 | #size-cells = <0>; | |
852 | status = "disabled"; | |
853 | }; | |
854 | ||
469352ad SH |
855 | qspi: spi@e6b10000 { |
856 | compatible = "renesas,qspi-r8a7793", "renesas,qspi"; | |
857 | reg = <0 0xe6b10000 0 0x2c>; | |
214e8481 | 858 | interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
469352ad | 859 | clocks = <&mstp9_clks R8A7793_CLK_QSPI_MOD>; |
a858cd49 NS |
860 | dmas = <&dmac0 0x17>, <&dmac0 0x18>, |
861 | <&dmac1 0x17>, <&dmac1 0x18>; | |
862 | dma-names = "tx", "rx", "tx", "rx"; | |
f1ba73ea | 863 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
469352ad SH |
864 | num-cs = <1>; |
865 | #address-cells = <1>; | |
866 | #size-cells = <0>; | |
867 | status = "disabled"; | |
868 | }; | |
869 | ||
ee94fc9b LP |
870 | du: display@feb00000 { |
871 | compatible = "renesas,du-r8a7793"; | |
872 | reg = <0 0xfeb00000 0 0x40000>, | |
873 | <0 0xfeb90000 0 0x1c>; | |
874 | reg-names = "du", "lvds.0"; | |
214e8481 SH |
875 | interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
876 | <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; | |
ee94fc9b LP |
877 | clocks = <&mstp7_clks R8A7793_CLK_DU0>, |
878 | <&mstp7_clks R8A7793_CLK_DU1>, | |
879 | <&mstp7_clks R8A7793_CLK_LVDS0>; | |
880 | clock-names = "du.0", "du.1", "lvds.0"; | |
881 | status = "disabled"; | |
882 | ||
883 | ports { | |
884 | #address-cells = <1>; | |
885 | #size-cells = <0>; | |
886 | ||
887 | port@0 { | |
888 | reg = <0>; | |
889 | du_out_rgb: endpoint { | |
890 | }; | |
891 | }; | |
892 | port@1 { | |
893 | reg = <1>; | |
894 | du_out_lvds0: endpoint { | |
895 | }; | |
896 | }; | |
897 | }; | |
898 | }; | |
899 | ||
a0e300ce SH |
900 | can0: can@e6e80000 { |
901 | compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; | |
902 | reg = <0 0xe6e80000 0 0x1000>; | |
903 | interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
904 | clocks = <&mstp9_clks R8A7793_CLK_RCAN0>, | |
905 | <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; | |
906 | clock-names = "clkp1", "clkp2", "can_clk"; | |
f1ba73ea | 907 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
a0e300ce SH |
908 | status = "disabled"; |
909 | }; | |
910 | ||
911 | can1: can@e6e88000 { | |
912 | compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can"; | |
913 | reg = <0 0xe6e88000 0 0x1000>; | |
914 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; | |
915 | clocks = <&mstp9_clks R8A7793_CLK_RCAN1>, | |
916 | <&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>; | |
917 | clock-names = "clkp1", "clkp2", "can_clk"; | |
f1ba73ea | 918 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
a0e300ce SH |
919 | status = "disabled"; |
920 | }; | |
921 | ||
0e03e8ae UH |
922 | clocks { |
923 | #address-cells = <2>; | |
924 | #size-cells = <2>; | |
925 | ranges; | |
926 | ||
927 | /* External root clock */ | |
3b81c0ce | 928 | extal_clk: extal { |
0e03e8ae UH |
929 | compatible = "fixed-clock"; |
930 | #clock-cells = <0>; | |
931 | /* This value must be overridden by the board. */ | |
932 | clock-frequency = <0>; | |
0e03e8ae UH |
933 | }; |
934 | ||
ad6472bf SH |
935 | /* |
936 | * The external audio clocks are configured as 0 Hz fixed frequency clocks by | |
937 | * default. Boards that provide audio clocks should override them. | |
938 | */ | |
939 | audio_clk_a: audio_clk_a { | |
940 | compatible = "fixed-clock"; | |
941 | #clock-cells = <0>; | |
942 | clock-frequency = <0>; | |
ad6472bf SH |
943 | }; |
944 | audio_clk_b: audio_clk_b { | |
945 | compatible = "fixed-clock"; | |
946 | #clock-cells = <0>; | |
947 | clock-frequency = <0>; | |
ad6472bf SH |
948 | }; |
949 | audio_clk_c: audio_clk_c { | |
950 | compatible = "fixed-clock"; | |
951 | #clock-cells = <0>; | |
952 | clock-frequency = <0>; | |
ad6472bf SH |
953 | }; |
954 | ||
7892e6c1 SH |
955 | /* External USB clock - can be overridden by the board */ |
956 | usb_extal_clk: usb_extal { | |
957 | compatible = "fixed-clock"; | |
958 | #clock-cells = <0>; | |
959 | clock-frequency = <48000000>; | |
960 | }; | |
961 | ||
962 | /* External CAN clock */ | |
963 | can_clk: can { | |
964 | compatible = "fixed-clock"; | |
965 | #clock-cells = <0>; | |
966 | /* This value must be overridden by the board. */ | |
967 | clock-frequency = <0>; | |
7892e6c1 SH |
968 | }; |
969 | ||
166d8ca6 GU |
970 | /* External SCIF clock */ |
971 | scif_clk: scif { | |
972 | compatible = "fixed-clock"; | |
973 | #clock-cells = <0>; | |
974 | /* This value must be overridden by the board. */ | |
975 | clock-frequency = <0>; | |
166d8ca6 GU |
976 | }; |
977 | ||
0e03e8ae UH |
978 | /* Special CPG clocks */ |
979 | cpg_clocks: cpg_clocks@e6150000 { | |
980 | compatible = "renesas,r8a7793-cpg-clocks", | |
981 | "renesas,rcar-gen2-cpg-clocks"; | |
982 | reg = <0 0xe6150000 0 0x1000>; | |
7892e6c1 | 983 | clocks = <&extal_clk &usb_extal_clk>; |
0e03e8ae UH |
984 | #clock-cells = <1>; |
985 | clock-output-names = "main", "pll0", "pll1", "pll3", | |
986 | "lb", "qspi", "sdh", "sd0", "z", | |
987 | "rcan", "adsp"; | |
4b31bad5 | 988 | #power-domain-cells = <0>; |
0e03e8ae UH |
989 | }; |
990 | ||
991 | /* Variable factor clocks */ | |
3b81c0ce | 992 | sd2_clk: sd2@e6150078 { |
0e03e8ae UH |
993 | compatible = "renesas,r8a7793-div6-clock", |
994 | "renesas,cpg-div6-clock"; | |
995 | reg = <0 0xe6150078 0 4>; | |
996 | clocks = <&pll1_div2_clk>; | |
997 | #clock-cells = <0>; | |
0e03e8ae | 998 | }; |
3b81c0ce | 999 | sd3_clk: sd3@e615026c { |
0e03e8ae UH |
1000 | compatible = "renesas,r8a7793-div6-clock", |
1001 | "renesas,cpg-div6-clock"; | |
1002 | reg = <0 0xe615026c 0 4>; | |
1003 | clocks = <&pll1_div2_clk>; | |
1004 | #clock-cells = <0>; | |
0e03e8ae | 1005 | }; |
3b81c0ce | 1006 | mmc0_clk: mmc0@e6150240 { |
0e03e8ae UH |
1007 | compatible = "renesas,r8a7793-div6-clock", |
1008 | "renesas,cpg-div6-clock"; | |
1009 | reg = <0 0xe6150240 0 4>; | |
1010 | clocks = <&pll1_div2_clk>; | |
1011 | #clock-cells = <0>; | |
0e03e8ae UH |
1012 | }; |
1013 | ||
1014 | /* Fixed factor clocks */ | |
3b81c0ce | 1015 | pll1_div2_clk: pll1_div2 { |
0e03e8ae UH |
1016 | compatible = "fixed-factor-clock"; |
1017 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; | |
1018 | #clock-cells = <0>; | |
1019 | clock-div = <2>; | |
1020 | clock-mult = <1>; | |
0e03e8ae | 1021 | }; |
3b81c0ce | 1022 | zg_clk: zg { |
0e03e8ae UH |
1023 | compatible = "fixed-factor-clock"; |
1024 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; | |
1025 | #clock-cells = <0>; | |
1026 | clock-div = <5>; | |
1027 | clock-mult = <1>; | |
0e03e8ae | 1028 | }; |
3b81c0ce | 1029 | zx_clk: zx { |
0e03e8ae UH |
1030 | compatible = "fixed-factor-clock"; |
1031 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; | |
1032 | #clock-cells = <0>; | |
1033 | clock-div = <3>; | |
1034 | clock-mult = <1>; | |
0e03e8ae | 1035 | }; |
3b81c0ce | 1036 | zs_clk: zs { |
0e03e8ae UH |
1037 | compatible = "fixed-factor-clock"; |
1038 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; | |
1039 | #clock-cells = <0>; | |
1040 | clock-div = <6>; | |
1041 | clock-mult = <1>; | |
0e03e8ae | 1042 | }; |
3b81c0ce | 1043 | hp_clk: hp { |
0e03e8ae UH |
1044 | compatible = "fixed-factor-clock"; |
1045 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; | |
1046 | #clock-cells = <0>; | |
1047 | clock-div = <12>; | |
1048 | clock-mult = <1>; | |
0e03e8ae | 1049 | }; |
3b81c0ce | 1050 | p_clk: p { |
0e03e8ae UH |
1051 | compatible = "fixed-factor-clock"; |
1052 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; | |
1053 | #clock-cells = <0>; | |
1054 | clock-div = <24>; | |
1055 | clock-mult = <1>; | |
0e03e8ae | 1056 | }; |
3b81c0ce | 1057 | m2_clk: m2 { |
892f09f1 SH |
1058 | compatible = "fixed-factor-clock"; |
1059 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; | |
1060 | #clock-cells = <0>; | |
1061 | clock-div = <8>; | |
1062 | clock-mult = <1>; | |
892f09f1 | 1063 | }; |
3b81c0ce | 1064 | rclk_clk: rclk { |
0e03e8ae UH |
1065 | compatible = "fixed-factor-clock"; |
1066 | clocks = <&cpg_clocks R8A7793_CLK_PLL1>; | |
1067 | #clock-cells = <0>; | |
1068 | clock-div = <(48 * 1024)>; | |
1069 | clock-mult = <1>; | |
0e03e8ae | 1070 | }; |
3b81c0ce | 1071 | mp_clk: mp { |
0e03e8ae UH |
1072 | compatible = "fixed-factor-clock"; |
1073 | clocks = <&pll1_div2_clk>; | |
1074 | #clock-cells = <0>; | |
1075 | clock-div = <15>; | |
1076 | clock-mult = <1>; | |
0e03e8ae | 1077 | }; |
3b81c0ce | 1078 | cp_clk: cp { |
0e03e8ae UH |
1079 | compatible = "fixed-factor-clock"; |
1080 | clocks = <&extal_clk>; | |
1081 | #clock-cells = <0>; | |
1082 | clock-div = <2>; | |
1083 | clock-mult = <1>; | |
0e03e8ae UH |
1084 | }; |
1085 | ||
1086 | /* Gate clocks */ | |
1087 | mstp1_clks: mstp1_clks@e6150134 { | |
1088 | compatible = "renesas,r8a7793-mstp-clocks", | |
1089 | "renesas,cpg-mstp-clocks"; | |
1090 | reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; | |
1091 | clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, | |
1092 | <&zg_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, | |
1093 | <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>, | |
1094 | <&zs_clk>, <&zs_clk>, <&zs_clk>; | |
1095 | #clock-cells = <1>; | |
1096 | clock-indices = < | |
1097 | R8A7793_CLK_VCP0 R8A7793_CLK_VPC0 | |
1098 | R8A7793_CLK_SSP1 R8A7793_CLK_TMU1 | |
1099 | R8A7793_CLK_3DG R8A7793_CLK_2DDMAC | |
1100 | R8A7793_CLK_FDP1_1 R8A7793_CLK_FDP1_0 | |
1101 | R8A7793_CLK_TMU3 R8A7793_CLK_TMU2 | |
1102 | R8A7793_CLK_CMT0 R8A7793_CLK_TMU0 | |
1103 | R8A7793_CLK_VSP1_DU1 R8A7793_CLK_VSP1_DU0 | |
1104 | R8A7793_CLK_VSP1_S | |
1105 | >; | |
1106 | clock-output-names = | |
1107 | "vcp0", "vpc0", "ssp_dev", "tmu1", | |
1108 | "pvrsrvkm", "tddmac", "fdp1", "fdp0", | |
1109 | "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1", | |
1110 | "vsp1-du0", "vsps"; | |
1111 | }; | |
38eb6a3a SH |
1112 | mstp2_clks: mstp2_clks@e6150138 { |
1113 | compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1114 | reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; | |
222ca783 SH |
1115 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, |
1116 | <&mp_clk>, <&mp_clk>, <&zs_clk>, <&zs_clk>; | |
38eb6a3a SH |
1117 | #clock-cells = <1>; |
1118 | clock-indices = < | |
222ca783 SH |
1119 | R8A7793_CLK_SCIFA2 R8A7793_CLK_SCIFA1 R8A7793_CLK_SCIFA0 |
1120 | R8A7793_CLK_SCIFB0 R8A7793_CLK_SCIFB1 R8A7793_CLK_SCIFB2 | |
38eb6a3a SH |
1121 | R8A7793_CLK_SYS_DMAC1 R8A7793_CLK_SYS_DMAC0 |
1122 | >; | |
222ca783 SH |
1123 | clock-output-names = |
1124 | "scifa2", "scifa1", "scifa0", "scifb0", | |
1125 | "scifb1", "scifb2", "sys-dmac1", "sys-dmac0"; | |
38eb6a3a | 1126 | }; |
0e03e8ae UH |
1127 | mstp3_clks: mstp3_clks@e615013c { |
1128 | compatible = "renesas,r8a7793-mstp-clocks", | |
1129 | "renesas,cpg-mstp-clocks"; | |
1130 | reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; | |
1131 | clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, | |
1132 | <&cpg_clocks R8A7793_CLK_SD0>, <&mmc0_clk>, | |
1133 | <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, | |
1134 | <&rclk_clk>, <&hp_clk>, <&hp_clk>; | |
1135 | #clock-cells = <1>; | |
1136 | clock-indices = < | |
1137 | R8A7793_CLK_TPU0 R8A7793_CLK_SDHI2 | |
1138 | R8A7793_CLK_SDHI1 R8A7793_CLK_SDHI0 | |
1139 | R8A7793_CLK_MMCIF0 R8A7793_CLK_IIC0 | |
1140 | R8A7793_CLK_PCIEC R8A7793_CLK_IIC1 | |
1141 | R8A7793_CLK_SSUSB R8A7793_CLK_CMT1 | |
1142 | R8A7793_CLK_USBDMAC0 R8A7793_CLK_USBDMAC1 | |
1143 | >; | |
1144 | clock-output-names = | |
1145 | "tpu0", "sdhi2", "sdhi1", "sdhi0", "mmcif0", | |
1146 | "i2c7", "pciec", "i2c8", "ssusb", "cmt1", | |
1147 | "usbdmac0", "usbdmac1"; | |
1148 | }; | |
1149 | mstp4_clks: mstp4_clks@e6150140 { | |
1150 | compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1151 | reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; | |
1152 | clocks = <&cp_clk>; | |
1153 | #clock-cells = <1>; | |
1154 | clock-indices = <R8A7793_CLK_IRQC>; | |
1155 | clock-output-names = "irqc"; | |
1156 | }; | |
0fddfb5b SH |
1157 | mstp5_clks: mstp5_clks@e6150144 { |
1158 | compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1159 | reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; | |
8d2883bd | 1160 | clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>; |
0fddfb5b | 1161 | #clock-cells = <1>; |
8d2883bd SH |
1162 | clock-indices = <R8A7793_CLK_AUDIO_DMAC0 R8A7793_CLK_AUDIO_DMAC1 |
1163 | R8A7793_CLK_THERMAL>; | |
1164 | clock-output-names = "audmac0", "audmac1", "thermal"; | |
0fddfb5b | 1165 | }; |
0e03e8ae UH |
1166 | mstp7_clks: mstp7_clks@e615014c { |
1167 | compatible = "renesas,r8a7793-mstp-clocks", | |
1168 | "renesas,cpg-mstp-clocks"; | |
1169 | reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; | |
1170 | clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&p_clk>, | |
1171 | <&p_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>, | |
1172 | <&p_clk>, <&p_clk>, <&p_clk>, <&zx_clk>, | |
1173 | <&zx_clk>, <&zx_clk>; | |
1174 | #clock-cells = <1>; | |
1175 | clock-indices = < | |
1176 | R8A7793_CLK_EHCI R8A7793_CLK_HSUSB | |
1177 | R8A7793_CLK_HSCIF2 R8A7793_CLK_SCIF5 | |
1178 | R8A7793_CLK_SCIF4 R8A7793_CLK_HSCIF1 | |
1179 | R8A7793_CLK_HSCIF0 R8A7793_CLK_SCIF3 | |
1180 | R8A7793_CLK_SCIF2 R8A7793_CLK_SCIF1 | |
1181 | R8A7793_CLK_SCIF0 R8A7793_CLK_DU1 | |
1182 | R8A7793_CLK_DU0 R8A7793_CLK_LVDS0 | |
1183 | >; | |
1184 | clock-output-names = | |
1185 | "ehci", "hsusb", "hscif2", "scif5", "scif4", | |
1186 | "hscif1", "hscif0", "scif3", "scif2", | |
1187 | "scif1", "scif0", "du1", "du0", "lvds0"; | |
1188 | }; | |
1189 | mstp8_clks: mstp8_clks@e6150990 { | |
1190 | compatible = "renesas,r8a7793-mstp-clocks", | |
1191 | "renesas,cpg-mstp-clocks"; | |
1192 | reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; | |
1193 | clocks = <&zx_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, | |
1194 | <&p_clk>, <&zs_clk>, <&zs_clk>; | |
1195 | #clock-cells = <1>; | |
1196 | clock-indices = < | |
1197 | R8A7793_CLK_IPMMU_SGX R8A7793_CLK_VIN2 | |
1198 | R8A7793_CLK_VIN1 R8A7793_CLK_VIN0 | |
1199 | R8A7793_CLK_ETHER R8A7793_CLK_SATA1 | |
1200 | R8A7793_CLK_SATA0 | |
1201 | >; | |
1202 | clock-output-names = | |
1203 | "ipmmu_sgx", "vin2", "vin1", "vin0", "ether", | |
1204 | "sata1", "sata0"; | |
1205 | }; | |
469352ad SH |
1206 | mstp9_clks: mstp9_clks@e6150994 { |
1207 | compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1208 | reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; | |
d96011d0 MD |
1209 | clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
1210 | <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, | |
7892e6c1 | 1211 | <&p_clk>, <&p_clk>, |
7aed17f4 LP |
1212 | <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, |
1213 | <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, | |
1214 | <&hp_clk>, <&hp_clk>; | |
469352ad | 1215 | #clock-cells = <1>; |
d96011d0 MD |
1216 | clock-indices = < |
1217 | R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6 | |
1218 | R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 | |
1219 | R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 | |
1220 | R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 | |
7892e6c1 SH |
1221 | R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1 |
1222 | R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5 | |
7aed17f4 LP |
1223 | R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 |
1224 | R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 | |
1225 | R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 | |
d96011d0 MD |
1226 | >; |
1227 | clock-output-names = | |
1228 | "gpio7", "gpio6", "gpio5", "gpio4", | |
1229 | "gpio3", "gpio2", "gpio1", "gpio0", | |
7892e6c1 SH |
1230 | "rcan1", "rcan0", "qspi_mod", "i2c5", |
1231 | "i2c6", "i2c4", "i2c3", "i2c2", "i2c1", | |
1232 | "i2c0"; | |
469352ad | 1233 | }; |
072d3265 SH |
1234 | mstp10_clks: mstp10_clks@e6150998 { |
1235 | compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1236 | reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; | |
1237 | clocks = <&p_clk>, | |
1238 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1239 | <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, | |
1240 | <&p_clk>, | |
1241 | <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, | |
1242 | <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, | |
1243 | <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, | |
1244 | <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, | |
1245 | <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, | |
1246 | <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>, | |
1247 | <&mstp10_clks R8A7793_CLK_SCU_ALL>, <&mstp10_clks R8A7793_CLK_SCU_ALL>; | |
1248 | ||
1249 | #clock-cells = <1>; | |
1250 | clock-indices = < | |
1251 | R8A7793_CLK_SSI_ALL | |
1252 | R8A7793_CLK_SSI9 R8A7793_CLK_SSI8 R8A7793_CLK_SSI7 R8A7793_CLK_SSI6 R8A7793_CLK_SSI5 | |
1253 | R8A7793_CLK_SSI4 R8A7793_CLK_SSI3 R8A7793_CLK_SSI2 R8A7793_CLK_SSI1 R8A7793_CLK_SSI0 | |
1254 | R8A7793_CLK_SCU_ALL | |
1255 | R8A7793_CLK_SCU_DVC1 R8A7793_CLK_SCU_DVC0 | |
1256 | R8A7793_CLK_SCU_CTU1_MIX1 R8A7793_CLK_SCU_CTU0_MIX0 | |
1257 | R8A7793_CLK_SCU_SRC9 R8A7793_CLK_SCU_SRC8 R8A7793_CLK_SCU_SRC7 R8A7793_CLK_SCU_SRC6 R8A7793_CLK_SCU_SRC5 | |
1258 | R8A7793_CLK_SCU_SRC4 R8A7793_CLK_SCU_SRC3 R8A7793_CLK_SCU_SRC2 R8A7793_CLK_SCU_SRC1 R8A7793_CLK_SCU_SRC0 | |
1259 | >; | |
1260 | clock-output-names = | |
1261 | "ssi-all", | |
1262 | "ssi9", "ssi8", "ssi7", "ssi6", "ssi5", | |
1263 | "ssi4", "ssi3", "ssi2", "ssi1", "ssi0", | |
1264 | "scu-all", | |
1265 | "scu-dvc1", "scu-dvc0", | |
1266 | "scu-ctu1-mix1", "scu-ctu0-mix0", | |
1267 | "scu-src9", "scu-src8", "scu-src7", "scu-src6", "scu-src5", | |
1268 | "scu-src4", "scu-src3", "scu-src2", "scu-src1", "scu-src0"; | |
1269 | }; | |
222ca783 SH |
1270 | mstp11_clks: mstp11_clks@e615099c { |
1271 | compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
1272 | reg = <0 0xe615099c 0 4>, <0 0xe61509ac 0 4>; | |
1273 | clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>; | |
1274 | #clock-cells = <1>; | |
1275 | clock-indices = < | |
1276 | R8A7793_CLK_SCIFA3 R8A7793_CLK_SCIFA4 R8A7793_CLK_SCIFA5 | |
1277 | >; | |
1278 | clock-output-names = "scifa3", "scifa4", "scifa5"; | |
1279 | }; | |
0e03e8ae UH |
1280 | }; |
1281 | ||
a7ede1ab GU |
1282 | sysc: system-controller@e6180000 { |
1283 | compatible = "renesas,r8a7793-sysc"; | |
1284 | reg = <0 0xe6180000 0 0x0200>; | |
1285 | #power-domain-cells = <1>; | |
1286 | }; | |
1287 | ||
098cb3a6 | 1288 | ipmmu_sy0: mmu@e6280000 { |
c51b1473 | 1289 | compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; |
098cb3a6 | 1290 | reg = <0 0xe6280000 0 0x1000>; |
214e8481 SH |
1291 | interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, |
1292 | <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; | |
098cb3a6 MD |
1293 | #iommu-cells = <1>; |
1294 | status = "disabled"; | |
1295 | }; | |
1296 | ||
1297 | ipmmu_sy1: mmu@e6290000 { | |
c51b1473 | 1298 | compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; |
098cb3a6 | 1299 | reg = <0 0xe6290000 0 0x1000>; |
214e8481 | 1300 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
098cb3a6 MD |
1301 | #iommu-cells = <1>; |
1302 | status = "disabled"; | |
1303 | }; | |
1304 | ||
1305 | ipmmu_ds: mmu@e6740000 { | |
c51b1473 | 1306 | compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; |
098cb3a6 | 1307 | reg = <0 0xe6740000 0 0x1000>; |
214e8481 SH |
1308 | interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
1309 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; | |
098cb3a6 MD |
1310 | #iommu-cells = <1>; |
1311 | status = "disabled"; | |
1312 | }; | |
1313 | ||
1314 | ipmmu_mp: mmu@ec680000 { | |
c51b1473 | 1315 | compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; |
098cb3a6 | 1316 | reg = <0 0xec680000 0 0x1000>; |
214e8481 | 1317 | interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; |
098cb3a6 MD |
1318 | #iommu-cells = <1>; |
1319 | status = "disabled"; | |
1320 | }; | |
1321 | ||
1322 | ipmmu_mx: mmu@fe951000 { | |
c51b1473 | 1323 | compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; |
098cb3a6 | 1324 | reg = <0 0xfe951000 0 0x1000>; |
214e8481 SH |
1325 | interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, |
1326 | <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; | |
098cb3a6 MD |
1327 | #iommu-cells = <1>; |
1328 | status = "disabled"; | |
1329 | }; | |
1330 | ||
1331 | ipmmu_rt: mmu@ffc80000 { | |
c51b1473 | 1332 | compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; |
098cb3a6 | 1333 | reg = <0 0xffc80000 0 0x1000>; |
214e8481 | 1334 | interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; |
098cb3a6 MD |
1335 | #iommu-cells = <1>; |
1336 | status = "disabled"; | |
1337 | }; | |
1338 | ||
1339 | ipmmu_gp: mmu@e62a0000 { | |
c51b1473 | 1340 | compatible = "renesas,ipmmu-r8a7793", "renesas,ipmmu-vmsa"; |
098cb3a6 | 1341 | reg = <0 0xe62a0000 0 0x1000>; |
214e8481 SH |
1342 | interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, |
1343 | <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; | |
098cb3a6 MD |
1344 | #iommu-cells = <1>; |
1345 | status = "disabled"; | |
1346 | }; | |
951431e0 SH |
1347 | |
1348 | rcar_sound: sound@ec500000 { | |
1349 | /* | |
1350 | * #sound-dai-cells is required | |
1351 | * | |
1352 | * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; | |
1353 | * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; | |
1354 | */ | |
1355 | compatible = "renesas,rcar_sound-r8a7793", "renesas,rcar_sound-gen2"; | |
1356 | reg = <0 0xec500000 0 0x1000>, /* SCU */ | |
1357 | <0 0xec5a0000 0 0x100>, /* ADG */ | |
1358 | <0 0xec540000 0 0x1000>, /* SSIU */ | |
3cf7452a SH |
1359 | <0 0xec541000 0 0x280>, /* SSI */ |
1360 | <0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/ | |
1361 | reg-names = "scu", "adg", "ssiu", "ssi", "audmapp"; | |
951431e0 SH |
1362 | |
1363 | clocks = <&mstp10_clks R8A7793_CLK_SSI_ALL>, | |
1364 | <&mstp10_clks R8A7793_CLK_SSI9>, <&mstp10_clks R8A7793_CLK_SSI8>, | |
1365 | <&mstp10_clks R8A7793_CLK_SSI7>, <&mstp10_clks R8A7793_CLK_SSI6>, | |
1366 | <&mstp10_clks R8A7793_CLK_SSI5>, <&mstp10_clks R8A7793_CLK_SSI4>, | |
1367 | <&mstp10_clks R8A7793_CLK_SSI3>, <&mstp10_clks R8A7793_CLK_SSI2>, | |
1368 | <&mstp10_clks R8A7793_CLK_SSI1>, <&mstp10_clks R8A7793_CLK_SSI0>, | |
1369 | <&mstp10_clks R8A7793_CLK_SCU_SRC9>, <&mstp10_clks R8A7793_CLK_SCU_SRC8>, | |
1370 | <&mstp10_clks R8A7793_CLK_SCU_SRC7>, <&mstp10_clks R8A7793_CLK_SCU_SRC6>, | |
1371 | <&mstp10_clks R8A7793_CLK_SCU_SRC5>, <&mstp10_clks R8A7793_CLK_SCU_SRC4>, | |
1372 | <&mstp10_clks R8A7793_CLK_SCU_SRC3>, <&mstp10_clks R8A7793_CLK_SCU_SRC2>, | |
1373 | <&mstp10_clks R8A7793_CLK_SCU_SRC1>, <&mstp10_clks R8A7793_CLK_SCU_SRC0>, | |
4dfc6f8b | 1374 | <&mstp10_clks R8A7793_CLK_SCU_DVC0>, <&mstp10_clks R8A7793_CLK_SCU_DVC1>, |
951431e0 SH |
1375 | <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>, <&m2_clk>; |
1376 | clock-names = "ssi-all", | |
1377 | "ssi.9", "ssi.8", "ssi.7", "ssi.6", "ssi.5", | |
1378 | "ssi.4", "ssi.3", "ssi.2", "ssi.1", "ssi.0", | |
1379 | "src.9", "src.8", "src.7", "src.6", "src.5", | |
1380 | "src.4", "src.3", "src.2", "src.1", "src.0", | |
4dfc6f8b | 1381 | "dvc.0", "dvc.1", |
951431e0 | 1382 | "clk_a", "clk_b", "clk_c", "clk_i"; |
f1ba73ea | 1383 | power-domains = <&sysc R8A7793_PD_ALWAYS_ON>; |
951431e0 SH |
1384 | |
1385 | status = "disabled"; | |
1386 | ||
4dfc6f8b | 1387 | rcar_sound,dvc { |
ad53f5f0 | 1388 | dvc0: dvc-0 { |
f418cbb6 SH |
1389 | dmas = <&audma0 0xbc>; |
1390 | dma-names = "tx"; | |
1391 | }; | |
ad53f5f0 | 1392 | dvc1: dvc-1 { |
f418cbb6 SH |
1393 | dmas = <&audma0 0xbe>; |
1394 | dma-names = "tx"; | |
1395 | }; | |
4dfc6f8b | 1396 | }; |
f418cbb6 | 1397 | |
951431e0 | 1398 | rcar_sound,src { |
ad53f5f0 | 1399 | src0: src-0 { |
f418cbb6 SH |
1400 | interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>; |
1401 | dmas = <&audma0 0x85>, <&audma1 0x9a>; | |
1402 | dma-names = "rx", "tx"; | |
1403 | }; | |
ad53f5f0 | 1404 | src1: src-1 { |
f418cbb6 SH |
1405 | interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
1406 | dmas = <&audma0 0x87>, <&audma1 0x9c>; | |
1407 | dma-names = "rx", "tx"; | |
1408 | }; | |
ad53f5f0 | 1409 | src2: src-2 { |
f418cbb6 SH |
1410 | interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
1411 | dmas = <&audma0 0x89>, <&audma1 0x9e>; | |
1412 | dma-names = "rx", "tx"; | |
1413 | }; | |
ad53f5f0 | 1414 | src3: src-3 { |
f418cbb6 SH |
1415 | interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
1416 | dmas = <&audma0 0x8b>, <&audma1 0xa0>; | |
1417 | dma-names = "rx", "tx"; | |
1418 | }; | |
ad53f5f0 | 1419 | src4: src-4 { |
f418cbb6 SH |
1420 | interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
1421 | dmas = <&audma0 0x8d>, <&audma1 0xb0>; | |
1422 | dma-names = "rx", "tx"; | |
1423 | }; | |
ad53f5f0 | 1424 | src5: src-5 { |
f418cbb6 SH |
1425 | interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
1426 | dmas = <&audma0 0x8f>, <&audma1 0xb2>; | |
1427 | dma-names = "rx", "tx"; | |
1428 | }; | |
ad53f5f0 | 1429 | src6: src-6 { |
f418cbb6 SH |
1430 | interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
1431 | dmas = <&audma0 0x91>, <&audma1 0xb4>; | |
1432 | dma-names = "rx", "tx"; | |
1433 | }; | |
ad53f5f0 | 1434 | src7: src-7 { |
f418cbb6 SH |
1435 | interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; |
1436 | dmas = <&audma0 0x93>, <&audma1 0xb6>; | |
1437 | dma-names = "rx", "tx"; | |
1438 | }; | |
ad53f5f0 | 1439 | src8: src-8 { |
f418cbb6 SH |
1440 | interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; |
1441 | dmas = <&audma0 0x95>, <&audma1 0xb8>; | |
1442 | dma-names = "rx", "tx"; | |
1443 | }; | |
ad53f5f0 | 1444 | src9: src-9 { |
f418cbb6 SH |
1445 | interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>; |
1446 | dmas = <&audma0 0x97>, <&audma1 0xba>; | |
1447 | dma-names = "rx", "tx"; | |
1448 | }; | |
951431e0 SH |
1449 | }; |
1450 | ||
1451 | rcar_sound,ssi { | |
ad53f5f0 | 1452 | ssi0: ssi-0 { |
951431e0 | 1453 | interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1454 | dmas = <&audma0 0x01>, <&audma1 0x02>, <&audma0 0x15>, <&audma1 0x16>; |
1455 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1456 | }; |
ad53f5f0 | 1457 | ssi1: ssi-1 { |
951431e0 | 1458 | interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1459 | dmas = <&audma0 0x03>, <&audma1 0x04>, <&audma0 0x49>, <&audma1 0x4a>; |
1460 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1461 | }; |
ad53f5f0 | 1462 | ssi2: ssi-2 { |
951431e0 | 1463 | interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1464 | dmas = <&audma0 0x05>, <&audma1 0x06>, <&audma0 0x63>, <&audma1 0x64>; |
1465 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1466 | }; |
ad53f5f0 | 1467 | ssi3: ssi-3 { |
951431e0 | 1468 | interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1469 | dmas = <&audma0 0x07>, <&audma1 0x08>, <&audma0 0x6f>, <&audma1 0x70>; |
1470 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1471 | }; |
ad53f5f0 | 1472 | ssi4: ssi-4 { |
951431e0 | 1473 | interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1474 | dmas = <&audma0 0x09>, <&audma1 0x0a>, <&audma0 0x71>, <&audma1 0x72>; |
1475 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1476 | }; |
ad53f5f0 | 1477 | ssi5: ssi-5 { |
951431e0 | 1478 | interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1479 | dmas = <&audma0 0x0b>, <&audma1 0x0c>, <&audma0 0x73>, <&audma1 0x74>; |
1480 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1481 | }; |
ad53f5f0 | 1482 | ssi6: ssi-6 { |
951431e0 | 1483 | interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1484 | dmas = <&audma0 0x0d>, <&audma1 0x0e>, <&audma0 0x75>, <&audma1 0x76>; |
1485 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1486 | }; |
ad53f5f0 | 1487 | ssi7: ssi-7 { |
951431e0 | 1488 | interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1489 | dmas = <&audma0 0x0f>, <&audma1 0x10>, <&audma0 0x79>, <&audma1 0x7a>; |
1490 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1491 | }; |
ad53f5f0 | 1492 | ssi8: ssi-8 { |
951431e0 | 1493 | interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1494 | dmas = <&audma0 0x11>, <&audma1 0x12>, <&audma0 0x7b>, <&audma1 0x7c>; |
1495 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 | 1496 | }; |
ad53f5f0 | 1497 | ssi9: ssi-9 { |
951431e0 | 1498 | interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
f418cbb6 SH |
1499 | dmas = <&audma0 0x13>, <&audma1 0x14>, <&audma0 0x7d>, <&audma1 0x7e>; |
1500 | dma-names = "rx", "tx", "rxu", "txu"; | |
951431e0 SH |
1501 | }; |
1502 | }; | |
1503 | }; | |
0e03e8ae | 1504 | }; |