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6bcf60f8 HS |
1 | /* |
2 | * Copyright (c) 2013 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <dt-bindings/gpio/gpio.h> | |
17 | #include <dt-bindings/pinctrl/rockchip.h> | |
18 | #include "rk3xxx.dtsi" | |
19 | #include "rk3188-clocks.dtsi" | |
20 | ||
21 | / { | |
22 | compatible = "rockchip,rk3188"; | |
23 | ||
24 | cpus { | |
25 | #address-cells = <1>; | |
26 | #size-cells = <0>; | |
27 | ||
28 | cpu@0 { | |
29 | device_type = "cpu"; | |
30 | compatible = "arm,cortex-a9"; | |
31 | next-level-cache = <&L2>; | |
32 | reg = <0x0>; | |
33 | }; | |
34 | cpu@1 { | |
35 | device_type = "cpu"; | |
36 | compatible = "arm,cortex-a9"; | |
37 | next-level-cache = <&L2>; | |
38 | reg = <0x1>; | |
39 | }; | |
40 | cpu@2 { | |
41 | device_type = "cpu"; | |
42 | compatible = "arm,cortex-a9"; | |
43 | next-level-cache = <&L2>; | |
44 | reg = <0x2>; | |
45 | }; | |
46 | cpu@3 { | |
47 | device_type = "cpu"; | |
48 | compatible = "arm,cortex-a9"; | |
49 | next-level-cache = <&L2>; | |
50 | reg = <0x3>; | |
51 | }; | |
52 | }; | |
53 | ||
54 | soc { | |
55 | global-timer@1013c200 { | |
56 | interrupts = <GIC_PPI 11 0xf04>; | |
57 | }; | |
58 | ||
59 | local-timer@1013c600 { | |
60 | interrupts = <GIC_PPI 13 0xf04>; | |
61 | }; | |
62 | ||
de18e014 HS |
63 | sram: sram@10080000 { |
64 | compatible = "mmio-sram"; | |
65 | reg = <0x10080000 0x8000>; | |
66 | #address-cells = <1>; | |
67 | #size-cells = <1>; | |
68 | ranges = <0 0x10080000 0x8000>; | |
69 | ||
70 | smp-sram@0 { | |
71 | compatible = "rockchip,rk3066-smp-sram"; | |
72 | reg = <0x0 0x50>; | |
73 | }; | |
74 | }; | |
75 | ||
6bcf60f8 HS |
76 | pinctrl@20008000 { |
77 | compatible = "rockchip,rk3188-pinctrl"; | |
78 | reg = <0x20008000 0xa0>, | |
79 | <0x20008164 0x1a0>; | |
80 | reg-names = "base", "pull"; | |
81 | #address-cells = <1>; | |
82 | #size-cells = <1>; | |
83 | ranges; | |
84 | ||
85 | gpio0: gpio0@0x2000a000 { | |
86 | compatible = "rockchip,rk3188-gpio-bank0"; | |
87 | reg = <0x2000a000 0x100>, | |
88 | <0x20004064 0x8>; | |
89 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
90 | clocks = <&clk_gates8 9>; | |
91 | ||
92 | gpio-controller; | |
93 | #gpio-cells = <2>; | |
94 | ||
95 | interrupt-controller; | |
96 | #interrupt-cells = <2>; | |
97 | }; | |
98 | ||
99 | gpio1: gpio1@0x2003c000 { | |
100 | compatible = "rockchip,gpio-bank"; | |
101 | reg = <0x2003c000 0x100>; | |
102 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
103 | clocks = <&clk_gates8 10>; | |
104 | ||
105 | gpio-controller; | |
106 | #gpio-cells = <2>; | |
107 | ||
108 | interrupt-controller; | |
109 | #interrupt-cells = <2>; | |
110 | }; | |
111 | ||
112 | gpio2: gpio2@2003e000 { | |
113 | compatible = "rockchip,gpio-bank"; | |
114 | reg = <0x2003e000 0x100>; | |
115 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
116 | clocks = <&clk_gates8 11>; | |
117 | ||
118 | gpio-controller; | |
119 | #gpio-cells = <2>; | |
120 | ||
121 | interrupt-controller; | |
122 | #interrupt-cells = <2>; | |
123 | }; | |
124 | ||
125 | gpio3: gpio3@20080000 { | |
126 | compatible = "rockchip,gpio-bank"; | |
127 | reg = <0x20080000 0x100>; | |
128 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
129 | clocks = <&clk_gates8 12>; | |
130 | ||
131 | gpio-controller; | |
132 | #gpio-cells = <2>; | |
133 | ||
134 | interrupt-controller; | |
135 | #interrupt-cells = <2>; | |
136 | }; | |
137 | ||
138 | pcfg_pull_up: pcfg_pull_up { | |
139 | bias-pull-up; | |
140 | }; | |
141 | ||
142 | pcfg_pull_down: pcfg_pull_down { | |
143 | bias-pull-down; | |
144 | }; | |
145 | ||
146 | pcfg_pull_none: pcfg_pull_none { | |
147 | bias-disable; | |
148 | }; | |
149 | ||
150 | uart0 { | |
151 | uart0_xfer: uart0-xfer { | |
152 | rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_none>, | |
153 | <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; | |
154 | }; | |
155 | ||
156 | uart0_cts: uart0-cts { | |
157 | rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; | |
158 | }; | |
159 | ||
160 | uart0_rts: uart0-rts { | |
161 | rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; | |
162 | }; | |
163 | }; | |
164 | ||
165 | uart1 { | |
166 | uart1_xfer: uart1-xfer { | |
167 | rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_none>, | |
168 | <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; | |
169 | }; | |
170 | ||
171 | uart1_cts: uart1-cts { | |
172 | rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; | |
173 | }; | |
174 | ||
175 | uart1_rts: uart1-rts { | |
176 | rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; | |
177 | }; | |
178 | }; | |
179 | ||
180 | uart2 { | |
181 | uart2_xfer: uart2-xfer { | |
182 | rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_none>, | |
183 | <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; | |
184 | }; | |
185 | /* no rts / cts for uart2 */ | |
186 | }; | |
187 | ||
188 | uart3 { | |
189 | uart3_xfer: uart3-xfer { | |
190 | rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_none>, | |
191 | <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; | |
192 | }; | |
193 | ||
194 | uart3_cts: uart3-cts { | |
195 | rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; | |
196 | }; | |
197 | ||
198 | uart3_rts: uart3-rts { | |
199 | rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; | |
200 | }; | |
201 | }; | |
202 | ||
203 | sd0 { | |
204 | sd0_clk: sd0-clk { | |
205 | rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; | |
206 | }; | |
207 | ||
208 | sd0_cmd: sd0-cmd { | |
209 | rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; | |
210 | }; | |
211 | ||
212 | sd0_cd: sd0-cd { | |
213 | rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; | |
214 | }; | |
215 | ||
216 | sd0_wp: sd0-wp { | |
217 | rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; | |
218 | }; | |
219 | ||
220 | sd0_pwr: sd0-pwr { | |
221 | rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; | |
222 | }; | |
223 | ||
224 | sd0_bus1: sd0-bus-width1 { | |
225 | rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; | |
226 | }; | |
227 | ||
228 | sd0_bus4: sd0-bus-width4 { | |
229 | rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, | |
230 | <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, | |
231 | <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, | |
232 | <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; | |
233 | }; | |
234 | }; | |
235 | ||
236 | sd1 { | |
237 | sd1_clk: sd1-clk { | |
238 | rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; | |
239 | }; | |
240 | ||
241 | sd1_cmd: sd1-cmd { | |
242 | rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; | |
243 | }; | |
244 | ||
245 | sd1_cd: sd1-cd { | |
246 | rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; | |
247 | }; | |
248 | ||
249 | sd1_wp: sd1-wp { | |
250 | rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; | |
251 | }; | |
252 | ||
253 | sd1_bus1: sd1-bus-width1 { | |
254 | rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; | |
255 | }; | |
256 | ||
257 | sd1_bus4: sd1-bus-width4 { | |
258 | rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, | |
259 | <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, | |
260 | <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, | |
261 | <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; | |
262 | }; | |
263 | }; | |
264 | }; | |
265 | }; | |
266 | }; |