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6bcf60f8 HS |
1 | /* |
2 | * Copyright (c) 2013 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2 of the License, or | |
8 | * (at your option) any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | */ | |
15 | ||
16 | #include <dt-bindings/gpio/gpio.h> | |
17 | #include <dt-bindings/pinctrl/rockchip.h> | |
b13d2a7b | 18 | #include <dt-bindings/clock/rk3188-cru.h> |
6bcf60f8 | 19 | #include "rk3xxx.dtsi" |
6bcf60f8 HS |
20 | |
21 | / { | |
22 | compatible = "rockchip,rk3188"; | |
23 | ||
24 | cpus { | |
25 | #address-cells = <1>; | |
26 | #size-cells = <0>; | |
26ab69cb | 27 | enable-method = "rockchip,rk3066-smp"; |
6bcf60f8 HS |
28 | |
29 | cpu@0 { | |
30 | device_type = "cpu"; | |
31 | compatible = "arm,cortex-a9"; | |
32 | next-level-cache = <&L2>; | |
33 | reg = <0x0>; | |
34 | }; | |
35 | cpu@1 { | |
36 | device_type = "cpu"; | |
37 | compatible = "arm,cortex-a9"; | |
38 | next-level-cache = <&L2>; | |
39 | reg = <0x1>; | |
40 | }; | |
41 | cpu@2 { | |
42 | device_type = "cpu"; | |
43 | compatible = "arm,cortex-a9"; | |
44 | next-level-cache = <&L2>; | |
45 | reg = <0x2>; | |
46 | }; | |
47 | cpu@3 { | |
48 | device_type = "cpu"; | |
49 | compatible = "arm,cortex-a9"; | |
50 | next-level-cache = <&L2>; | |
51 | reg = <0x3>; | |
52 | }; | |
53 | }; | |
54 | ||
c3030d30 HS |
55 | sram: sram@10080000 { |
56 | compatible = "mmio-sram"; | |
57 | reg = <0x10080000 0x8000>; | |
58 | #address-cells = <1>; | |
59 | #size-cells = <1>; | |
60 | ranges = <0 0x10080000 0x8000>; | |
61 | ||
62 | smp-sram@0 { | |
63 | compatible = "rockchip,rk3066-smp-sram"; | |
64 | reg = <0x0 0x50>; | |
6bcf60f8 | 65 | }; |
c3030d30 HS |
66 | }; |
67 | ||
68 | cru: clock-controller@20000000 { | |
69 | compatible = "rockchip,rk3188-cru"; | |
70 | reg = <0x20000000 0x1000>; | |
71 | rockchip,grf = <&grf>; | |
72 | ||
73 | #clock-cells = <1>; | |
74 | #reset-cells = <1>; | |
75 | }; | |
6bcf60f8 | 76 | |
e40b43d6 | 77 | pinctrl: pinctrl@20008000 { |
c3030d30 HS |
78 | compatible = "rockchip,rk3188-pinctrl"; |
79 | rockchip,grf = <&grf>; | |
80 | rockchip,pmu = <&pmu>; | |
81 | ||
82 | #address-cells = <1>; | |
83 | #size-cells = <1>; | |
84 | ranges; | |
85 | ||
86 | gpio0: gpio0@0x2000a000 { | |
87 | compatible = "rockchip,rk3188-gpio-bank0"; | |
88 | reg = <0x2000a000 0x100>; | |
89 | interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
90 | clocks = <&cru PCLK_GPIO0>; | |
91 | ||
92 | gpio-controller; | |
93 | #gpio-cells = <2>; | |
94 | ||
95 | interrupt-controller; | |
96 | #interrupt-cells = <2>; | |
6bcf60f8 HS |
97 | }; |
98 | ||
c3030d30 HS |
99 | gpio1: gpio1@0x2003c000 { |
100 | compatible = "rockchip,gpio-bank"; | |
101 | reg = <0x2003c000 0x100>; | |
102 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
103 | clocks = <&cru PCLK_GPIO1>; | |
de18e014 | 104 | |
c3030d30 HS |
105 | gpio-controller; |
106 | #gpio-cells = <2>; | |
107 | ||
108 | interrupt-controller; | |
109 | #interrupt-cells = <2>; | |
de18e014 HS |
110 | }; |
111 | ||
c3030d30 HS |
112 | gpio2: gpio2@2003e000 { |
113 | compatible = "rockchip,gpio-bank"; | |
114 | reg = <0x2003e000 0x100>; | |
115 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
116 | clocks = <&cru PCLK_GPIO2>; | |
117 | ||
118 | gpio-controller; | |
119 | #gpio-cells = <2>; | |
b13d2a7b | 120 | |
c3030d30 HS |
121 | interrupt-controller; |
122 | #interrupt-cells = <2>; | |
b13d2a7b HS |
123 | }; |
124 | ||
c3030d30 HS |
125 | gpio3: gpio3@20080000 { |
126 | compatible = "rockchip,gpio-bank"; | |
127 | reg = <0x20080000 0x100>; | |
128 | interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
129 | clocks = <&cru PCLK_GPIO3>; | |
56f2b894 | 130 | |
c3030d30 HS |
131 | gpio-controller; |
132 | #gpio-cells = <2>; | |
6bcf60f8 | 133 | |
c3030d30 HS |
134 | interrupt-controller; |
135 | #interrupt-cells = <2>; | |
136 | }; | |
6bcf60f8 | 137 | |
c3030d30 HS |
138 | pcfg_pull_up: pcfg_pull_up { |
139 | bias-pull-up; | |
140 | }; | |
6bcf60f8 | 141 | |
c3030d30 HS |
142 | pcfg_pull_down: pcfg_pull_down { |
143 | bias-pull-down; | |
144 | }; | |
6bcf60f8 | 145 | |
c3030d30 HS |
146 | pcfg_pull_none: pcfg_pull_none { |
147 | bias-disable; | |
148 | }; | |
6bcf60f8 | 149 | |
c3030d30 HS |
150 | uart0 { |
151 | uart0_xfer: uart0-xfer { | |
152 | rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_up>, | |
153 | <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_none>; | |
154 | }; | |
6bcf60f8 | 155 | |
c3030d30 HS |
156 | uart0_cts: uart0-cts { |
157 | rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
158 | }; |
159 | ||
c3030d30 HS |
160 | uart0_rts: uart0-rts { |
161 | rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_none>; | |
162 | }; | |
163 | }; | |
6bcf60f8 | 164 | |
c3030d30 HS |
165 | uart1 { |
166 | uart1_xfer: uart1-xfer { | |
167 | rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_up>, | |
168 | <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_none>; | |
169 | }; | |
6bcf60f8 | 170 | |
c3030d30 HS |
171 | uart1_cts: uart1-cts { |
172 | rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
173 | }; |
174 | ||
c3030d30 HS |
175 | uart1_rts: uart1-rts { |
176 | rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_none>; | |
177 | }; | |
178 | }; | |
6bcf60f8 | 179 | |
c3030d30 HS |
180 | uart2 { |
181 | uart2_xfer: uart2-xfer { | |
182 | rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_up>, | |
183 | <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_none>; | |
184 | }; | |
185 | /* no rts / cts for uart2 */ | |
186 | }; | |
6bcf60f8 | 187 | |
c3030d30 HS |
188 | uart3 { |
189 | uart3_xfer: uart3-xfer { | |
190 | rockchip,pins = <RK_GPIO1 10 RK_FUNC_1 &pcfg_pull_up>, | |
191 | <RK_GPIO1 11 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
192 | }; |
193 | ||
c3030d30 HS |
194 | uart3_cts: uart3-cts { |
195 | rockchip,pins = <RK_GPIO1 12 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
196 | }; |
197 | ||
c3030d30 HS |
198 | uart3_rts: uart3-rts { |
199 | rockchip,pins = <RK_GPIO1 13 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 | 200 | }; |
c3030d30 | 201 | }; |
6bcf60f8 | 202 | |
c3030d30 HS |
203 | sd0 { |
204 | sd0_clk: sd0-clk { | |
205 | rockchip,pins = <RK_GPIO3 2 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
206 | }; |
207 | ||
c3030d30 HS |
208 | sd0_cmd: sd0-cmd { |
209 | rockchip,pins = <RK_GPIO3 3 RK_FUNC_1 &pcfg_pull_none>; | |
210 | }; | |
6bcf60f8 | 211 | |
c3030d30 HS |
212 | sd0_cd: sd0-cd { |
213 | rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_none>; | |
214 | }; | |
6bcf60f8 | 215 | |
c3030d30 HS |
216 | sd0_wp: sd0-wp { |
217 | rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
218 | }; |
219 | ||
c3030d30 HS |
220 | sd0_pwr: sd0-pwr { |
221 | rockchip,pins = <RK_GPIO3 1 RK_FUNC_1 &pcfg_pull_none>; | |
222 | }; | |
6bcf60f8 | 223 | |
c3030d30 HS |
224 | sd0_bus1: sd0-bus-width1 { |
225 | rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>; | |
226 | }; | |
6bcf60f8 | 227 | |
c3030d30 HS |
228 | sd0_bus4: sd0-bus-width4 { |
229 | rockchip,pins = <RK_GPIO3 4 RK_FUNC_1 &pcfg_pull_none>, | |
230 | <RK_GPIO3 5 RK_FUNC_1 &pcfg_pull_none>, | |
231 | <RK_GPIO3 6 RK_FUNC_1 &pcfg_pull_none>, | |
232 | <RK_GPIO3 7 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 | 233 | }; |
c3030d30 | 234 | }; |
6bcf60f8 | 235 | |
c3030d30 HS |
236 | sd1 { |
237 | sd1_clk: sd1-clk { | |
238 | rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
239 | }; |
240 | ||
c3030d30 HS |
241 | sd1_cmd: sd1-cmd { |
242 | rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_none>; | |
243 | }; | |
6bcf60f8 | 244 | |
c3030d30 HS |
245 | sd1_cd: sd1-cd { |
246 | rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_none>; | |
247 | }; | |
6bcf60f8 | 248 | |
c3030d30 HS |
249 | sd1_wp: sd1-wp { |
250 | rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
251 | }; |
252 | ||
c3030d30 HS |
253 | sd1_bus1: sd1-bus-width1 { |
254 | rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
255 | }; |
256 | ||
c3030d30 HS |
257 | sd1_bus4: sd1-bus-width4 { |
258 | rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_none>, | |
259 | <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_none>, | |
260 | <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_none>, | |
261 | <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_none>; | |
6bcf60f8 HS |
262 | }; |
263 | }; | |
264 | }; | |
265 | }; | |
fcbbf965 HS |
266 | |
267 | &global_timer { | |
268 | interrupts = <GIC_PPI 11 0xf04>; | |
269 | }; | |
270 | ||
271 | &local_timer { | |
272 | interrupts = <GIC_PPI 13 0xf04>; | |
273 | }; | |
274 | ||
275 | &uart0 { | |
276 | pinctrl-names = "default"; | |
277 | pinctrl-0 = <&uart0_xfer>; | |
278 | }; | |
279 | ||
280 | &uart1 { | |
281 | pinctrl-names = "default"; | |
282 | pinctrl-0 = <&uart1_xfer>; | |
283 | }; | |
284 | ||
285 | &uart2 { | |
286 | pinctrl-names = "default"; | |
287 | pinctrl-0 = <&uart2_xfer>; | |
288 | }; | |
289 | ||
290 | &uart3 { | |
291 | pinctrl-names = "default"; | |
292 | pinctrl-0 = <&uart3_xfer>; | |
293 | }; |