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f75efdd7 HS |
1 | /* |
2 | * Copyright (c) 2013 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
d6250a1f HS |
5 | * This file is dual-licensed: you can use it either under the terms |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
f75efdd7 | 9 | * |
d6250a1f HS |
10 | * a) This file is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This file is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * Or, alternatively, | |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
f75efdd7 HS |
42 | */ |
43 | ||
44 | #include <dt-bindings/interrupt-controller/irq.h> | |
45 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
46 | #include "skeleton.dtsi" | |
47 | ||
48 | / { | |
49 | interrupt-parent = <&gic>; | |
50 | ||
9cdffd8c | 51 | aliases { |
b3e4b953 | 52 | ethernet0 = &emac; |
9cdffd8c HS |
53 | i2c0 = &i2c0; |
54 | i2c1 = &i2c1; | |
55 | i2c2 = &i2c2; | |
56 | i2c3 = &i2c3; | |
57 | i2c4 = &i2c4; | |
4ff4ae12 HS |
58 | mshc0 = &emmc; |
59 | mshc1 = &mmc0; | |
60 | mshc2 = &mmc1; | |
e5b0deda JC |
61 | serial0 = &uart0; |
62 | serial1 = &uart1; | |
63 | serial2 = &uart2; | |
64 | serial3 = &uart3; | |
39c2bd78 HS |
65 | spi0 = &spi0; |
66 | spi1 = &spi1; | |
9cdffd8c HS |
67 | }; |
68 | ||
ac42f481 | 69 | amba { |
2ef7d5f3 | 70 | compatible = "simple-bus"; |
ac42f481 HS |
71 | #address-cells = <1>; |
72 | #size-cells = <1>; | |
73 | ranges; | |
74 | ||
75 | dmac1_s: dma-controller@20018000 { | |
76 | compatible = "arm,pl330", "arm,primecell"; | |
77 | reg = <0x20018000 0x4000>; | |
78 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
79 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
80 | #dma-cells = <1>; | |
9bed8b41 | 81 | arm,pl330-broken-no-flushp; |
ac42f481 HS |
82 | clocks = <&cru ACLK_DMA1>; |
83 | clock-names = "apb_pclk"; | |
84 | }; | |
85 | ||
86 | dmac1_ns: dma-controller@2001c000 { | |
87 | compatible = "arm,pl330", "arm,primecell"; | |
88 | reg = <0x2001c000 0x4000>; | |
89 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
90 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
91 | #dma-cells = <1>; | |
9bed8b41 | 92 | arm,pl330-broken-no-flushp; |
ac42f481 HS |
93 | clocks = <&cru ACLK_DMA1>; |
94 | clock-names = "apb_pclk"; | |
95 | status = "disabled"; | |
96 | }; | |
97 | ||
98 | dmac2: dma-controller@20078000 { | |
99 | compatible = "arm,pl330", "arm,primecell"; | |
100 | reg = <0x20078000 0x4000>; | |
101 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
102 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
103 | #dma-cells = <1>; | |
9bed8b41 | 104 | arm,pl330-broken-no-flushp; |
ac42f481 HS |
105 | clocks = <&cru ACLK_DMA2>; |
106 | clock-names = "apb_pclk"; | |
107 | }; | |
108 | }; | |
109 | ||
560106c1 HS |
110 | xin24m: oscillator { |
111 | compatible = "fixed-clock"; | |
112 | clock-frequency = <24000000>; | |
113 | #clock-cells = <0>; | |
114 | clock-output-names = "xin24m"; | |
115 | }; | |
116 | ||
c3030d30 HS |
117 | L2: l2-cache-controller@10138000 { |
118 | compatible = "arm,pl310-cache"; | |
119 | reg = <0x10138000 0x1000>; | |
120 | cache-unified; | |
121 | cache-level = <2>; | |
122 | }; | |
123 | ||
ff84b90e HS |
124 | scu@1013c000 { |
125 | compatible = "arm,cortex-a9-scu"; | |
126 | reg = <0x1013c000 0x100>; | |
127 | }; | |
128 | ||
e40b43d6 | 129 | global_timer: global-timer@1013c200 { |
c3030d30 HS |
130 | compatible = "arm,cortex-a9-global-timer"; |
131 | reg = <0x1013c200 0x20>; | |
132 | interrupts = <GIC_PPI 11 0x304>; | |
133 | clocks = <&cru CORE_PERI>; | |
134 | }; | |
135 | ||
e40b43d6 | 136 | local_timer: local-timer@1013c600 { |
c3030d30 HS |
137 | compatible = "arm,cortex-a9-twd-timer"; |
138 | reg = <0x1013c600 0x20>; | |
139 | interrupts = <GIC_PPI 13 0x304>; | |
140 | clocks = <&cru CORE_PERI>; | |
141 | }; | |
142 | ||
ff84b90e HS |
143 | gic: interrupt-controller@1013d000 { |
144 | compatible = "arm,cortex-a9-gic"; | |
145 | interrupt-controller; | |
146 | #interrupt-cells = <3>; | |
147 | reg = <0x1013d000 0x1000>, | |
148 | <0x1013c100 0x0100>; | |
149 | }; | |
150 | ||
c3030d30 HS |
151 | uart0: serial@10124000 { |
152 | compatible = "snps,dw-apb-uart"; | |
153 | reg = <0x10124000 0x400>; | |
154 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
155 | reg-shift = <2>; | |
156 | reg-io-width = <1>; | |
69667ca2 HS |
157 | clock-names = "baudclk", "apb_pclk"; |
158 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
c3030d30 HS |
159 | status = "disabled"; |
160 | }; | |
161 | ||
162 | uart1: serial@10126000 { | |
163 | compatible = "snps,dw-apb-uart"; | |
164 | reg = <0x10126000 0x400>; | |
165 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
166 | reg-shift = <2>; | |
167 | reg-io-width = <1>; | |
69667ca2 HS |
168 | clock-names = "baudclk", "apb_pclk"; |
169 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
c3030d30 HS |
170 | status = "disabled"; |
171 | }; | |
172 | ||
fd14e6f9 HS |
173 | usb_otg: usb@10180000 { |
174 | compatible = "rockchip,rk3066-usb", "snps,dwc2"; | |
175 | reg = <0x10180000 0x40000>; | |
176 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
177 | clocks = <&cru HCLK_OTG0>; | |
178 | clock-names = "otg"; | |
ec32bd9f HS |
179 | dr_mode = "otg"; |
180 | g-np-tx-fifo-size = <16>; | |
181 | g-rx-fifo-size = <275>; | |
182 | g-tx-fifo-size = <256 128 128 64 64 32>; | |
183 | g-use-dma; | |
760bb977 HS |
184 | phys = <&usbphy0>; |
185 | phy-names = "usb2-phy"; | |
fd14e6f9 HS |
186 | status = "disabled"; |
187 | }; | |
188 | ||
189 | usb_host: usb@101c0000 { | |
190 | compatible = "snps,dwc2"; | |
191 | reg = <0x101c0000 0x40000>; | |
192 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
193 | clocks = <&cru HCLK_OTG1>; | |
194 | clock-names = "otg"; | |
ec32bd9f | 195 | dr_mode = "host"; |
760bb977 HS |
196 | phys = <&usbphy1>; |
197 | phy-names = "usb2-phy"; | |
fd14e6f9 HS |
198 | status = "disabled"; |
199 | }; | |
200 | ||
18ec91e1 RP |
201 | emac: ethernet@10204000 { |
202 | compatible = "snps,arc-emac"; | |
203 | reg = <0x10204000 0x3c>; | |
204 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
205 | #address-cells = <1>; | |
206 | #size-cells = <0>; | |
207 | ||
208 | rockchip,grf = <&grf>; | |
209 | ||
210 | clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; | |
211 | clock-names = "hclk", "macref"; | |
212 | max-speed = <100>; | |
213 | phy-mode = "rmii"; | |
214 | ||
215 | status = "disabled"; | |
216 | }; | |
217 | ||
e40b43d6 | 218 | mmc0: dwmmc@10214000 { |
c3030d30 HS |
219 | compatible = "rockchip,rk2928-dw-mshc"; |
220 | reg = <0x10214000 0x1000>; | |
221 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
c3030d30 HS |
222 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; |
223 | clock-names = "biu", "ciu"; | |
4c1e3ff7 | 224 | fifo-depth = <256>; |
c3030d30 HS |
225 | status = "disabled"; |
226 | }; | |
227 | ||
e40b43d6 | 228 | mmc1: dwmmc@10218000 { |
c3030d30 HS |
229 | compatible = "rockchip,rk2928-dw-mshc"; |
230 | reg = <0x10218000 0x1000>; | |
231 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
c3030d30 HS |
232 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; |
233 | clock-names = "biu", "ciu"; | |
4c1e3ff7 | 234 | fifo-depth = <256>; |
c3030d30 | 235 | status = "disabled"; |
f75efdd7 | 236 | }; |
ff84b90e | 237 | |
4ff4ae12 HS |
238 | emmc: dwmmc@1021c000 { |
239 | compatible = "rockchip,rk2928-dw-mshc"; | |
240 | reg = <0x1021c000 0x1000>; | |
241 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
4ff4ae12 HS |
242 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; |
243 | clock-names = "biu", "ciu"; | |
4c1e3ff7 | 244 | fifo-depth = <256>; |
4ff4ae12 HS |
245 | status = "disabled"; |
246 | }; | |
247 | ||
ff84b90e HS |
248 | pmu: pmu@20004000 { |
249 | compatible = "rockchip,rk3066-pmu", "syscon"; | |
250 | reg = <0x20004000 0x100>; | |
251 | }; | |
252 | ||
253 | grf: grf@20008000 { | |
254 | compatible = "syscon"; | |
255 | reg = <0x20008000 0x200>; | |
256 | }; | |
257 | ||
9cdffd8c HS |
258 | i2c0: i2c@2002d000 { |
259 | compatible = "rockchip,rk3066-i2c"; | |
260 | reg = <0x2002d000 0x1000>; | |
261 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
262 | #address-cells = <1>; | |
263 | #size-cells = <0>; | |
264 | ||
265 | rockchip,grf = <&grf>; | |
9cdffd8c HS |
266 | |
267 | clock-names = "i2c"; | |
268 | clocks = <&cru PCLK_I2C0>; | |
269 | ||
270 | status = "disabled"; | |
271 | }; | |
272 | ||
273 | i2c1: i2c@2002f000 { | |
274 | compatible = "rockchip,rk3066-i2c"; | |
275 | reg = <0x2002f000 0x1000>; | |
276 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
277 | #address-cells = <1>; | |
278 | #size-cells = <0>; | |
279 | ||
280 | rockchip,grf = <&grf>; | |
281 | ||
282 | clocks = <&cru PCLK_I2C1>; | |
283 | clock-names = "i2c"; | |
284 | ||
285 | status = "disabled"; | |
286 | }; | |
287 | ||
550c7f4e BG |
288 | pwm0: pwm@20030000 { |
289 | compatible = "rockchip,rk2928-pwm"; | |
290 | reg = <0x20030000 0x10>; | |
291 | #pwm-cells = <2>; | |
292 | clocks = <&cru PCLK_PWM01>; | |
293 | status = "disabled"; | |
294 | }; | |
295 | ||
296 | pwm1: pwm@20030010 { | |
297 | compatible = "rockchip,rk2928-pwm"; | |
298 | reg = <0x20030010 0x10>; | |
299 | #pwm-cells = <2>; | |
300 | clocks = <&cru PCLK_PWM01>; | |
301 | status = "disabled"; | |
302 | }; | |
303 | ||
eb2b9d47 HS |
304 | wdt: watchdog@2004c000 { |
305 | compatible = "snps,dw-wdt"; | |
306 | reg = <0x2004c000 0x100>; | |
307 | clocks = <&cru PCLK_WDT>; | |
308 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
309 | status = "disabled"; | |
310 | }; | |
311 | ||
550c7f4e BG |
312 | pwm2: pwm@20050020 { |
313 | compatible = "rockchip,rk2928-pwm"; | |
314 | reg = <0x20050020 0x10>; | |
315 | #pwm-cells = <2>; | |
316 | clocks = <&cru PCLK_PWM23>; | |
317 | status = "disabled"; | |
318 | }; | |
319 | ||
320 | pwm3: pwm@20050030 { | |
321 | compatible = "rockchip,rk2928-pwm"; | |
322 | reg = <0x20050030 0x10>; | |
323 | #pwm-cells = <2>; | |
324 | clocks = <&cru PCLK_PWM23>; | |
325 | status = "disabled"; | |
326 | }; | |
327 | ||
9cdffd8c HS |
328 | i2c2: i2c@20056000 { |
329 | compatible = "rockchip,rk3066-i2c"; | |
330 | reg = <0x20056000 0x1000>; | |
331 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
332 | #address-cells = <1>; | |
333 | #size-cells = <0>; | |
334 | ||
335 | rockchip,grf = <&grf>; | |
336 | ||
337 | clocks = <&cru PCLK_I2C2>; | |
338 | clock-names = "i2c"; | |
339 | ||
340 | status = "disabled"; | |
341 | }; | |
342 | ||
343 | i2c3: i2c@2005a000 { | |
344 | compatible = "rockchip,rk3066-i2c"; | |
345 | reg = <0x2005a000 0x1000>; | |
346 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
347 | #address-cells = <1>; | |
348 | #size-cells = <0>; | |
349 | ||
350 | rockchip,grf = <&grf>; | |
351 | ||
352 | clocks = <&cru PCLK_I2C3>; | |
353 | clock-names = "i2c"; | |
354 | ||
355 | status = "disabled"; | |
356 | }; | |
357 | ||
358 | i2c4: i2c@2005e000 { | |
359 | compatible = "rockchip,rk3066-i2c"; | |
360 | reg = <0x2005e000 0x1000>; | |
361 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
362 | #address-cells = <1>; | |
363 | #size-cells = <0>; | |
364 | ||
365 | rockchip,grf = <&grf>; | |
366 | ||
367 | clocks = <&cru PCLK_I2C4>; | |
368 | clock-names = "i2c"; | |
369 | ||
370 | status = "disabled"; | |
371 | }; | |
372 | ||
ff84b90e HS |
373 | uart2: serial@20064000 { |
374 | compatible = "snps,dw-apb-uart"; | |
375 | reg = <0x20064000 0x400>; | |
376 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
377 | reg-shift = <2>; | |
378 | reg-io-width = <1>; | |
69667ca2 HS |
379 | clock-names = "baudclk", "apb_pclk"; |
380 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
ff84b90e HS |
381 | status = "disabled"; |
382 | }; | |
383 | ||
384 | uart3: serial@20068000 { | |
385 | compatible = "snps,dw-apb-uart"; | |
386 | reg = <0x20068000 0x400>; | |
387 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
388 | reg-shift = <2>; | |
389 | reg-io-width = <1>; | |
69667ca2 HS |
390 | clock-names = "baudclk", "apb_pclk"; |
391 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
ff84b90e HS |
392 | status = "disabled"; |
393 | }; | |
f23a6179 HS |
394 | |
395 | saradc: saradc@2006c000 { | |
396 | compatible = "rockchip,saradc"; | |
397 | reg = <0x2006c000 0x100>; | |
398 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
399 | #io-channel-cells = <1>; | |
400 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
401 | clock-names = "saradc", "apb_pclk"; | |
402 | status = "disabled"; | |
403 | }; | |
39c2bd78 HS |
404 | |
405 | spi0: spi@20070000 { | |
406 | compatible = "rockchip,rk3066-spi"; | |
407 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
408 | clock-names = "spiclk", "apb_pclk"; | |
409 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
410 | reg = <0x20070000 0x1000>; | |
411 | #address-cells = <1>; | |
412 | #size-cells = <0>; | |
b3e3a7b2 JC |
413 | dmas = <&dmac2 10>, <&dmac2 11>; |
414 | dma-names = "tx", "rx"; | |
39c2bd78 HS |
415 | status = "disabled"; |
416 | }; | |
417 | ||
418 | spi1: spi@20074000 { | |
419 | compatible = "rockchip,rk3066-spi"; | |
420 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
421 | clock-names = "spiclk", "apb_pclk"; | |
422 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
423 | reg = <0x20074000 0x1000>; | |
424 | #address-cells = <1>; | |
425 | #size-cells = <0>; | |
b3e3a7b2 JC |
426 | dmas = <&dmac2 12>, <&dmac2 13>; |
427 | dma-names = "tx", "rx"; | |
39c2bd78 HS |
428 | status = "disabled"; |
429 | }; | |
f75efdd7 | 430 | }; |