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f75efdd7 HS |
1 | /* |
2 | * Copyright (c) 2013 MundoReader S.L. | |
3 | * Author: Heiko Stuebner <heiko@sntech.de> | |
4 | * | |
d6250a1f HS |
5 | * This file is dual-licensed: you can use it either under the terms |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
f75efdd7 | 9 | * |
d6250a1f HS |
10 | * a) This file is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This file is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * Or, alternatively, | |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
f75efdd7 HS |
42 | */ |
43 | ||
44 | #include <dt-bindings/interrupt-controller/irq.h> | |
45 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
46 | #include "skeleton.dtsi" | |
47 | ||
48 | / { | |
49 | interrupt-parent = <&gic>; | |
50 | ||
9cdffd8c HS |
51 | aliases { |
52 | i2c0 = &i2c0; | |
53 | i2c1 = &i2c1; | |
54 | i2c2 = &i2c2; | |
55 | i2c3 = &i2c3; | |
56 | i2c4 = &i2c4; | |
4ff4ae12 HS |
57 | mshc0 = &emmc; |
58 | mshc1 = &mmc0; | |
59 | mshc2 = &mmc1; | |
e5b0deda JC |
60 | serial0 = &uart0; |
61 | serial1 = &uart1; | |
62 | serial2 = &uart2; | |
63 | serial3 = &uart3; | |
39c2bd78 HS |
64 | spi0 = &spi0; |
65 | spi1 = &spi1; | |
9cdffd8c HS |
66 | }; |
67 | ||
ac42f481 HS |
68 | amba { |
69 | compatible = "arm,amba-bus"; | |
70 | #address-cells = <1>; | |
71 | #size-cells = <1>; | |
72 | ranges; | |
73 | ||
74 | dmac1_s: dma-controller@20018000 { | |
75 | compatible = "arm,pl330", "arm,primecell"; | |
76 | reg = <0x20018000 0x4000>; | |
77 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
78 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
79 | #dma-cells = <1>; | |
80 | clocks = <&cru ACLK_DMA1>; | |
81 | clock-names = "apb_pclk"; | |
82 | }; | |
83 | ||
84 | dmac1_ns: dma-controller@2001c000 { | |
85 | compatible = "arm,pl330", "arm,primecell"; | |
86 | reg = <0x2001c000 0x4000>; | |
87 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, | |
88 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; | |
89 | #dma-cells = <1>; | |
90 | clocks = <&cru ACLK_DMA1>; | |
91 | clock-names = "apb_pclk"; | |
92 | status = "disabled"; | |
93 | }; | |
94 | ||
95 | dmac2: dma-controller@20078000 { | |
96 | compatible = "arm,pl330", "arm,primecell"; | |
97 | reg = <0x20078000 0x4000>; | |
98 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, | |
99 | <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; | |
100 | #dma-cells = <1>; | |
101 | clocks = <&cru ACLK_DMA2>; | |
102 | clock-names = "apb_pclk"; | |
103 | }; | |
104 | }; | |
105 | ||
560106c1 HS |
106 | xin24m: oscillator { |
107 | compatible = "fixed-clock"; | |
108 | clock-frequency = <24000000>; | |
109 | #clock-cells = <0>; | |
110 | clock-output-names = "xin24m"; | |
111 | }; | |
112 | ||
c3030d30 HS |
113 | L2: l2-cache-controller@10138000 { |
114 | compatible = "arm,pl310-cache"; | |
115 | reg = <0x10138000 0x1000>; | |
116 | cache-unified; | |
117 | cache-level = <2>; | |
118 | }; | |
119 | ||
ff84b90e HS |
120 | scu@1013c000 { |
121 | compatible = "arm,cortex-a9-scu"; | |
122 | reg = <0x1013c000 0x100>; | |
123 | }; | |
124 | ||
e40b43d6 | 125 | global_timer: global-timer@1013c200 { |
c3030d30 HS |
126 | compatible = "arm,cortex-a9-global-timer"; |
127 | reg = <0x1013c200 0x20>; | |
128 | interrupts = <GIC_PPI 11 0x304>; | |
129 | clocks = <&cru CORE_PERI>; | |
130 | }; | |
131 | ||
e40b43d6 | 132 | local_timer: local-timer@1013c600 { |
c3030d30 HS |
133 | compatible = "arm,cortex-a9-twd-timer"; |
134 | reg = <0x1013c600 0x20>; | |
135 | interrupts = <GIC_PPI 13 0x304>; | |
136 | clocks = <&cru CORE_PERI>; | |
137 | }; | |
138 | ||
ff84b90e HS |
139 | gic: interrupt-controller@1013d000 { |
140 | compatible = "arm,cortex-a9-gic"; | |
141 | interrupt-controller; | |
142 | #interrupt-cells = <3>; | |
143 | reg = <0x1013d000 0x1000>, | |
144 | <0x1013c100 0x0100>; | |
145 | }; | |
146 | ||
c3030d30 HS |
147 | uart0: serial@10124000 { |
148 | compatible = "snps,dw-apb-uart"; | |
149 | reg = <0x10124000 0x400>; | |
150 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
151 | reg-shift = <2>; | |
152 | reg-io-width = <1>; | |
69667ca2 HS |
153 | clock-names = "baudclk", "apb_pclk"; |
154 | clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; | |
c3030d30 HS |
155 | status = "disabled"; |
156 | }; | |
157 | ||
158 | uart1: serial@10126000 { | |
159 | compatible = "snps,dw-apb-uart"; | |
160 | reg = <0x10126000 0x400>; | |
161 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
162 | reg-shift = <2>; | |
163 | reg-io-width = <1>; | |
69667ca2 HS |
164 | clock-names = "baudclk", "apb_pclk"; |
165 | clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; | |
c3030d30 HS |
166 | status = "disabled"; |
167 | }; | |
168 | ||
fd14e6f9 HS |
169 | usb_otg: usb@10180000 { |
170 | compatible = "rockchip,rk3066-usb", "snps,dwc2"; | |
171 | reg = <0x10180000 0x40000>; | |
172 | interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
173 | clocks = <&cru HCLK_OTG0>; | |
174 | clock-names = "otg"; | |
175 | status = "disabled"; | |
176 | }; | |
177 | ||
178 | usb_host: usb@101c0000 { | |
179 | compatible = "snps,dwc2"; | |
180 | reg = <0x101c0000 0x40000>; | |
181 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
182 | clocks = <&cru HCLK_OTG1>; | |
183 | clock-names = "otg"; | |
184 | status = "disabled"; | |
185 | }; | |
186 | ||
18ec91e1 RP |
187 | emac: ethernet@10204000 { |
188 | compatible = "snps,arc-emac"; | |
189 | reg = <0x10204000 0x3c>; | |
190 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; | |
191 | #address-cells = <1>; | |
192 | #size-cells = <0>; | |
193 | ||
194 | rockchip,grf = <&grf>; | |
195 | ||
196 | clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>; | |
197 | clock-names = "hclk", "macref"; | |
198 | max-speed = <100>; | |
199 | phy-mode = "rmii"; | |
200 | ||
201 | status = "disabled"; | |
202 | }; | |
203 | ||
e40b43d6 | 204 | mmc0: dwmmc@10214000 { |
c3030d30 HS |
205 | compatible = "rockchip,rk2928-dw-mshc"; |
206 | reg = <0x10214000 0x1000>; | |
207 | interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
c3030d30 HS |
208 | clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>; |
209 | clock-names = "biu", "ciu"; | |
4c1e3ff7 | 210 | fifo-depth = <256>; |
c3030d30 HS |
211 | status = "disabled"; |
212 | }; | |
213 | ||
e40b43d6 | 214 | mmc1: dwmmc@10218000 { |
c3030d30 HS |
215 | compatible = "rockchip,rk2928-dw-mshc"; |
216 | reg = <0x10218000 0x1000>; | |
217 | interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
c3030d30 HS |
218 | clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>; |
219 | clock-names = "biu", "ciu"; | |
4c1e3ff7 | 220 | fifo-depth = <256>; |
c3030d30 | 221 | status = "disabled"; |
f75efdd7 | 222 | }; |
ff84b90e | 223 | |
4ff4ae12 HS |
224 | emmc: dwmmc@1021c000 { |
225 | compatible = "rockchip,rk2928-dw-mshc"; | |
226 | reg = <0x1021c000 0x1000>; | |
227 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; | |
4ff4ae12 HS |
228 | clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>; |
229 | clock-names = "biu", "ciu"; | |
4c1e3ff7 | 230 | fifo-depth = <256>; |
4ff4ae12 HS |
231 | status = "disabled"; |
232 | }; | |
233 | ||
ff84b90e HS |
234 | pmu: pmu@20004000 { |
235 | compatible = "rockchip,rk3066-pmu", "syscon"; | |
236 | reg = <0x20004000 0x100>; | |
237 | }; | |
238 | ||
239 | grf: grf@20008000 { | |
240 | compatible = "syscon"; | |
241 | reg = <0x20008000 0x200>; | |
242 | }; | |
243 | ||
9cdffd8c HS |
244 | i2c0: i2c@2002d000 { |
245 | compatible = "rockchip,rk3066-i2c"; | |
246 | reg = <0x2002d000 0x1000>; | |
247 | interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
248 | #address-cells = <1>; | |
249 | #size-cells = <0>; | |
250 | ||
251 | rockchip,grf = <&grf>; | |
9cdffd8c HS |
252 | |
253 | clock-names = "i2c"; | |
254 | clocks = <&cru PCLK_I2C0>; | |
255 | ||
256 | status = "disabled"; | |
257 | }; | |
258 | ||
259 | i2c1: i2c@2002f000 { | |
260 | compatible = "rockchip,rk3066-i2c"; | |
261 | reg = <0x2002f000 0x1000>; | |
262 | interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; | |
263 | #address-cells = <1>; | |
264 | #size-cells = <0>; | |
265 | ||
266 | rockchip,grf = <&grf>; | |
267 | ||
268 | clocks = <&cru PCLK_I2C1>; | |
269 | clock-names = "i2c"; | |
270 | ||
271 | status = "disabled"; | |
272 | }; | |
273 | ||
550c7f4e BG |
274 | pwm0: pwm@20030000 { |
275 | compatible = "rockchip,rk2928-pwm"; | |
276 | reg = <0x20030000 0x10>; | |
277 | #pwm-cells = <2>; | |
278 | clocks = <&cru PCLK_PWM01>; | |
279 | status = "disabled"; | |
280 | }; | |
281 | ||
282 | pwm1: pwm@20030010 { | |
283 | compatible = "rockchip,rk2928-pwm"; | |
284 | reg = <0x20030010 0x10>; | |
285 | #pwm-cells = <2>; | |
286 | clocks = <&cru PCLK_PWM01>; | |
287 | status = "disabled"; | |
288 | }; | |
289 | ||
eb2b9d47 HS |
290 | wdt: watchdog@2004c000 { |
291 | compatible = "snps,dw-wdt"; | |
292 | reg = <0x2004c000 0x100>; | |
293 | clocks = <&cru PCLK_WDT>; | |
294 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; | |
295 | status = "disabled"; | |
296 | }; | |
297 | ||
550c7f4e BG |
298 | pwm2: pwm@20050020 { |
299 | compatible = "rockchip,rk2928-pwm"; | |
300 | reg = <0x20050020 0x10>; | |
301 | #pwm-cells = <2>; | |
302 | clocks = <&cru PCLK_PWM23>; | |
303 | status = "disabled"; | |
304 | }; | |
305 | ||
306 | pwm3: pwm@20050030 { | |
307 | compatible = "rockchip,rk2928-pwm"; | |
308 | reg = <0x20050030 0x10>; | |
309 | #pwm-cells = <2>; | |
310 | clocks = <&cru PCLK_PWM23>; | |
311 | status = "disabled"; | |
312 | }; | |
313 | ||
9cdffd8c HS |
314 | i2c2: i2c@20056000 { |
315 | compatible = "rockchip,rk3066-i2c"; | |
316 | reg = <0x20056000 0x1000>; | |
317 | interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
318 | #address-cells = <1>; | |
319 | #size-cells = <0>; | |
320 | ||
321 | rockchip,grf = <&grf>; | |
322 | ||
323 | clocks = <&cru PCLK_I2C2>; | |
324 | clock-names = "i2c"; | |
325 | ||
326 | status = "disabled"; | |
327 | }; | |
328 | ||
329 | i2c3: i2c@2005a000 { | |
330 | compatible = "rockchip,rk3066-i2c"; | |
331 | reg = <0x2005a000 0x1000>; | |
332 | interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
333 | #address-cells = <1>; | |
334 | #size-cells = <0>; | |
335 | ||
336 | rockchip,grf = <&grf>; | |
337 | ||
338 | clocks = <&cru PCLK_I2C3>; | |
339 | clock-names = "i2c"; | |
340 | ||
341 | status = "disabled"; | |
342 | }; | |
343 | ||
344 | i2c4: i2c@2005e000 { | |
345 | compatible = "rockchip,rk3066-i2c"; | |
346 | reg = <0x2005e000 0x1000>; | |
347 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; | |
348 | #address-cells = <1>; | |
349 | #size-cells = <0>; | |
350 | ||
351 | rockchip,grf = <&grf>; | |
352 | ||
353 | clocks = <&cru PCLK_I2C4>; | |
354 | clock-names = "i2c"; | |
355 | ||
356 | status = "disabled"; | |
357 | }; | |
358 | ||
ff84b90e HS |
359 | uart2: serial@20064000 { |
360 | compatible = "snps,dw-apb-uart"; | |
361 | reg = <0x20064000 0x400>; | |
362 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
363 | reg-shift = <2>; | |
364 | reg-io-width = <1>; | |
69667ca2 HS |
365 | clock-names = "baudclk", "apb_pclk"; |
366 | clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; | |
ff84b90e HS |
367 | status = "disabled"; |
368 | }; | |
369 | ||
370 | uart3: serial@20068000 { | |
371 | compatible = "snps,dw-apb-uart"; | |
372 | reg = <0x20068000 0x400>; | |
373 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
374 | reg-shift = <2>; | |
375 | reg-io-width = <1>; | |
69667ca2 HS |
376 | clock-names = "baudclk", "apb_pclk"; |
377 | clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; | |
ff84b90e HS |
378 | status = "disabled"; |
379 | }; | |
f23a6179 HS |
380 | |
381 | saradc: saradc@2006c000 { | |
382 | compatible = "rockchip,saradc"; | |
383 | reg = <0x2006c000 0x100>; | |
384 | interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
385 | #io-channel-cells = <1>; | |
386 | clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; | |
387 | clock-names = "saradc", "apb_pclk"; | |
388 | status = "disabled"; | |
389 | }; | |
39c2bd78 HS |
390 | |
391 | spi0: spi@20070000 { | |
392 | compatible = "rockchip,rk3066-spi"; | |
393 | clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; | |
394 | clock-names = "spiclk", "apb_pclk"; | |
395 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
396 | reg = <0x20070000 0x1000>; | |
397 | #address-cells = <1>; | |
398 | #size-cells = <0>; | |
b3e3a7b2 JC |
399 | dmas = <&dmac2 10>, <&dmac2 11>; |
400 | dma-names = "tx", "rx"; | |
39c2bd78 HS |
401 | status = "disabled"; |
402 | }; | |
403 | ||
404 | spi1: spi@20074000 { | |
405 | compatible = "rockchip,rk3066-spi"; | |
406 | clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; | |
407 | clock-names = "spiclk", "apb_pclk"; | |
408 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
409 | reg = <0x20074000 0x1000>; | |
410 | #address-cells = <1>; | |
411 | #size-cells = <0>; | |
b3e3a7b2 JC |
412 | dmas = <&dmac2 12>, <&dmac2 13>; |
413 | dma-names = "tx", "rx"; | |
39c2bd78 HS |
414 | status = "disabled"; |
415 | }; | |
f75efdd7 | 416 | }; |