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ARM: shmobile: r8a7790: tidyup SDHI register size on DTSI
[deliverable/linux.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
35d35aae 16#include <dt-bindings/clock/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
334394c0
AB		 61 clocks {
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
4753219d 67
334394c0
AB		 68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
4753219d 73
d2e8190b
BB		 74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <20000000>;
78 };
79 };
80
f04660e4
AB		 81 sram: sram@00300000 {
82 compatible = "mmio-sram";
83 reg = <0x00300000 0x20000>;
84 };
85
655ff266
LD		 86 ahb {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91
92 apb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges;
97
98 mmc0: mmc@f0000000 {
99 compatible = "atmel,hsmci";
100 reg = <0xf0000000 0x600>;
5e8b3bc3 101 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 102 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 103 dma-names = "rxtx";
655ff266
LD		 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
106 status = "disabled";
107 #address-cells = <1>;
108 #size-cells = <0>;
d2e8190b
BB		 109 clocks = <&mci0_clk>;
110 clock-names = "mci_clk";
655ff266
LD		 111 };
112
113 spi0: spi@f0004000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
b7ef678e 116 compatible = "atmel,at91rm9200-spi";
655ff266 117 reg = <0xf0004000 0x100>;
5e8b3bc3 118 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 119 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
120 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
121 dma-names = "tx", "rx";
655ff266
LD		 122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 124 clocks = <&spi0_clk>;
125 clock-names = "spi_clk";
655ff266
LD		 126 status = "disabled";
127 };
128
129 ssc0: ssc@f0008000 {
130 compatible = "atmel,at91sam9g45-ssc";
131 reg = <0xf0008000 0x4000>;
5e8b3bc3 132 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 133 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
134 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
135 dma-names = "tx", "rx";
655ff266
LD		 136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 138 clocks = <&ssc0_clk>;
139 clock-names = "pclk";
655ff266
LD		 140 status = "disabled";
141 };
142
655ff266
LD		 143 tcb0: timer@f0010000 {
144 compatible = "atmel,at91sam9x5-tcb";
145 reg = <0xf0010000 0x100>;
5e8b3bc3 146 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 147 clocks = <&tcb0_clk>;
148 clock-names = "t0_clk";
655ff266
LD		 149 };
150
151 i2c0: i2c@f0014000 {
152 compatible = "atmel,at91sam9x5-i2c";
153 reg = <0xf0014000 0x4000>;
5e8b3bc3 154 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 155 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
156 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 157 dma-names = "tx", "rx";
655ff266
LD		 158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_i2c0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
d2e8190b 162 clocks = <&twi0_clk>;
655ff266
LD		 163 status = "disabled";
164 };
165
166 i2c1: i2c@f0018000 {
167 compatible = "atmel,at91sam9x5-i2c";
168 reg = <0xf0018000 0x4000>;
5e8b3bc3 169 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 170 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
171 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 172 dma-names = "tx", "rx";
655ff266
LD		 173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c1>;
175 #address-cells = <1>;
176 #size-cells = <0>;
d2e8190b 177 clocks = <&twi1_clk>;
655ff266
LD		 178 status = "disabled";
179 };
180
181 usart0: serial@f001c000 {
182 compatible = "atmel,at91sam9260-usart";
183 reg = <0xf001c000 0x100>;
5e8b3bc3 184 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 185 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
186 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
187 dma-names = "tx", "rx";
655ff266
LD		 188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 190 clocks = <&usart0_clk>;
191 clock-names = "usart";
655ff266
LD		 192 status = "disabled";
193 };
194
195 usart1: serial@f0020000 {
196 compatible = "atmel,at91sam9260-usart";
197 reg = <0xf0020000 0x100>;
5e8b3bc3 198 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 199 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
200 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
201 dma-names = "tx", "rx";
655ff266
LD		 202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 204 clocks = <&usart1_clk>;
205 clock-names = "usart";
655ff266
LD		 206 status = "disabled";
207 };
208
f3ab0527
BS		 209 pwm0: pwm@f002c000 {
210 compatible = "atmel,sama5d3-pwm";
211 reg = <0xf002c000 0x300>;
212 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
213 #pwm-cells = <3>;
214 clocks = <&pwm_clk>;
215 status = "disabled";
216 };
655ff266 217
655ff266
LD		 218 isi: isi@f0034000 {
219 compatible = "atmel,at91sam9g45-isi";
220 reg = <0xf0034000 0x4000>;
5e8b3bc3 221 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
4dd32e6d
JW		 222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_isi_data_0_7>;
b00122f6
JW		 224 clocks = <&isi_clk>;
225 clock-names = "isi_clk";
655ff266 226 status = "disabled";
4dd32e6d
JW		 227 port {
228 #address-cells = <1>;
229 #size-cells = <0>;
230 };
655ff266
LD		 231 };
232
6ced9f4a
AB		 233 sfr: sfr@f0038000 {
234 compatible = "atmel,sama5d3-sfr", "syscon";
235 reg = <0xf0038000 0x60>;
236 };
237
655ff266
LD		 238 mmc1: mmc@f8000000 {
239 compatible = "atmel,hsmci";
240 reg = <0xf8000000 0x600>;
5e8b3bc3 241 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 242 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 243 dma-names = "rxtx";
655ff266
LD		 244 pinctrl-names = "default";
245 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
246 status = "disabled";
247 #address-cells = <1>;
248 #size-cells = <0>;
d2e8190b
BB		 249 clocks = <&mci1_clk>;
250 clock-names = "mci_clk";
655ff266
LD		 251 };
252
655ff266
LD		 253 spi1: spi@f8008000 {
254 #address-cells = <1>;
255 #size-cells = <0>;
b7ef678e 256 compatible = "atmel,at91rm9200-spi";
655ff266 257 reg = <0xf8008000 0x100>;
5e8b3bc3 258 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 259 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
260 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
261 dma-names = "tx", "rx";
655ff266
LD		 262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 264 clocks = <&spi1_clk>;
265 clock-names = "spi_clk";
655ff266
LD		 266 status = "disabled";
267 };
268
269 ssc1: ssc@f800c000 {
270 compatible = "atmel,at91sam9g45-ssc";
271 reg = <0xf800c000 0x4000>;
5e8b3bc3 272 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 273 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
274 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
275 dma-names = "tx", "rx";
655ff266
LD		 276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 278 clocks = <&ssc1_clk>;
279 clock-names = "pclk";
655ff266
LD		 280 status = "disabled";
281 };
282
655ff266 283 adc0: adc@f8018000 {
b3b84dec
AB		 284 #address-cells = <1>;
285 #size-cells = <0>;
9879b96d 286 compatible = "atmel,at91sam9x5-adc";
655ff266 287 reg = <0xf8018000 0x100>;
5e8b3bc3 288 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 289 pinctrl-names = "default";
290 pinctrl-0 = <
291 &pinctrl_adc0_adtrg
292 &pinctrl_adc0_ad0
293 &pinctrl_adc0_ad1
294 &pinctrl_adc0_ad2
295 &pinctrl_adc0_ad3
296 &pinctrl_adc0_ad4
297 &pinctrl_adc0_ad5
298 &pinctrl_adc0_ad6
299 &pinctrl_adc0_ad7
300 &pinctrl_adc0_ad8
301 &pinctrl_adc0_ad9
302 &pinctrl_adc0_ad10
303 &pinctrl_adc0_ad11
304 >;
d2e8190b
BB		 305 clocks = <&adc_clk>,
306 <&adc_op_clk>;
307 clock-names = "adc_clk", "adc_op_clk";
655ff266 308 atmel,adc-channels-used = <0xfff>;
655ff266 309 atmel,adc-startup-time = <40>;
b3b84dec 310 atmel,adc-use-external-triggers;
655ff266
LD		 311 atmel,adc-vref = <3000>;
312 atmel,adc-res = <10 12>;
313 atmel,adc-res-names = "lowres", "highres";
314 status = "disabled";
315
316 trigger@0 {
b3b84dec 317 reg = <0>;
655ff266
LD		 318 trigger-name = "external-rising";
319 trigger-value = <0x1>;
320 trigger-external;
321 };
322 trigger@1 {
b3b84dec 323 reg = <1>;
655ff266
LD		 324 trigger-name = "external-falling";
325 trigger-value = <0x2>;
326 trigger-external;
327 };
328 trigger@2 {
b3b84dec 329 reg = <2>;
655ff266
LD		 330 trigger-name = "external-any";
331 trigger-value = <0x3>;
332 trigger-external;
333 };
334 trigger@3 {
b3b84dec 335 reg = <3>;
655ff266
LD		 336 trigger-name = "continuous";
337 trigger-value = <0x6>;
338 };
339 };
340
655ff266
LD		 341 i2c2: i2c@f801c000 {
342 compatible = "atmel,at91sam9x5-i2c";
343 reg = <0xf801c000 0x4000>;
5e8b3bc3 344 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 345 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
346 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 347 dma-names = "tx", "rx";
557844ec
NF		 348 pinctrl-names = "default";
349 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 350 #address-cells = <1>;
351 #size-cells = <0>;
d2e8190b 352 clocks = <&twi2_clk>;
655ff266
LD		 353 status = "disabled";
354 };
355
356 usart2: serial@f8020000 {
357 compatible = "atmel,at91sam9260-usart";
358 reg = <0xf8020000 0x100>;
5e8b3bc3 359 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 360 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
361 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
362 dma-names = "tx", "rx";
655ff266
LD		 363 pinctrl-names = "default";
364 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 365 clocks = <&usart2_clk>;
366 clock-names = "usart";
655ff266
LD		 367 status = "disabled";
368 };
369
370 usart3: serial@f8024000 {
371 compatible = "atmel,at91sam9260-usart";
372 reg = <0xf8024000 0x100>;
5e8b3bc3 373 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 374 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
375 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
376 dma-names = "tx", "rx";
655ff266
LD		 377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 379 clocks = <&usart3_clk>;
380 clock-names = "usart";
655ff266
LD		 381 status = "disabled";
382 };
383
655ff266 384 sha@f8034000 {
c76f266d 385 compatible = "atmel,at91sam9g46-sha";
655ff266 386 reg = <0xf8034000 0x100>;
5e8b3bc3 387 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 388 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
389 dma-names = "tx";
4df4f446
BB		 390 clocks = <&sha_clk>;
391 clock-names = "sha_clk";
655ff266
LD		 392 };
393
394 aes@f8038000 {
c76f266d 395 compatible = "atmel,at91sam9g46-aes";
655ff266 396 reg = <0xf8038000 0x100>;
07f7d503 397 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 398 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
399 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
400 dma-names = "tx", "rx";
f68cd356
BB		 401 clocks = <&aes_clk>;
402 clock-names = "aes_clk";
655ff266
LD		 403 };
404
405 tdes@f803c000 {
c76f266d 406 compatible = "atmel,at91sam9g46-tdes";
655ff266 407 reg = <0xf803c000 0x100>;
5e8b3bc3 408 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 409 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
410 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
411 dma-names = "tx", "rx";
45e5c2cb
BB		 412 clocks = <&tdes_clk>;
413 clock-names = "tdes_clk";
655ff266
LD		 414 };
415
416 dma0: dma-controller@ffffe600 {
417 compatible = "atmel,at91sam9g45-dma";
418 reg = <0xffffe600 0x200>;
5e8b3bc3 419 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 420 #dma-cells = <2>;
d2e8190b
BB		 421 clocks = <&dma0_clk>;
422 clock-names = "dma_clk";
655ff266
LD		 423 };
424
425 dma1: dma-controller@ffffe800 {
426 compatible = "atmel,at91sam9g45-dma";
427 reg = <0xffffe800 0x200>;
5e8b3bc3 428 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 429 #dma-cells = <2>;
d2e8190b
BB		 430 clocks = <&dma1_clk>;
431 clock-names = "dma_clk";
655ff266
LD		 432 };
433
434 ramc0: ramc@ffffea00 {
063de897 435 compatible = "atmel,sama5d3-ddramc";
655ff266 436 reg = <0xffffea00 0x200>;
063de897
AB		 437 clocks = <&ddrck>, <&mpddr_clk>;
438 clock-names = "ddrck", "mpddr";
655ff266
LD		 439 };
440
441 dbgu: serial@ffffee00 {
442 compatible = "atmel,at91sam9260-usart";
443 reg = <0xffffee00 0x200>;
5e8b3bc3 444 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
d24cd783
LD		 445 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
446 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
447 dma-names = "tx", "rx";
655ff266
LD		 448 pinctrl-names = "default";
449 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 450 clocks = <&dbgu_clk>;
451 clock-names = "usart";
655ff266
LD		 452 status = "disabled";
453 };
454
455 aic: interrupt-controller@fffff000 {
456 #interrupt-cells = <3>;
457 compatible = "atmel,sama5d3-aic";
458 interrupt-controller;
459 reg = <0xfffff000 0x200>;
460 atmel,external-irqs = <47>;
461 };
462
463 pinctrl@fffff200 {
464 #address-cells = <1>;
465 #size-cells = <1>;
e0065cf7 466 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
655ff266
LD		 467 ranges = <0xfffff200 0xfffff200 0xa00>;
468 atmel,mux-mask = <
469 /* A B C */
470 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
471 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
472 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
473 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
474 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
475 >;
476
477 /* shared pinctrl settings */
478 adc0 {
479 pinctrl_adc0_adtrg: adc0_adtrg {
480 atmel,pins =
c9d0f317 481 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 482 };
483 pinctrl_adc0_ad0: adc0_ad0 {
484 atmel,pins =
c9d0f317 485 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 486 };
487 pinctrl_adc0_ad1: adc0_ad1 {
488 atmel,pins =
c9d0f317 489 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 490 };
491 pinctrl_adc0_ad2: adc0_ad2 {
492 atmel,pins =
c9d0f317 493 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 494 };
495 pinctrl_adc0_ad3: adc0_ad3 {
496 atmel,pins =
c9d0f317 497 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 498 };
499 pinctrl_adc0_ad4: adc0_ad4 {
500 atmel,pins =
c9d0f317 501 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 502 };
503 pinctrl_adc0_ad5: adc0_ad5 {
504 atmel,pins =
c9d0f317 505 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 506 };
507 pinctrl_adc0_ad6: adc0_ad6 {
508 atmel,pins =
c9d0f317 509 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 510 };
511 pinctrl_adc0_ad7: adc0_ad7 {
512 atmel,pins =
c9d0f317 513 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 514 };
515 pinctrl_adc0_ad8: adc0_ad8 {
516 atmel,pins =
c9d0f317 517 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 518 };
519 pinctrl_adc0_ad9: adc0_ad9 {
520 atmel,pins =
c9d0f317 521 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 522 };
523 pinctrl_adc0_ad10: adc0_ad10 {
524 atmel,pins =
c9d0f317 525 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 526 };
527 pinctrl_adc0_ad11: adc0_ad11 {
528 atmel,pins =
c9d0f317 529 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 530 };
531 };
532
655ff266
LD		 533 dbgu {
534 pinctrl_dbgu: dbgu-0 {
535 atmel,pins =
c9d0f317
JCPV		 536 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
537 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 538 };
539 };
540
541 i2c0 {
542 pinctrl_i2c0: i2c0-0 {
543 atmel,pins =
c9d0f317
JCPV		 544 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
545 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 546 };
547 };
548
549 i2c1 {
550 pinctrl_i2c1: i2c1-0 {
551 atmel,pins =
c9d0f317
JCPV		 552 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
553 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 554 };
555 };
556
557844ec
NF		 557 i2c2 {
558 pinctrl_i2c2: i2c2-0 {
559 atmel,pins =
560 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
561 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
562 };
563 };
564
655ff266 565 isi {
cbaa29c4 566 pinctrl_isi_data_0_7: isi-0-data-0-7 {
655ff266 567 atmel,pins =
c9d0f317
JCPV		 568 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
569 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
570 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
571 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
572 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
573 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
574 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
575 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
576 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
577 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
cbaa29c4
BS		 578 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
579 };
580
581 pinctrl_isi_data_8_9: isi-0-data-8-9 {
582 atmel,pins =
583 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
c9d0f317 584 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266 585 };
cbaa29c4 586
3d755488
BS		 587 pinctrl_isi_data_10_11: isi-0-data-10-11 {
588 atmel,pins =
589 <AT91_PIOC 27 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC27 periph C ISI_PD10, conflicts with SPI1_NPCS2, TWCK1 */
590 AT91_PIOC 26 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC26 periph C ISI_PD11, conflicts with SPI1_NPCS1, TWD1 */
591 };
655ff266
LD		 592 };
593
655ff266
LD		 594 mmc0 {
595 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
596 atmel,pins =
c9d0f317
JCPV		 597 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
598 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
599 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 600 };
601 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
602 atmel,pins =
c9d0f317
JCPV		 603 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
604 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
605 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 606 };
607 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
608 atmel,pins =
c9d0f317
JCPV		 609 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
610 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
611 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
612 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 613 };
614 };
615
616 mmc1 {
617 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
618 atmel,pins =
c9d0f317
JCPV		 619 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
620 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
621 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 622 };
623 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
624 atmel,pins =
c9d0f317
JCPV		 625 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
626 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
627 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 628 };
629 };
630
655ff266
LD		 631 nand0 {
632 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
633 atmel,pins =
c9d0f317
JCPV		 634 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
635 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 636 };
637 };
638
5eefd5f4
NF		 639 pwm0 {
640 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
641 atmel,pins =
642 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
643 };
644 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
645 atmel,pins =
646 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
647 };
648 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
649 atmel,pins =
650 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
651 };
652 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
653 atmel,pins =
654 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
655 };
656
657 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
658 atmel,pins =
659 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
660 };
661 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
662 atmel,pins =
663 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
664 };
665 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
666 atmel,pins =
667 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
668 };
669 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
670 atmel,pins =
671 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
672 };
673 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
674 atmel,pins =
675 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
676 };
677 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
678 atmel,pins =
679 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
680 };
681
682 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
683 atmel,pins =
684 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
685 };
686 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
687 atmel,pins =
688 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
689 };
690 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
691 atmel,pins =
692 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
693 };
694 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
695 atmel,pins =
696 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
697 };
698
699 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
700 atmel,pins =
701 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
702 };
703 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
704 atmel,pins =
705 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
706 };
707 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
708 atmel,pins =
709 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
710 };
711 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
712 atmel,pins =
713 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
714 };
715 };
716
655ff266
LD		 717 spi0 {
718 pinctrl_spi0: spi0-0 {
719 atmel,pins =
c9d0f317
JCPV		 720 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
721 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
722 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 723 };
724 };
725
726 spi1 {
727 pinctrl_spi1: spi1-0 {
728 atmel,pins =
c9d0f317
JCPV		 729 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
730 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
731 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 732 };
733 };
734
735 ssc0 {
736 pinctrl_ssc0_tx: ssc0_tx {
737 atmel,pins =
c9d0f317
JCPV		 738 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
739 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
740 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 741 };
742
743 pinctrl_ssc0_rx: ssc0_rx {
744 atmel,pins =
c9d0f317
JCPV		 745 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
746 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
747 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 748 };
749 };
750
751 ssc1 {
752 pinctrl_ssc1_tx: ssc1_tx {
753 atmel,pins =
c9d0f317
JCPV		 754 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
755 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
756 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 757 };
758
759 pinctrl_ssc1_rx: ssc1_rx {
760 atmel,pins =
c9d0f317
JCPV		 761 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
762 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
763 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 764 };
765 };
766
655ff266
LD		 767 usart0 {
768 pinctrl_usart0: usart0-0 {
769 atmel,pins =
c9d0f317
JCPV		 770 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
771 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 772 };
773
774 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
775 atmel,pins =
c9d0f317
JCPV		 776 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
777 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 778 };
779 };
780
781 usart1 {
782 pinctrl_usart1: usart1-0 {
783 atmel,pins =
c9d0f317
JCPV		 784 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
785 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 786 };
787
788 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
789 atmel,pins =
c9d0f317
JCPV		 790 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
791 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 792 };
793 };
794
795 usart2 {
796 pinctrl_usart2: usart2-0 {
797 atmel,pins =
c9d0f317
JCPV		 798 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
799 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 800 };
801
802 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
803 atmel,pins =
c9d0f317
JCPV		 804 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
805 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 806 };
807 };
808
809 usart3 {
810 pinctrl_usart3: usart3-0 {
811 atmel,pins =
c9d0f317
JCPV		 812 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
813 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 814 };
815
816 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
817 atmel,pins =
c9d0f317
JCPV		 818 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
819 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 820 };
821 };
c9d0f317
JCPV		 822
823
824 pioA: gpio@fffff200 {
825 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
826 reg = <0xfffff200 0x100>;
5e8b3bc3 827 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 828 #gpio-cells = <2>;
829 gpio-controller;
830 interrupt-controller;
831 #interrupt-cells = <2>;
d2e8190b 832 clocks = <&pioA_clk>;
c9d0f317
JCPV		 833 };
834
835 pioB: gpio@fffff400 {
836 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
837 reg = <0xfffff400 0x100>;
5e8b3bc3 838 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 839 #gpio-cells = <2>;
840 gpio-controller;
841 interrupt-controller;
842 #interrupt-cells = <2>;
d2e8190b 843 clocks = <&pioB_clk>;
c9d0f317
JCPV		 844 };
845
846 pioC: gpio@fffff600 {
847 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
848 reg = <0xfffff600 0x100>;
5e8b3bc3 849 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 850 #gpio-cells = <2>;
851 gpio-controller;
852 interrupt-controller;
853 #interrupt-cells = <2>;
d2e8190b 854 clocks = <&pioC_clk>;
c9d0f317
JCPV		 855 };
856
857 pioD: gpio@fffff800 {
858 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
859 reg = <0xfffff800 0x100>;
5e8b3bc3 860 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 861 #gpio-cells = <2>;
862 gpio-controller;
863 interrupt-controller;
864 #interrupt-cells = <2>;
d2e8190b 865 clocks = <&pioD_clk>;
c9d0f317
JCPV		 866 };
867
868 pioE: gpio@fffffa00 {
869 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
870 reg = <0xfffffa00 0x100>;
5e8b3bc3 871 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 872 #gpio-cells = <2>;
873 gpio-controller;
874 interrupt-controller;
875 #interrupt-cells = <2>;
d2e8190b 876 clocks = <&pioE_clk>;
c9d0f317 877 };
655ff266
LD		 878 };
879
880 pmc: pmc@fffffc00 {
d2e8190b 881 compatible = "atmel,sama5d3-pmc";
655ff266 882 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 883 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
884 interrupt-controller;
885 #address-cells = <1>;
886 #size-cells = <0>;
887 #interrupt-cells = <1>;
888
4753219d
BB		 889 main_rc_osc: main_rc_osc {
890 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
d2e8190b 891 #clock-cells = <0>;
4753219d
BB		 892 interrupt-parent = <&pmc>;
893 interrupts = <AT91_PMC_MOSCRCS>;
894 clock-frequency = <12000000>;
895 clock-accuracy = <50000000>;
d2e8190b
BB		 896 };
897
4753219d
BB		 898 main_osc: main_osc {
899 compatible = "atmel,at91rm9200-clk-main-osc";
d2e8190b
BB		 900 #clock-cells = <0>;
901 interrupt-parent = <&pmc>;
902 interrupts = <AT91_PMC_MOSCS>;
4753219d
BB		 903 clocks = <&main_xtal>;
904 };
905
906 main: mainck {
907 compatible = "atmel,at91sam9x5-clk-main";
908 #clock-cells = <0>;
909 interrupt-parent = <&pmc>;
910 interrupts = <AT91_PMC_MOSCSELS>;
911 clocks = <&main_rc_osc &main_osc>;
d2e8190b
BB		 912 };
913
914 plla: pllack {
915 compatible = "atmel,sama5d3-clk-pll";
916 #clock-cells = <0>;
917 interrupt-parent = <&pmc>;
918 interrupts = <AT91_PMC_LOCKA>;
919 clocks = <&main>;
920 reg = <0>;
921 atmel,clk-input-range = <8000000 50000000>;
922 #atmel,pll-clk-output-range-cells = <4>;
923 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
924 };
925
926 plladiv: plladivck {
927 compatible = "atmel,at91sam9x5-clk-plldiv";
928 #clock-cells = <0>;
929 clocks = <&plla>;
930 };
931
932 utmi: utmick {
933 compatible = "atmel,at91sam9x5-clk-utmi";
934 #clock-cells = <0>;
935 interrupt-parent = <&pmc>;
936 interrupts = <AT91_PMC_LOCKU>;
937 clocks = <&main>;
938 };
939
940 mck: masterck {
941 compatible = "atmel,at91sam9x5-clk-master";
942 #clock-cells = <0>;
943 interrupt-parent = <&pmc>;
944 interrupts = <AT91_PMC_MCKRDY>;
945 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
946 atmel,clk-output-range = <0 166000000>;
947 atmel,clk-divisors = <1 2 4 3>;
948 };
949
950 usb: usbck {
951 compatible = "atmel,at91sam9x5-clk-usb";
952 #clock-cells = <0>;
953 clocks = <&plladiv>, <&utmi>;
954 };
955
956 prog: progck {
957 compatible = "atmel,at91sam9x5-clk-programmable";
958 #address-cells = <1>;
959 #size-cells = <0>;
960 interrupt-parent = <&pmc>;
961 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
962
963 prog0: prog0 {
964 #clock-cells = <0>;
965 reg = <0>;
966 interrupts = <AT91_PMC_PCKRDY(0)>;
967 };
968
969 prog1: prog1 {
970 #clock-cells = <0>;
971 reg = <1>;
972 interrupts = <AT91_PMC_PCKRDY(1)>;
973 };
974
975 prog2: prog2 {
976 #clock-cells = <0>;
977 reg = <2>;
978 interrupts = <AT91_PMC_PCKRDY(2)>;
979 };
980 };
981
982 smd: smdclk {
983 compatible = "atmel,at91sam9x5-clk-smd";
984 #clock-cells = <0>;
985 clocks = <&plladiv>, <&utmi>;
986 };
987
988 systemck {
989 compatible = "atmel,at91rm9200-clk-system";
990 #address-cells = <1>;
991 #size-cells = <0>;
992
993 ddrck: ddrck {
994 #clock-cells = <0>;
995 reg = <2>;
996 clocks = <&mck>;
997 };
998
999 smdck: smdck {
1000 #clock-cells = <0>;
1001 reg = <4>;
1002 clocks = <&smd>;
1003 };
1004
1005 uhpck: uhpck {
1006 #clock-cells = <0>;
1007 reg = <6>;
1008 clocks = <&usb>;
1009 };
1010
1011 udpck: udpck {
1012 #clock-cells = <0>;
1013 reg = <7>;
1014 clocks = <&usb>;
1015 };
1016
1017 pck0: pck0 {
1018 #clock-cells = <0>;
1019 reg = <8>;
1020 clocks = <&prog0>;
1021 };
1022
1023 pck1: pck1 {
1024 #clock-cells = <0>;
1025 reg = <9>;
1026 clocks = <&prog1>;
1027 };
1028
1029 pck2: pck2 {
1030 #clock-cells = <0>;
1031 reg = <10>;
1032 clocks = <&prog2>;
1033 };
1034 };
1035
1036 periphck {
1037 compatible = "atmel,at91sam9x5-clk-peripheral";
1038 #address-cells = <1>;
1039 #size-cells = <0>;
1040 clocks = <&mck>;
1041
1042 dbgu_clk: dbgu_clk {
1043 #clock-cells = <0>;
1044 reg = <2>;
1045 };
1046
8a85ba20
AB		 1047 hsmc_clk: hsmc_clk {
1048 #clock-cells = <0>;
1049 reg = <5>;
1050 };
1051
d2e8190b
BB		 1052 pioA_clk: pioA_clk {
1053 #clock-cells = <0>;
1054 reg = <6>;
1055 };
1056
1057 pioB_clk: pioB_clk {
1058 #clock-cells = <0>;
1059 reg = <7>;
1060 };
1061
1062 pioC_clk: pioC_clk {
1063 #clock-cells = <0>;
1064 reg = <8>;
1065 };
1066
1067 pioD_clk: pioD_clk {
1068 #clock-cells = <0>;
1069 reg = <9>;
1070 };
1071
1072 pioE_clk: pioE_clk {
1073 #clock-cells = <0>;
1074 reg = <10>;
1075 };
1076
1077 usart0_clk: usart0_clk {
1078 #clock-cells = <0>;
1079 reg = <12>;
1080 atmel,clk-output-range = <0 66000000>;
1081 };
1082
1083 usart1_clk: usart1_clk {
1084 #clock-cells = <0>;
1085 reg = <13>;
1086 atmel,clk-output-range = <0 66000000>;
1087 };
1088
1089 usart2_clk: usart2_clk {
1090 #clock-cells = <0>;
1091 reg = <14>;
1092 atmel,clk-output-range = <0 66000000>;
1093 };
1094
1095 usart3_clk: usart3_clk {
1096 #clock-cells = <0>;
1097 reg = <15>;
1098 atmel,clk-output-range = <0 66000000>;
1099 };
1100
1101 twi0_clk: twi0_clk {
1102 reg = <18>;
1103 #clock-cells = <0>;
1104 atmel,clk-output-range = <0 16625000>;
1105 };
1106
1107 twi1_clk: twi1_clk {
1108 #clock-cells = <0>;
1109 reg = <19>;
1110 atmel,clk-output-range = <0 16625000>;
1111 };
1112
1113 twi2_clk: twi2_clk {
1114 #clock-cells = <0>;
1115 reg = <20>;
1116 atmel,clk-output-range = <0 16625000>;
1117 };
1118
1119 mci0_clk: mci0_clk {
1120 #clock-cells = <0>;
1121 reg = <21>;
1122 };
1123
1124 mci1_clk: mci1_clk {
1125 #clock-cells = <0>;
1126 reg = <22>;
1127 };
1128
1129 spi0_clk: spi0_clk {
1130 #clock-cells = <0>;
1131 reg = <24>;
1132 atmel,clk-output-range = <0 133000000>;
1133 };
1134
1135 spi1_clk: spi1_clk {
1136 #clock-cells = <0>;
1137 reg = <25>;
1138 atmel,clk-output-range = <0 133000000>;
1139 };
1140
1141 tcb0_clk: tcb0_clk {
1142 #clock-cells = <0>;
1143 reg = <26>;
1144 atmel,clk-output-range = <0 133000000>;
1145 };
1146
1147 pwm_clk: pwm_clk {
1148 #clock-cells = <0>;
1149 reg = <28>;
1150 };
1151
1152 adc_clk: adc_clk {
1153 #clock-cells = <0>;
1154 reg = <29>;
1155 atmel,clk-output-range = <0 66000000>;
1156 };
1157
1158 dma0_clk: dma0_clk {
1159 #clock-cells = <0>;
1160 reg = <30>;
1161 };
1162
1163 dma1_clk: dma1_clk {
1164 #clock-cells = <0>;
1165 reg = <31>;
1166 };
1167
1168 uhphs_clk: uhphs_clk {
1169 #clock-cells = <0>;
1170 reg = <32>;
1171 };
1172
1173 udphs_clk: udphs_clk {
1174 #clock-cells = <0>;
1175 reg = <33>;
1176 };
1177
1178 isi_clk: isi_clk {
1179 #clock-cells = <0>;
1180 reg = <37>;
1181 };
1182
1183 ssc0_clk: ssc0_clk {
1184 #clock-cells = <0>;
1185 reg = <38>;
1186 atmel,clk-output-range = <0 66000000>;
1187 };
1188
1189 ssc1_clk: ssc1_clk {
1190 #clock-cells = <0>;
1191 reg = <39>;
1192 atmel,clk-output-range = <0 66000000>;
1193 };
1194
1195 sha_clk: sha_clk {
1196 #clock-cells = <0>;
1197 reg = <42>;
1198 };
1199
1200 aes_clk: aes_clk {
1201 #clock-cells = <0>;
1202 reg = <43>;
1203 };
1204
1205 tdes_clk: tdes_clk {
1206 #clock-cells = <0>;
1207 reg = <44>;
1208 };
1209
1210 trng_clk: trng_clk {
1211 #clock-cells = <0>;
1212 reg = <45>;
1213 };
1214
1215 fuse_clk: fuse_clk {
1216 #clock-cells = <0>;
1217 reg = <48>;
1218 };
063de897
AB		 1219
1220 mpddr_clk: mpddr_clk {
1221 #clock-cells = <0>;
1222 reg = <49>;
1223 };
d2e8190b 1224 };
655ff266
LD		 1225 };
1226
1227 rstc@fffffe00 {
1228 compatible = "atmel,at91sam9g45-rstc";
1229 reg = <0xfffffe00 0x10>;
1230 };
1231
16aa7f1f
MR		 1232 shutdown-controller@fffffe10 {
1233 compatible = "atmel,at91sam9x5-shdwc";
1234 reg = <0xfffffe10 0x10>;
1235 };
1236
655ff266
LD		 1237 pit: timer@fffffe30 {
1238 compatible = "atmel,at91sam9260-pit";
1239 reg = <0xfffffe30 0xf>;
5e8b3bc3 1240 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1241 clocks = <&mck>;
655ff266
LD		 1242 };
1243
1244 watchdog@fffffe40 {
1245 compatible = "atmel,at91sam9260-wdt";
1246 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1247 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1248 atmel,watchdog-type = "hardware";
1249 atmel,reset-type = "all";
1250 atmel,dbg-halt;
1251 atmel,idle-halt;
655ff266
LD		 1252 status = "disabled";
1253 };
1254
4753219d
BB		 1255 sckc@fffffe50 {
1256 compatible = "atmel,at91sam9x5-sckc";
1257 reg = <0xfffffe50 0x4>;
1258
1259 slow_rc_osc: slow_rc_osc {
1260 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1261 #clock-cells = <0>;
1262 clock-frequency = <32768>;
1263 clock-accuracy = <50000000>;
1264 atmel,startup-time-usec = <75>;
1265 };
1266
1267 slow_osc: slow_osc {
1268 compatible = "atmel,at91sam9x5-clk-slow-osc";
1269 #clock-cells = <0>;
1270 clocks = <&slow_xtal>;
1271 atmel,startup-time-usec = <1200000>;
1272 };
1273
1274 clk32k: slowck {
1275 compatible = "atmel,at91sam9x5-clk-slow";
1276 #clock-cells = <0>;
1277 clocks = <&slow_rc_osc &slow_osc>;
1278 };
1279 };
1280
655ff266
LD		 1281 rtc@fffffeb0 {
1282 compatible = "atmel,at91rm9200-rtc";
1283 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1284 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1285 };
1286 };
1287
1288 usb0: gadget@00500000 {
1289 #address-cells = <1>;
1290 #size-cells = <0>;
1291 compatible = "atmel,at91sam9rl-udc";
1292 reg = <0x00500000 0x100000
1293 0xf8030000 0x4000>;
5e8b3bc3 1294 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1295 clocks = <&udphs_clk>, <&utmi>;
1296 clock-names = "pclk", "hclk";
655ff266
LD		 1297 status = "disabled";
1298
1299 ep0 {
1300 reg = <0>;
1301 atmel,fifo-size = <64>;
1302 atmel,nb-banks = <1>;
1303 };
1304
1305 ep1 {
1306 reg = <1>;
1307 atmel,fifo-size = <1024>;
1308 atmel,nb-banks = <3>;
1309 atmel,can-dma;
1310 atmel,can-isoc;
1311 };
1312
1313 ep2 {
1314 reg = <2>;
1315 atmel,fifo-size = <1024>;
1316 atmel,nb-banks = <3>;
1317 atmel,can-dma;
1318 atmel,can-isoc;
1319 };
1320
1321 ep3 {
1322 reg = <3>;
1323 atmel,fifo-size = <1024>;
1324 atmel,nb-banks = <2>;
1325 atmel,can-dma;
1326 };
1327
1328 ep4 {
1329 reg = <4>;
1330 atmel,fifo-size = <1024>;
1331 atmel,nb-banks = <2>;
1332 atmel,can-dma;
1333 };
1334
1335 ep5 {
1336 reg = <5>;
1337 atmel,fifo-size = <1024>;
1338 atmel,nb-banks = <2>;
1339 atmel,can-dma;
1340 };
1341
1342 ep6 {
1343 reg = <6>;
1344 atmel,fifo-size = <1024>;
1345 atmel,nb-banks = <2>;
1346 atmel,can-dma;
1347 };
1348
1349 ep7 {
1350 reg = <7>;
1351 atmel,fifo-size = <1024>;
1352 atmel,nb-banks = <2>;
1353 atmel,can-dma;
1354 };
1355
1356 ep8 {
1357 reg = <8>;
1358 atmel,fifo-size = <1024>;
1359 atmel,nb-banks = <2>;
1360 };
1361
1362 ep9 {
1363 reg = <9>;
1364 atmel,fifo-size = <1024>;
1365 atmel,nb-banks = <2>;
1366 };
1367
1368 ep10 {
1369 reg = <10>;
1370 atmel,fifo-size = <1024>;
1371 atmel,nb-banks = <2>;
1372 };
1373
1374 ep11 {
1375 reg = <11>;
1376 atmel,fifo-size = <1024>;
1377 atmel,nb-banks = <2>;
1378 };
1379
1380 ep12 {
1381 reg = <12>;
1382 atmel,fifo-size = <1024>;
1383 atmel,nb-banks = <2>;
1384 };
1385
1386 ep13 {
1387 reg = <13>;
1388 atmel,fifo-size = <1024>;
1389 atmel,nb-banks = <2>;
1390 };
1391
1392 ep14 {
1393 reg = <14>;
1394 atmel,fifo-size = <1024>;
1395 atmel,nb-banks = <2>;
1396 };
1397
1398 ep15 {
1399 reg = <15>;
1400 atmel,fifo-size = <1024>;
1401 atmel,nb-banks = <2>;
1402 };
1403 };
1404
1405 usb1: ohci@00600000 {
1406 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1407 reg = <0x00600000 0x100000>;
5e8b3bc3 1408 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
5f877518 1409 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
d2e8190b
BB		 1410 <&uhpck>;
1411 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1412 status = "disabled";
1413 };
1414
1415 usb2: ehci@00700000 {
1416 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1417 reg = <0x00700000 0x100000>;
5e8b3bc3 1418 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1419 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1420 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1421 status = "disabled";
1422 };
1423
1424 nand0: nand@60000000 {
1425 compatible = "atmel,at91rm9200-nand";
1426 #address-cells = <1>;
1427 #size-cells = <1>;
8ae599ef 1428 ranges;
655ff266
LD		 1429 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1430 0xffffc070 0x00000490 /* SMC PMECC regs */
1431 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1432 0x00110000 0x00018000 /* ROM code */
655ff266 1433 >;
5e8b3bc3 1434 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1435 atmel,nand-addr-offset = <21>;
1436 atmel,nand-cmd-offset = <22>;
e8b2da6e 1437 atmel,nand-has-dma;
655ff266
LD		 1438 pinctrl-names = "default";
1439 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1440 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1441 status = "disabled";
8ae599ef
JW		 1442
1443 nfc@70000000 {
1444 compatible = "atmel,sama5d3-nfc";
1445 #address-cells = <1>;
1446 #size-cells = <1>;
1447 reg = <
1448 0x70000000 0x10000000 /* NFC Command Registers */
1449 0xffffc000 0x00000070 /* NFC HSMC regs */
1450 0x00200000 0x00100000 /* NFC SRAM banks */
1451 >;
8a85ba20 1452 clocks = <&hsmc_clk>;
8ae599ef 1453 };
655ff266
LD		 1454 };
1455 };
1456};
Linux kernel - Deliverables
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