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ARM: at91: dts: sama5d3: split isi pinctrl
[deliverable/linux.git] / arch / arm / boot / dts / sama5d3.dtsi
CommitLineData
655ff266
LD		 1/*
2 * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
b32313c6 3 * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
655ff266
LD		 4 *
5 * Copyright (C) 2013 Atmel,
6 * 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
6db64d29 11#include "skeleton.dtsi"
d4ae89c8 12#include <dt-bindings/dma/at91.h>
c9d0f317 13#include <dt-bindings/pinctrl/at91.h>
5e8b3bc3 14#include <dt-bindings/interrupt-controller/irq.h>
92f8629b 15#include <dt-bindings/gpio/gpio.h>
35d35aae 16#include <dt-bindings/clock/at91.h>
655ff266
LD		 17
18/ {
19 model = "Atmel SAMA5D3 family SoC";
20 compatible = "atmel,sama5d3", "atmel,sama5";
21 interrupt-parent = <&aic>;
22
23 aliases {
24 serial0 = &dbgu;
25 serial1 = &usart0;
26 serial2 = &usart1;
27 serial3 = &usart2;
28 serial4 = &usart3;
29 gpio0 = &pioA;
30 gpio1 = &pioB;
31 gpio2 = &pioC;
32 gpio3 = &pioD;
33 gpio4 = &pioE;
34 tcb0 = &tcb0;
655ff266
LD		 35 i2c0 = &i2c0;
36 i2c1 = &i2c1;
37 i2c2 = &i2c2;
38 ssc0 = &ssc0;
39 ssc1 = &ssc1;
f3ab0527 40 pwm0 = &pwm0;
655ff266
LD		 41 };
42 cpus {
8b2efa89
AB		 43 #address-cells = <1>;
44 #size-cells = <0>;
655ff266 45 cpu@0 {
e757a6ee 46 device_type = "cpu";
655ff266 47 compatible = "arm,cortex-a5";
e757a6ee 48 reg = <0x0>;
655ff266
LD		 49 };
50 };
51
d9da9778
AB		 52 pmu {
53 compatible = "arm,cortex-a5-pmu";
54 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
55 };
56
655ff266
LD		 57 memory {
58 reg = <0x20000000 0x8000000>;
59 };
60
334394c0
AB		 61 clocks {
62 slow_xtal: slow_xtal {
63 compatible = "fixed-clock";
64 #clock-cells = <0>;
65 clock-frequency = <0>;
66 };
4753219d 67
334394c0
AB		 68 main_xtal: main_xtal {
69 compatible = "fixed-clock";
70 #clock-cells = <0>;
71 clock-frequency = <0>;
72 };
4753219d 73
d2e8190b
BB		 74 adc_op_clk: adc_op_clk{
75 compatible = "fixed-clock";
76 #clock-cells = <0>;
77 clock-frequency = <20000000>;
78 };
79 };
80
f04660e4
AB		 81 sram: sram@00300000 {
82 compatible = "mmio-sram";
83 reg = <0x00300000 0x20000>;
84 };
85
655ff266
LD		 86 ahb {
87 compatible = "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91
92 apb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 ranges;
97
98 mmc0: mmc@f0000000 {
99 compatible = "atmel,hsmci";
100 reg = <0xf0000000 0x600>;
5e8b3bc3 101 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 102 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 103 dma-names = "rxtx";
655ff266
LD		 104 pinctrl-names = "default";
105 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
106 status = "disabled";
107 #address-cells = <1>;
108 #size-cells = <0>;
d2e8190b
BB		 109 clocks = <&mci0_clk>;
110 clock-names = "mci_clk";
655ff266
LD		 111 };
112
113 spi0: spi@f0004000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
b7ef678e 116 compatible = "atmel,at91rm9200-spi";
655ff266 117 reg = <0xf0004000 0x100>;
5e8b3bc3 118 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 119 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
120 <&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
121 dma-names = "tx", "rx";
655ff266
LD		 122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_spi0>;
d2e8190b
BB		 124 clocks = <&spi0_clk>;
125 clock-names = "spi_clk";
655ff266
LD		 126 status = "disabled";
127 };
128
129 ssc0: ssc@f0008000 {
130 compatible = "atmel,at91sam9g45-ssc";
131 reg = <0xf0008000 0x4000>;
5e8b3bc3 132 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 133 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(13)>,
134 <&dma0 2 AT91_DMA_CFG_PER_ID(14)>;
135 dma-names = "tx", "rx";
655ff266
LD		 136 pinctrl-names = "default";
137 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
d2e8190b
BB		 138 clocks = <&ssc0_clk>;
139 clock-names = "pclk";
655ff266
LD		 140 status = "disabled";
141 };
142
655ff266
LD		 143 tcb0: timer@f0010000 {
144 compatible = "atmel,at91sam9x5-tcb";
145 reg = <0xf0010000 0x100>;
5e8b3bc3 146 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
d2e8190b
BB		 147 clocks = <&tcb0_clk>;
148 clock-names = "t0_clk";
655ff266
LD		 149 };
150
151 i2c0: i2c@f0014000 {
152 compatible = "atmel,at91sam9x5-i2c";
153 reg = <0xf0014000 0x4000>;
5e8b3bc3 154 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 155 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
156 <&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
d9a63a45 157 dma-names = "tx", "rx";
655ff266
LD		 158 pinctrl-names = "default";
159 pinctrl-0 = <&pinctrl_i2c0>;
160 #address-cells = <1>;
161 #size-cells = <0>;
d2e8190b 162 clocks = <&twi0_clk>;
655ff266
LD		 163 status = "disabled";
164 };
165
166 i2c1: i2c@f0018000 {
167 compatible = "atmel,at91sam9x5-i2c";
168 reg = <0xf0018000 0x4000>;
5e8b3bc3 169 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 170 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
171 <&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
d9a63a45 172 dma-names = "tx", "rx";
655ff266
LD		 173 pinctrl-names = "default";
174 pinctrl-0 = <&pinctrl_i2c1>;
175 #address-cells = <1>;
176 #size-cells = <0>;
d2e8190b 177 clocks = <&twi1_clk>;
655ff266
LD		 178 status = "disabled";
179 };
180
181 usart0: serial@f001c000 {
182 compatible = "atmel,at91sam9260-usart";
183 reg = <0xf001c000 0x100>;
5e8b3bc3 184 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 185 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
186 <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
187 dma-names = "tx", "rx";
655ff266
LD		 188 pinctrl-names = "default";
189 pinctrl-0 = <&pinctrl_usart0>;
d2e8190b
BB		 190 clocks = <&usart0_clk>;
191 clock-names = "usart";
655ff266
LD		 192 status = "disabled";
193 };
194
195 usart1: serial@f0020000 {
196 compatible = "atmel,at91sam9260-usart";
197 reg = <0xf0020000 0x100>;
5e8b3bc3 198 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 199 dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(5)>,
200 <&dma0 2 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
201 dma-names = "tx", "rx";
655ff266
LD		 202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_usart1>;
d2e8190b
BB		 204 clocks = <&usart1_clk>;
205 clock-names = "usart";
655ff266
LD		 206 status = "disabled";
207 };
208
f3ab0527
BS		 209 pwm0: pwm@f002c000 {
210 compatible = "atmel,sama5d3-pwm";
211 reg = <0xf002c000 0x300>;
212 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
213 #pwm-cells = <3>;
214 clocks = <&pwm_clk>;
215 status = "disabled";
216 };
655ff266 217
655ff266
LD		 218 isi: isi@f0034000 {
219 compatible = "atmel,at91sam9g45-isi";
220 reg = <0xf0034000 0x4000>;
5e8b3bc3 221 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
b00122f6
JW		 222 clocks = <&isi_clk>;
223 clock-names = "isi_clk";
655ff266
LD		 224 status = "disabled";
225 };
226
6ced9f4a
AB		 227 sfr: sfr@f0038000 {
228 compatible = "atmel,sama5d3-sfr", "syscon";
229 reg = <0xf0038000 0x60>;
230 };
231
655ff266
LD		 232 mmc1: mmc@f8000000 {
233 compatible = "atmel,hsmci";
234 reg = <0xf8000000 0x600>;
5e8b3bc3 235 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
d4ae89c8 236 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
05c1bc97 237 dma-names = "rxtx";
655ff266
LD		 238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
240 status = "disabled";
241 #address-cells = <1>;
242 #size-cells = <0>;
d2e8190b
BB		 243 clocks = <&mci1_clk>;
244 clock-names = "mci_clk";
655ff266
LD		 245 };
246
655ff266
LD		 247 spi1: spi@f8008000 {
248 #address-cells = <1>;
249 #size-cells = <0>;
b7ef678e 250 compatible = "atmel,at91rm9200-spi";
655ff266 251 reg = <0xf8008000 0x100>;
5e8b3bc3 252 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
e543a73a
NF		 253 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
254 <&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
255 dma-names = "tx", "rx";
655ff266
LD		 256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_spi1>;
d2e8190b
BB		 258 clocks = <&spi1_clk>;
259 clock-names = "spi_clk";
655ff266
LD		 260 status = "disabled";
261 };
262
263 ssc1: ssc@f800c000 {
264 compatible = "atmel,at91sam9g45-ssc";
265 reg = <0xf800c000 0x4000>;
5e8b3bc3 266 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
58962b74
BS		 267 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(3)>,
268 <&dma1 2 AT91_DMA_CFG_PER_ID(4)>;
269 dma-names = "tx", "rx";
655ff266
LD		 270 pinctrl-names = "default";
271 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
d2e8190b
BB		 272 clocks = <&ssc1_clk>;
273 clock-names = "pclk";
655ff266
LD		 274 status = "disabled";
275 };
276
655ff266 277 adc0: adc@f8018000 {
b3b84dec
AB		 278 #address-cells = <1>;
279 #size-cells = <0>;
9879b96d 280 compatible = "atmel,at91sam9x5-adc";
655ff266 281 reg = <0xf8018000 0x100>;
5e8b3bc3 282 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
655ff266
LD		 283 pinctrl-names = "default";
284 pinctrl-0 = <
285 &pinctrl_adc0_adtrg
286 &pinctrl_adc0_ad0
287 &pinctrl_adc0_ad1
288 &pinctrl_adc0_ad2
289 &pinctrl_adc0_ad3
290 &pinctrl_adc0_ad4
291 &pinctrl_adc0_ad5
292 &pinctrl_adc0_ad6
293 &pinctrl_adc0_ad7
294 &pinctrl_adc0_ad8
295 &pinctrl_adc0_ad9
296 &pinctrl_adc0_ad10
297 &pinctrl_adc0_ad11
298 >;
d2e8190b
BB		 299 clocks = <&adc_clk>,
300 <&adc_op_clk>;
301 clock-names = "adc_clk", "adc_op_clk";
655ff266 302 atmel,adc-channels-used = <0xfff>;
655ff266 303 atmel,adc-startup-time = <40>;
b3b84dec 304 atmel,adc-use-external-triggers;
655ff266
LD		 305 atmel,adc-vref = <3000>;
306 atmel,adc-res = <10 12>;
307 atmel,adc-res-names = "lowres", "highres";
308 status = "disabled";
309
310 trigger@0 {
b3b84dec 311 reg = <0>;
655ff266
LD		 312 trigger-name = "external-rising";
313 trigger-value = <0x1>;
314 trigger-external;
315 };
316 trigger@1 {
b3b84dec 317 reg = <1>;
655ff266
LD		 318 trigger-name = "external-falling";
319 trigger-value = <0x2>;
320 trigger-external;
321 };
322 trigger@2 {
b3b84dec 323 reg = <2>;
655ff266
LD		 324 trigger-name = "external-any";
325 trigger-value = <0x3>;
326 trigger-external;
327 };
328 trigger@3 {
b3b84dec 329 reg = <3>;
655ff266
LD		 330 trigger-name = "continuous";
331 trigger-value = <0x6>;
332 };
333 };
334
655ff266
LD		 335 i2c2: i2c@f801c000 {
336 compatible = "atmel,at91sam9x5-i2c";
337 reg = <0xf801c000 0x4000>;
5e8b3bc3 338 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
d4ae89c8
LD		 339 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
340 <&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
d9a63a45 341 dma-names = "tx", "rx";
557844ec
NF		 342 pinctrl-names = "default";
343 pinctrl-0 = <&pinctrl_i2c2>;
655ff266
LD		 344 #address-cells = <1>;
345 #size-cells = <0>;
d2e8190b 346 clocks = <&twi2_clk>;
655ff266
LD		 347 status = "disabled";
348 };
349
350 usart2: serial@f8020000 {
351 compatible = "atmel,at91sam9260-usart";
352 reg = <0xf8020000 0x100>;
5e8b3bc3 353 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 354 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(7)>,
355 <&dma1 2 (AT91_DMA_CFG_PER_ID(8) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
356 dma-names = "tx", "rx";
655ff266
LD		 357 pinctrl-names = "default";
358 pinctrl-0 = <&pinctrl_usart2>;
d2e8190b
BB		 359 clocks = <&usart2_clk>;
360 clock-names = "usart";
655ff266
LD		 361 status = "disabled";
362 };
363
364 usart3: serial@f8024000 {
365 compatible = "atmel,at91sam9260-usart";
366 reg = <0xf8024000 0x100>;
5e8b3bc3 367 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
d24cd783
LD		 368 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(9)>,
369 <&dma1 2 (AT91_DMA_CFG_PER_ID(10) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
370 dma-names = "tx", "rx";
655ff266
LD		 371 pinctrl-names = "default";
372 pinctrl-0 = <&pinctrl_usart3>;
d2e8190b
BB		 373 clocks = <&usart3_clk>;
374 clock-names = "usart";
655ff266
LD		 375 status = "disabled";
376 };
377
655ff266 378 sha@f8034000 {
c76f266d 379 compatible = "atmel,at91sam9g46-sha";
655ff266 380 reg = <0xf8034000 0x100>;
5e8b3bc3 381 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 382 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
383 dma-names = "tx";
4df4f446
BB		 384 clocks = <&sha_clk>;
385 clock-names = "sha_clk";
655ff266
LD		 386 };
387
388 aes@f8038000 {
c76f266d 389 compatible = "atmel,at91sam9g46-aes";
655ff266 390 reg = <0xf8038000 0x100>;
07f7d503 391 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 392 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
393 <&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
394 dma-names = "tx", "rx";
f68cd356
BB		 395 clocks = <&aes_clk>;
396 clock-names = "aes_clk";
655ff266
LD		 397 };
398
399 tdes@f803c000 {
c76f266d 400 compatible = "atmel,at91sam9g46-tdes";
655ff266 401 reg = <0xf803c000 0x100>;
5e8b3bc3 402 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
9860c515
NF		 403 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
404 <&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
405 dma-names = "tx", "rx";
45e5c2cb
BB		 406 clocks = <&tdes_clk>;
407 clock-names = "tdes_clk";
655ff266
LD		 408 };
409
410 dma0: dma-controller@ffffe600 {
411 compatible = "atmel,at91sam9g45-dma";
412 reg = <0xffffe600 0x200>;
5e8b3bc3 413 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 414 #dma-cells = <2>;
d2e8190b
BB		 415 clocks = <&dma0_clk>;
416 clock-names = "dma_clk";
655ff266
LD		 417 };
418
419 dma1: dma-controller@ffffe800 {
420 compatible = "atmel,at91sam9g45-dma";
421 reg = <0xffffe800 0x200>;
5e8b3bc3 422 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
980ce7d9 423 #dma-cells = <2>;
d2e8190b
BB		 424 clocks = <&dma1_clk>;
425 clock-names = "dma_clk";
655ff266
LD		 426 };
427
428 ramc0: ramc@ffffea00 {
063de897 429 compatible = "atmel,sama5d3-ddramc";
655ff266 430 reg = <0xffffea00 0x200>;
063de897
AB		 431 clocks = <&ddrck>, <&mpddr_clk>;
432 clock-names = "ddrck", "mpddr";
655ff266
LD		 433 };
434
435 dbgu: serial@ffffee00 {
436 compatible = "atmel,at91sam9260-usart";
437 reg = <0xffffee00 0x200>;
5e8b3bc3 438 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
d24cd783
LD		 439 dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(13)>,
440 <&dma1 2 (AT91_DMA_CFG_PER_ID(14) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
441 dma-names = "tx", "rx";
655ff266
LD		 442 pinctrl-names = "default";
443 pinctrl-0 = <&pinctrl_dbgu>;
d2e8190b
BB		 444 clocks = <&dbgu_clk>;
445 clock-names = "usart";
655ff266
LD		 446 status = "disabled";
447 };
448
449 aic: interrupt-controller@fffff000 {
450 #interrupt-cells = <3>;
451 compatible = "atmel,sama5d3-aic";
452 interrupt-controller;
453 reg = <0xfffff000 0x200>;
454 atmel,external-irqs = <47>;
455 };
456
457 pinctrl@fffff200 {
458 #address-cells = <1>;
459 #size-cells = <1>;
e0065cf7 460 compatible = "atmel,sama5d3-pinctrl", "atmel,at91sam9x5-pinctrl", "simple-bus";
655ff266
LD		 461 ranges = <0xfffff200 0xfffff200 0xa00>;
462 atmel,mux-mask = <
463 /* A B C */
464 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
465 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
466 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
467 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
468 0xffffffff 0xbf9f8000 0x18000000 /* pioE */
469 >;
470
471 /* shared pinctrl settings */
472 adc0 {
473 pinctrl_adc0_adtrg: adc0_adtrg {
474 atmel,pins =
c9d0f317 475 <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
655ff266
LD		 476 };
477 pinctrl_adc0_ad0: adc0_ad0 {
478 atmel,pins =
c9d0f317 479 <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
655ff266
LD		 480 };
481 pinctrl_adc0_ad1: adc0_ad1 {
482 atmel,pins =
c9d0f317 483 <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
655ff266
LD		 484 };
485 pinctrl_adc0_ad2: adc0_ad2 {
486 atmel,pins =
c9d0f317 487 <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
655ff266
LD		 488 };
489 pinctrl_adc0_ad3: adc0_ad3 {
490 atmel,pins =
c9d0f317 491 <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
655ff266
LD		 492 };
493 pinctrl_adc0_ad4: adc0_ad4 {
494 atmel,pins =
c9d0f317 495 <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
655ff266
LD		 496 };
497 pinctrl_adc0_ad5: adc0_ad5 {
498 atmel,pins =
c9d0f317 499 <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
655ff266
LD		 500 };
501 pinctrl_adc0_ad6: adc0_ad6 {
502 atmel,pins =
c9d0f317 503 <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
655ff266
LD		 504 };
505 pinctrl_adc0_ad7: adc0_ad7 {
506 atmel,pins =
c9d0f317 507 <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
655ff266
LD		 508 };
509 pinctrl_adc0_ad8: adc0_ad8 {
510 atmel,pins =
c9d0f317 511 <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
655ff266
LD		 512 };
513 pinctrl_adc0_ad9: adc0_ad9 {
514 atmel,pins =
c9d0f317 515 <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
655ff266
LD		 516 };
517 pinctrl_adc0_ad10: adc0_ad10 {
518 atmel,pins =
c9d0f317 519 <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
655ff266
LD		 520 };
521 pinctrl_adc0_ad11: adc0_ad11 {
522 atmel,pins =
c9d0f317 523 <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
655ff266
LD		 524 };
525 };
526
655ff266
LD		 527 dbgu {
528 pinctrl_dbgu: dbgu-0 {
529 atmel,pins =
c9d0f317
JCPV		 530 <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
531 AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
655ff266
LD		 532 };
533 };
534
535 i2c0 {
536 pinctrl_i2c0: i2c0-0 {
537 atmel,pins =
c9d0f317
JCPV		 538 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
539 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
655ff266
LD		 540 };
541 };
542
543 i2c1 {
544 pinctrl_i2c1: i2c1-0 {
545 atmel,pins =
c9d0f317
JCPV		 546 <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
547 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
655ff266
LD		 548 };
549 };
550
557844ec
NF		 551 i2c2 {
552 pinctrl_i2c2: i2c2-0 {
553 atmel,pins =
554 <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
555 AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
556 };
557 };
558
655ff266 559 isi {
cbaa29c4 560 pinctrl_isi_data_0_7: isi-0-data-0-7 {
655ff266 561 atmel,pins =
c9d0f317
JCPV		 562 <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
563 AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
564 AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
565 AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
566 AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
567 AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
568 AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
569 AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
570 AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
571 AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
cbaa29c4
BS		 572 AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
573 };
574
575 pinctrl_isi_data_8_9: isi-0-data-8-9 {
576 atmel,pins =
577 <AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
c9d0f317 578 AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
655ff266 579 };
cbaa29c4 580
655ff266
LD		 581 pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
582 atmel,pins =
c9d0f317 583 <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
655ff266
LD		 584 };
585 };
586
655ff266
LD		 587 mmc0 {
588 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
589 atmel,pins =
c9d0f317
JCPV		 590 <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
591 AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
592 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
655ff266
LD		 593 };
594 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
595 atmel,pins =
c9d0f317
JCPV		 596 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
597 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
598 AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
655ff266
LD		 599 };
600 pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
601 atmel,pins =
c9d0f317
JCPV		 602 <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
603 AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
604 AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
605 AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
655ff266
LD		 606 };
607 };
608
609 mmc1 {
610 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
611 atmel,pins =
c9d0f317
JCPV		 612 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
613 AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
614 AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
655ff266
LD		 615 };
616 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
617 atmel,pins =
c9d0f317
JCPV		 618 <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
619 AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
620 AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
655ff266
LD		 621 };
622 };
623
655ff266
LD		 624 nand0 {
625 pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
626 atmel,pins =
c9d0f317
JCPV		 627 <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
628 AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
655ff266
LD		 629 };
630 };
631
5eefd5f4
NF		 632 pwm0 {
633 pinctrl_pwm0_pwmh0_0: pwm0_pwmh0-0 {
634 atmel,pins =
635 <AT91_PIOA 20 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D4 and LCDDAT20 */
636 };
637 pinctrl_pwm0_pwmh0_1: pwm0_pwmh0-1 {
638 atmel,pins =
639 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX0 */
640 };
641 pinctrl_pwm0_pwml0_0: pwm0_pwml0-0 {
642 atmel,pins =
643 <AT91_PIOA 21 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D5 and LCDDAT21 */
644 };
645 pinctrl_pwm0_pwml0_1: pwm0_pwml0-1 {
646 atmel,pins =
647 <AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTX1 */
648 };
649
650 pinctrl_pwm0_pwmh1_0: pwm0_pwmh1-0 {
651 atmel,pins =
652 <AT91_PIOA 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D6 and LCDDAT22 */
653 };
654 pinctrl_pwm0_pwmh1_1: pwm0_pwmh1-1 {
655 atmel,pins =
656 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX0 */
657 };
658 pinctrl_pwm0_pwmh1_2: pwm0_pwmh1-2 {
659 atmel,pins =
660 <AT91_PIOB 27 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with G125CKO and RTS1 */
661 };
662 pinctrl_pwm0_pwml1_0: pwm0_pwml1-0 {
663 atmel,pins =
664 <AT91_PIOA 23 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with ISI_D7 and LCDDAT23 */
665 };
666 pinctrl_pwm0_pwml1_1: pwm0_pwml1-1 {
667 atmel,pins =
668 <AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRX1 */
669 };
670 pinctrl_pwm0_pwml1_2: pwm0_pwml1-2 {
671 atmel,pins =
672 <AT91_PIOE 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with IRQ */
673 };
674
675 pinctrl_pwm0_pwmh2_0: pwm0_pwmh2-0 {
676 atmel,pins =
677 <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXCK */
678 };
679 pinctrl_pwm0_pwmh2_1: pwm0_pwmh2-1 {
680 atmel,pins =
681 <AT91_PIOD 5 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA4 and TIOA0 */
682 };
683 pinctrl_pwm0_pwml2_0: pwm0_pwml2-0 {
684 atmel,pins =
685 <AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GTXEN */
686 };
687 pinctrl_pwm0_pwml2_1: pwm0_pwml2-1 {
688 atmel,pins =
689 <AT91_PIOD 6 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA5 and TIOB0 */
690 };
691
692 pinctrl_pwm0_pwmh3_0: pwm0_pwmh3-0 {
693 atmel,pins =
694 <AT91_PIOB 12 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXDV */
695 };
696 pinctrl_pwm0_pwmh3_1: pwm0_pwmh3-1 {
697 atmel,pins =
698 <AT91_PIOD 7 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA6 and TCLK0 */
699 };
700 pinctrl_pwm0_pwml3_0: pwm0_pwml3-0 {
701 atmel,pins =
702 <AT91_PIOB 13 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with GRXER */
703 };
704 pinctrl_pwm0_pwml3_1: pwm0_pwml3-1 {
705 atmel,pins =
706 <AT91_PIOD 8 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with MCI0_DA7 */
707 };
708 };
709
655ff266
LD		 710 spi0 {
711 pinctrl_spi0: spi0-0 {
712 atmel,pins =
c9d0f317
JCPV		 713 <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
714 AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
715 AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
655ff266
LD		 716 };
717 };
718
719 spi1 {
720 pinctrl_spi1: spi1-0 {
721 atmel,pins =
c9d0f317
JCPV		 722 <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
723 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
724 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
655ff266
LD		 725 };
726 };
727
728 ssc0 {
729 pinctrl_ssc0_tx: ssc0_tx {
730 atmel,pins =
c9d0f317
JCPV		 731 <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
732 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
733 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
655ff266
LD		 734 };
735
736 pinctrl_ssc0_rx: ssc0_rx {
737 atmel,pins =
c9d0f317
JCPV		 738 <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
739 AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
740 AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
655ff266
LD		 741 };
742 };
743
744 ssc1 {
745 pinctrl_ssc1_tx: ssc1_tx {
746 atmel,pins =
c9d0f317
JCPV		 747 <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
748 AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
749 AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
655ff266
LD		 750 };
751
752 pinctrl_ssc1_rx: ssc1_rx {
753 atmel,pins =
c9d0f317
JCPV		 754 <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
755 AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
756 AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
655ff266
LD		 757 };
758 };
759
655ff266
LD		 760 usart0 {
761 pinctrl_usart0: usart0-0 {
762 atmel,pins =
c9d0f317
JCPV		 763 <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
764 AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
655ff266
LD		 765 };
766
767 pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
768 atmel,pins =
c9d0f317
JCPV		 769 <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
770 AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
655ff266
LD		 771 };
772 };
773
774 usart1 {
775 pinctrl_usart1: usart1-0 {
776 atmel,pins =
c9d0f317
JCPV		 777 <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
778 AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
655ff266
LD		 779 };
780
781 pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
782 atmel,pins =
c9d0f317
JCPV		 783 <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
784 AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
655ff266
LD		 785 };
786 };
787
788 usart2 {
789 pinctrl_usart2: usart2-0 {
790 atmel,pins =
c9d0f317
JCPV		 791 <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
792 AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
655ff266
LD		 793 };
794
795 pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
796 atmel,pins =
c9d0f317
JCPV		 797 <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
798 AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
655ff266
LD		 799 };
800 };
801
802 usart3 {
803 pinctrl_usart3: usart3-0 {
804 atmel,pins =
c9d0f317
JCPV		 805 <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
806 AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
655ff266
LD		 807 };
808
809 pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
810 atmel,pins =
c9d0f317
JCPV		 811 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
812 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
655ff266
LD		 813 };
814 };
c9d0f317
JCPV		 815
816
817 pioA: gpio@fffff200 {
818 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
819 reg = <0xfffff200 0x100>;
5e8b3bc3 820 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 821 #gpio-cells = <2>;
822 gpio-controller;
823 interrupt-controller;
824 #interrupt-cells = <2>;
d2e8190b 825 clocks = <&pioA_clk>;
c9d0f317
JCPV		 826 };
827
828 pioB: gpio@fffff400 {
829 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
830 reg = <0xfffff400 0x100>;
5e8b3bc3 831 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 832 #gpio-cells = <2>;
833 gpio-controller;
834 interrupt-controller;
835 #interrupt-cells = <2>;
d2e8190b 836 clocks = <&pioB_clk>;
c9d0f317
JCPV		 837 };
838
839 pioC: gpio@fffff600 {
840 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
841 reg = <0xfffff600 0x100>;
5e8b3bc3 842 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 843 #gpio-cells = <2>;
844 gpio-controller;
845 interrupt-controller;
846 #interrupt-cells = <2>;
d2e8190b 847 clocks = <&pioC_clk>;
c9d0f317
JCPV		 848 };
849
850 pioD: gpio@fffff800 {
851 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
852 reg = <0xfffff800 0x100>;
5e8b3bc3 853 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 854 #gpio-cells = <2>;
855 gpio-controller;
856 interrupt-controller;
857 #interrupt-cells = <2>;
d2e8190b 858 clocks = <&pioD_clk>;
c9d0f317
JCPV		 859 };
860
861 pioE: gpio@fffffa00 {
862 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
863 reg = <0xfffffa00 0x100>;
5e8b3bc3 864 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
c9d0f317
JCPV		 865 #gpio-cells = <2>;
866 gpio-controller;
867 interrupt-controller;
868 #interrupt-cells = <2>;
d2e8190b 869 clocks = <&pioE_clk>;
c9d0f317 870 };
655ff266
LD		 871 };
872
873 pmc: pmc@fffffc00 {
d2e8190b 874 compatible = "atmel,sama5d3-pmc";
655ff266 875 reg = <0xfffffc00 0x120>;
d2e8190b
BB		 876 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
877 interrupt-controller;
878 #address-cells = <1>;
879 #size-cells = <0>;
880 #interrupt-cells = <1>;
881
4753219d
BB		 882 main_rc_osc: main_rc_osc {
883 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
d2e8190b 884 #clock-cells = <0>;
4753219d
BB		 885 interrupt-parent = <&pmc>;
886 interrupts = <AT91_PMC_MOSCRCS>;
887 clock-frequency = <12000000>;
888 clock-accuracy = <50000000>;
d2e8190b
BB		 889 };
890
4753219d
BB		 891 main_osc: main_osc {
892 compatible = "atmel,at91rm9200-clk-main-osc";
d2e8190b
BB		 893 #clock-cells = <0>;
894 interrupt-parent = <&pmc>;
895 interrupts = <AT91_PMC_MOSCS>;
4753219d
BB		 896 clocks = <&main_xtal>;
897 };
898
899 main: mainck {
900 compatible = "atmel,at91sam9x5-clk-main";
901 #clock-cells = <0>;
902 interrupt-parent = <&pmc>;
903 interrupts = <AT91_PMC_MOSCSELS>;
904 clocks = <&main_rc_osc &main_osc>;
d2e8190b
BB		 905 };
906
907 plla: pllack {
908 compatible = "atmel,sama5d3-clk-pll";
909 #clock-cells = <0>;
910 interrupt-parent = <&pmc>;
911 interrupts = <AT91_PMC_LOCKA>;
912 clocks = <&main>;
913 reg = <0>;
914 atmel,clk-input-range = <8000000 50000000>;
915 #atmel,pll-clk-output-range-cells = <4>;
916 atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
917 };
918
919 plladiv: plladivck {
920 compatible = "atmel,at91sam9x5-clk-plldiv";
921 #clock-cells = <0>;
922 clocks = <&plla>;
923 };
924
925 utmi: utmick {
926 compatible = "atmel,at91sam9x5-clk-utmi";
927 #clock-cells = <0>;
928 interrupt-parent = <&pmc>;
929 interrupts = <AT91_PMC_LOCKU>;
930 clocks = <&main>;
931 };
932
933 mck: masterck {
934 compatible = "atmel,at91sam9x5-clk-master";
935 #clock-cells = <0>;
936 interrupt-parent = <&pmc>;
937 interrupts = <AT91_PMC_MCKRDY>;
938 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
939 atmel,clk-output-range = <0 166000000>;
940 atmel,clk-divisors = <1 2 4 3>;
941 };
942
943 usb: usbck {
944 compatible = "atmel,at91sam9x5-clk-usb";
945 #clock-cells = <0>;
946 clocks = <&plladiv>, <&utmi>;
947 };
948
949 prog: progck {
950 compatible = "atmel,at91sam9x5-clk-programmable";
951 #address-cells = <1>;
952 #size-cells = <0>;
953 interrupt-parent = <&pmc>;
954 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
955
956 prog0: prog0 {
957 #clock-cells = <0>;
958 reg = <0>;
959 interrupts = <AT91_PMC_PCKRDY(0)>;
960 };
961
962 prog1: prog1 {
963 #clock-cells = <0>;
964 reg = <1>;
965 interrupts = <AT91_PMC_PCKRDY(1)>;
966 };
967
968 prog2: prog2 {
969 #clock-cells = <0>;
970 reg = <2>;
971 interrupts = <AT91_PMC_PCKRDY(2)>;
972 };
973 };
974
975 smd: smdclk {
976 compatible = "atmel,at91sam9x5-clk-smd";
977 #clock-cells = <0>;
978 clocks = <&plladiv>, <&utmi>;
979 };
980
981 systemck {
982 compatible = "atmel,at91rm9200-clk-system";
983 #address-cells = <1>;
984 #size-cells = <0>;
985
986 ddrck: ddrck {
987 #clock-cells = <0>;
988 reg = <2>;
989 clocks = <&mck>;
990 };
991
992 smdck: smdck {
993 #clock-cells = <0>;
994 reg = <4>;
995 clocks = <&smd>;
996 };
997
998 uhpck: uhpck {
999 #clock-cells = <0>;
1000 reg = <6>;
1001 clocks = <&usb>;
1002 };
1003
1004 udpck: udpck {
1005 #clock-cells = <0>;
1006 reg = <7>;
1007 clocks = <&usb>;
1008 };
1009
1010 pck0: pck0 {
1011 #clock-cells = <0>;
1012 reg = <8>;
1013 clocks = <&prog0>;
1014 };
1015
1016 pck1: pck1 {
1017 #clock-cells = <0>;
1018 reg = <9>;
1019 clocks = <&prog1>;
1020 };
1021
1022 pck2: pck2 {
1023 #clock-cells = <0>;
1024 reg = <10>;
1025 clocks = <&prog2>;
1026 };
1027 };
1028
1029 periphck {
1030 compatible = "atmel,at91sam9x5-clk-peripheral";
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033 clocks = <&mck>;
1034
1035 dbgu_clk: dbgu_clk {
1036 #clock-cells = <0>;
1037 reg = <2>;
1038 };
1039
8a85ba20
AB		 1040 hsmc_clk: hsmc_clk {
1041 #clock-cells = <0>;
1042 reg = <5>;
1043 };
1044
d2e8190b
BB		 1045 pioA_clk: pioA_clk {
1046 #clock-cells = <0>;
1047 reg = <6>;
1048 };
1049
1050 pioB_clk: pioB_clk {
1051 #clock-cells = <0>;
1052 reg = <7>;
1053 };
1054
1055 pioC_clk: pioC_clk {
1056 #clock-cells = <0>;
1057 reg = <8>;
1058 };
1059
1060 pioD_clk: pioD_clk {
1061 #clock-cells = <0>;
1062 reg = <9>;
1063 };
1064
1065 pioE_clk: pioE_clk {
1066 #clock-cells = <0>;
1067 reg = <10>;
1068 };
1069
1070 usart0_clk: usart0_clk {
1071 #clock-cells = <0>;
1072 reg = <12>;
1073 atmel,clk-output-range = <0 66000000>;
1074 };
1075
1076 usart1_clk: usart1_clk {
1077 #clock-cells = <0>;
1078 reg = <13>;
1079 atmel,clk-output-range = <0 66000000>;
1080 };
1081
1082 usart2_clk: usart2_clk {
1083 #clock-cells = <0>;
1084 reg = <14>;
1085 atmel,clk-output-range = <0 66000000>;
1086 };
1087
1088 usart3_clk: usart3_clk {
1089 #clock-cells = <0>;
1090 reg = <15>;
1091 atmel,clk-output-range = <0 66000000>;
1092 };
1093
1094 twi0_clk: twi0_clk {
1095 reg = <18>;
1096 #clock-cells = <0>;
1097 atmel,clk-output-range = <0 16625000>;
1098 };
1099
1100 twi1_clk: twi1_clk {
1101 #clock-cells = <0>;
1102 reg = <19>;
1103 atmel,clk-output-range = <0 16625000>;
1104 };
1105
1106 twi2_clk: twi2_clk {
1107 #clock-cells = <0>;
1108 reg = <20>;
1109 atmel,clk-output-range = <0 16625000>;
1110 };
1111
1112 mci0_clk: mci0_clk {
1113 #clock-cells = <0>;
1114 reg = <21>;
1115 };
1116
1117 mci1_clk: mci1_clk {
1118 #clock-cells = <0>;
1119 reg = <22>;
1120 };
1121
1122 spi0_clk: spi0_clk {
1123 #clock-cells = <0>;
1124 reg = <24>;
1125 atmel,clk-output-range = <0 133000000>;
1126 };
1127
1128 spi1_clk: spi1_clk {
1129 #clock-cells = <0>;
1130 reg = <25>;
1131 atmel,clk-output-range = <0 133000000>;
1132 };
1133
1134 tcb0_clk: tcb0_clk {
1135 #clock-cells = <0>;
1136 reg = <26>;
1137 atmel,clk-output-range = <0 133000000>;
1138 };
1139
1140 pwm_clk: pwm_clk {
1141 #clock-cells = <0>;
1142 reg = <28>;
1143 };
1144
1145 adc_clk: adc_clk {
1146 #clock-cells = <0>;
1147 reg = <29>;
1148 atmel,clk-output-range = <0 66000000>;
1149 };
1150
1151 dma0_clk: dma0_clk {
1152 #clock-cells = <0>;
1153 reg = <30>;
1154 };
1155
1156 dma1_clk: dma1_clk {
1157 #clock-cells = <0>;
1158 reg = <31>;
1159 };
1160
1161 uhphs_clk: uhphs_clk {
1162 #clock-cells = <0>;
1163 reg = <32>;
1164 };
1165
1166 udphs_clk: udphs_clk {
1167 #clock-cells = <0>;
1168 reg = <33>;
1169 };
1170
1171 isi_clk: isi_clk {
1172 #clock-cells = <0>;
1173 reg = <37>;
1174 };
1175
1176 ssc0_clk: ssc0_clk {
1177 #clock-cells = <0>;
1178 reg = <38>;
1179 atmel,clk-output-range = <0 66000000>;
1180 };
1181
1182 ssc1_clk: ssc1_clk {
1183 #clock-cells = <0>;
1184 reg = <39>;
1185 atmel,clk-output-range = <0 66000000>;
1186 };
1187
1188 sha_clk: sha_clk {
1189 #clock-cells = <0>;
1190 reg = <42>;
1191 };
1192
1193 aes_clk: aes_clk {
1194 #clock-cells = <0>;
1195 reg = <43>;
1196 };
1197
1198 tdes_clk: tdes_clk {
1199 #clock-cells = <0>;
1200 reg = <44>;
1201 };
1202
1203 trng_clk: trng_clk {
1204 #clock-cells = <0>;
1205 reg = <45>;
1206 };
1207
1208 fuse_clk: fuse_clk {
1209 #clock-cells = <0>;
1210 reg = <48>;
1211 };
063de897
AB		 1212
1213 mpddr_clk: mpddr_clk {
1214 #clock-cells = <0>;
1215 reg = <49>;
1216 };
d2e8190b 1217 };
655ff266
LD		 1218 };
1219
1220 rstc@fffffe00 {
1221 compatible = "atmel,at91sam9g45-rstc";
1222 reg = <0xfffffe00 0x10>;
1223 };
1224
16aa7f1f
MR		 1225 shutdown-controller@fffffe10 {
1226 compatible = "atmel,at91sam9x5-shdwc";
1227 reg = <0xfffffe10 0x10>;
1228 };
1229
655ff266
LD		 1230 pit: timer@fffffe30 {
1231 compatible = "atmel,at91sam9260-pit";
1232 reg = <0xfffffe30 0xf>;
5e8b3bc3 1233 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
d2e8190b 1234 clocks = <&mck>;
655ff266
LD		 1235 };
1236
1237 watchdog@fffffe40 {
1238 compatible = "atmel,at91sam9260-wdt";
1239 reg = <0xfffffe40 0x10>;
fe46aa67
BB		 1240 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1241 atmel,watchdog-type = "hardware";
1242 atmel,reset-type = "all";
1243 atmel,dbg-halt;
1244 atmel,idle-halt;
655ff266
LD		 1245 status = "disabled";
1246 };
1247
4753219d
BB		 1248 sckc@fffffe50 {
1249 compatible = "atmel,at91sam9x5-sckc";
1250 reg = <0xfffffe50 0x4>;
1251
1252 slow_rc_osc: slow_rc_osc {
1253 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1254 #clock-cells = <0>;
1255 clock-frequency = <32768>;
1256 clock-accuracy = <50000000>;
1257 atmel,startup-time-usec = <75>;
1258 };
1259
1260 slow_osc: slow_osc {
1261 compatible = "atmel,at91sam9x5-clk-slow-osc";
1262 #clock-cells = <0>;
1263 clocks = <&slow_xtal>;
1264 atmel,startup-time-usec = <1200000>;
1265 };
1266
1267 clk32k: slowck {
1268 compatible = "atmel,at91sam9x5-clk-slow";
1269 #clock-cells = <0>;
1270 clocks = <&slow_rc_osc &slow_osc>;
1271 };
1272 };
1273
655ff266
LD		 1274 rtc@fffffeb0 {
1275 compatible = "atmel,at91rm9200-rtc";
1276 reg = <0xfffffeb0 0x30>;
5e8b3bc3 1277 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
655ff266
LD		 1278 };
1279 };
1280
1281 usb0: gadget@00500000 {
1282 #address-cells = <1>;
1283 #size-cells = <0>;
1284 compatible = "atmel,at91sam9rl-udc";
1285 reg = <0x00500000 0x100000
1286 0xf8030000 0x4000>;
5e8b3bc3 1287 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1288 clocks = <&udphs_clk>, <&utmi>;
1289 clock-names = "pclk", "hclk";
655ff266
LD		 1290 status = "disabled";
1291
1292 ep0 {
1293 reg = <0>;
1294 atmel,fifo-size = <64>;
1295 atmel,nb-banks = <1>;
1296 };
1297
1298 ep1 {
1299 reg = <1>;
1300 atmel,fifo-size = <1024>;
1301 atmel,nb-banks = <3>;
1302 atmel,can-dma;
1303 atmel,can-isoc;
1304 };
1305
1306 ep2 {
1307 reg = <2>;
1308 atmel,fifo-size = <1024>;
1309 atmel,nb-banks = <3>;
1310 atmel,can-dma;
1311 atmel,can-isoc;
1312 };
1313
1314 ep3 {
1315 reg = <3>;
1316 atmel,fifo-size = <1024>;
1317 atmel,nb-banks = <2>;
1318 atmel,can-dma;
1319 };
1320
1321 ep4 {
1322 reg = <4>;
1323 atmel,fifo-size = <1024>;
1324 atmel,nb-banks = <2>;
1325 atmel,can-dma;
1326 };
1327
1328 ep5 {
1329 reg = <5>;
1330 atmel,fifo-size = <1024>;
1331 atmel,nb-banks = <2>;
1332 atmel,can-dma;
1333 };
1334
1335 ep6 {
1336 reg = <6>;
1337 atmel,fifo-size = <1024>;
1338 atmel,nb-banks = <2>;
1339 atmel,can-dma;
1340 };
1341
1342 ep7 {
1343 reg = <7>;
1344 atmel,fifo-size = <1024>;
1345 atmel,nb-banks = <2>;
1346 atmel,can-dma;
1347 };
1348
1349 ep8 {
1350 reg = <8>;
1351 atmel,fifo-size = <1024>;
1352 atmel,nb-banks = <2>;
1353 };
1354
1355 ep9 {
1356 reg = <9>;
1357 atmel,fifo-size = <1024>;
1358 atmel,nb-banks = <2>;
1359 };
1360
1361 ep10 {
1362 reg = <10>;
1363 atmel,fifo-size = <1024>;
1364 atmel,nb-banks = <2>;
1365 };
1366
1367 ep11 {
1368 reg = <11>;
1369 atmel,fifo-size = <1024>;
1370 atmel,nb-banks = <2>;
1371 };
1372
1373 ep12 {
1374 reg = <12>;
1375 atmel,fifo-size = <1024>;
1376 atmel,nb-banks = <2>;
1377 };
1378
1379 ep13 {
1380 reg = <13>;
1381 atmel,fifo-size = <1024>;
1382 atmel,nb-banks = <2>;
1383 };
1384
1385 ep14 {
1386 reg = <14>;
1387 atmel,fifo-size = <1024>;
1388 atmel,nb-banks = <2>;
1389 };
1390
1391 ep15 {
1392 reg = <15>;
1393 atmel,fifo-size = <1024>;
1394 atmel,nb-banks = <2>;
1395 };
1396 };
1397
1398 usb1: ohci@00600000 {
1399 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
1400 reg = <0x00600000 0x100000>;
5e8b3bc3 1401 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
5f877518 1402 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
d2e8190b
BB		 1403 <&uhpck>;
1404 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
655ff266
LD		 1405 status = "disabled";
1406 };
1407
1408 usb2: ehci@00700000 {
1409 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
1410 reg = <0x00700000 0x100000>;
5e8b3bc3 1411 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
d2e8190b
BB		 1412 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
1413 clock-names = "usb_clk", "ehci_clk", "uhpck";
655ff266
LD		 1414 status = "disabled";
1415 };
1416
1417 nand0: nand@60000000 {
1418 compatible = "atmel,at91rm9200-nand";
1419 #address-cells = <1>;
1420 #size-cells = <1>;
8ae599ef 1421 ranges;
655ff266
LD		 1422 reg = < 0x60000000 0x01000000 /* EBI CS3 */
1423 0xffffc070 0x00000490 /* SMC PMECC regs */
1424 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
afa6a2a7 1425 0x00110000 0x00018000 /* ROM code */
655ff266 1426 >;
5e8b3bc3 1427 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
655ff266
LD		 1428 atmel,nand-addr-offset = <21>;
1429 atmel,nand-cmd-offset = <22>;
e8b2da6e 1430 atmel,nand-has-dma;
655ff266
LD		 1431 pinctrl-names = "default";
1432 pinctrl-0 = <&pinctrl_nand0_ale_cle>;
afa6a2a7 1433 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
655ff266 1434 status = "disabled";
8ae599ef
JW		 1435
1436 nfc@70000000 {
1437 compatible = "atmel,sama5d3-nfc";
1438 #address-cells = <1>;
1439 #size-cells = <1>;
1440 reg = <
1441 0x70000000 0x10000000 /* NFC Command Registers */
1442 0xffffc000 0x00000070 /* NFC HSMC regs */
1443 0x00200000 0x00100000 /* NFC SRAM banks */
1444 >;
8a85ba20 1445 clocks = <&hsmc_clk>;
8ae599ef 1446 };
655ff266
LD		 1447 };
1448 };
1449};
Linux kernel - Deliverables
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