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655ff266 LD |
1 | /* |
2 | * sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC | |
3 | * applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 SoC | |
4 | * | |
5 | * Copyright (C) 2013 Atmel, | |
6 | * 2013 Ludovic Desroches <ludovic.desroches@atmel.com> | |
7 | * | |
8 | * Licensed under GPLv2 or later. | |
9 | */ | |
10 | ||
6db64d29 | 11 | #include "skeleton.dtsi" |
d4ae89c8 | 12 | #include <dt-bindings/dma/at91.h> |
c9d0f317 | 13 | #include <dt-bindings/pinctrl/at91.h> |
5e8b3bc3 | 14 | #include <dt-bindings/interrupt-controller/irq.h> |
92f8629b | 15 | #include <dt-bindings/gpio/gpio.h> |
d2e8190b | 16 | #include <dt-bindings/clk/at91.h> |
655ff266 LD |
17 | |
18 | / { | |
19 | model = "Atmel SAMA5D3 family SoC"; | |
20 | compatible = "atmel,sama5d3", "atmel,sama5"; | |
21 | interrupt-parent = <&aic>; | |
22 | ||
23 | aliases { | |
24 | serial0 = &dbgu; | |
25 | serial1 = &usart0; | |
26 | serial2 = &usart1; | |
27 | serial3 = &usart2; | |
28 | serial4 = &usart3; | |
29 | gpio0 = &pioA; | |
30 | gpio1 = &pioB; | |
31 | gpio2 = &pioC; | |
32 | gpio3 = &pioD; | |
33 | gpio4 = &pioE; | |
34 | tcb0 = &tcb0; | |
655ff266 LD |
35 | i2c0 = &i2c0; |
36 | i2c1 = &i2c1; | |
37 | i2c2 = &i2c2; | |
38 | ssc0 = &ssc0; | |
39 | ssc1 = &ssc1; | |
f3ab0527 | 40 | pwm0 = &pwm0; |
655ff266 LD |
41 | }; |
42 | cpus { | |
8b2efa89 AB |
43 | #address-cells = <1>; |
44 | #size-cells = <0>; | |
655ff266 | 45 | cpu@0 { |
e757a6ee | 46 | device_type = "cpu"; |
655ff266 | 47 | compatible = "arm,cortex-a5"; |
e757a6ee | 48 | reg = <0x0>; |
655ff266 LD |
49 | }; |
50 | }; | |
51 | ||
d9da9778 AB |
52 | pmu { |
53 | compatible = "arm,cortex-a5-pmu"; | |
54 | interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>; | |
55 | }; | |
56 | ||
655ff266 LD |
57 | memory { |
58 | reg = <0x20000000 0x8000000>; | |
59 | }; | |
60 | ||
d2e8190b BB |
61 | clocks { |
62 | adc_op_clk: adc_op_clk{ | |
63 | compatible = "fixed-clock"; | |
64 | #clock-cells = <0>; | |
65 | clock-frequency = <20000000>; | |
66 | }; | |
67 | }; | |
68 | ||
655ff266 LD |
69 | ahb { |
70 | compatible = "simple-bus"; | |
71 | #address-cells = <1>; | |
72 | #size-cells = <1>; | |
73 | ranges; | |
74 | ||
75 | apb { | |
76 | compatible = "simple-bus"; | |
77 | #address-cells = <1>; | |
78 | #size-cells = <1>; | |
79 | ranges; | |
80 | ||
81 | mmc0: mmc@f0000000 { | |
82 | compatible = "atmel,hsmci"; | |
83 | reg = <0xf0000000 0x600>; | |
5e8b3bc3 | 84 | interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>; |
d4ae89c8 | 85 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>; |
05c1bc97 | 86 | dma-names = "rxtx"; |
655ff266 LD |
87 | pinctrl-names = "default"; |
88 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>; | |
89 | status = "disabled"; | |
90 | #address-cells = <1>; | |
91 | #size-cells = <0>; | |
d2e8190b BB |
92 | clocks = <&mci0_clk>; |
93 | clock-names = "mci_clk"; | |
655ff266 LD |
94 | }; |
95 | ||
96 | spi0: spi@f0004000 { | |
97 | #address-cells = <1>; | |
98 | #size-cells = <0>; | |
b7ef678e | 99 | compatible = "atmel,at91rm9200-spi"; |
655ff266 | 100 | reg = <0xf0004000 0x100>; |
5e8b3bc3 | 101 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>; |
e543a73a NF |
102 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>, |
103 | <&dma0 2 AT91_DMA_CFG_PER_ID(2)>; | |
104 | dma-names = "tx", "rx"; | |
655ff266 LD |
105 | pinctrl-names = "default"; |
106 | pinctrl-0 = <&pinctrl_spi0>; | |
d2e8190b BB |
107 | clocks = <&spi0_clk>; |
108 | clock-names = "spi_clk"; | |
655ff266 LD |
109 | status = "disabled"; |
110 | }; | |
111 | ||
112 | ssc0: ssc@f0008000 { | |
113 | compatible = "atmel,at91sam9g45-ssc"; | |
114 | reg = <0xf0008000 0x4000>; | |
5e8b3bc3 | 115 | interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>; |
655ff266 LD |
116 | pinctrl-names = "default"; |
117 | pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>; | |
d2e8190b BB |
118 | clocks = <&ssc0_clk>; |
119 | clock-names = "pclk"; | |
655ff266 LD |
120 | status = "disabled"; |
121 | }; | |
122 | ||
655ff266 LD |
123 | tcb0: timer@f0010000 { |
124 | compatible = "atmel,at91sam9x5-tcb"; | |
125 | reg = <0xf0010000 0x100>; | |
5e8b3bc3 | 126 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; |
d2e8190b BB |
127 | clocks = <&tcb0_clk>; |
128 | clock-names = "t0_clk"; | |
655ff266 LD |
129 | }; |
130 | ||
131 | i2c0: i2c@f0014000 { | |
132 | compatible = "atmel,at91sam9x5-i2c"; | |
133 | reg = <0xf0014000 0x4000>; | |
5e8b3bc3 | 134 | interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>; |
d4ae89c8 LD |
135 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>, |
136 | <&dma0 2 AT91_DMA_CFG_PER_ID(8)>; | |
d9a63a45 | 137 | dma-names = "tx", "rx"; |
655ff266 LD |
138 | pinctrl-names = "default"; |
139 | pinctrl-0 = <&pinctrl_i2c0>; | |
140 | #address-cells = <1>; | |
141 | #size-cells = <0>; | |
d2e8190b | 142 | clocks = <&twi0_clk>; |
655ff266 LD |
143 | status = "disabled"; |
144 | }; | |
145 | ||
146 | i2c1: i2c@f0018000 { | |
147 | compatible = "atmel,at91sam9x5-i2c"; | |
148 | reg = <0xf0018000 0x4000>; | |
5e8b3bc3 | 149 | interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>; |
d4ae89c8 LD |
150 | dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>, |
151 | <&dma0 2 AT91_DMA_CFG_PER_ID(10)>; | |
d9a63a45 | 152 | dma-names = "tx", "rx"; |
655ff266 LD |
153 | pinctrl-names = "default"; |
154 | pinctrl-0 = <&pinctrl_i2c1>; | |
155 | #address-cells = <1>; | |
156 | #size-cells = <0>; | |
d2e8190b | 157 | clocks = <&twi1_clk>; |
655ff266 LD |
158 | status = "disabled"; |
159 | }; | |
160 | ||
161 | usart0: serial@f001c000 { | |
162 | compatible = "atmel,at91sam9260-usart"; | |
163 | reg = <0xf001c000 0x100>; | |
5e8b3bc3 | 164 | interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
165 | pinctrl-names = "default"; |
166 | pinctrl-0 = <&pinctrl_usart0>; | |
d2e8190b BB |
167 | clocks = <&usart0_clk>; |
168 | clock-names = "usart"; | |
655ff266 LD |
169 | status = "disabled"; |
170 | }; | |
171 | ||
172 | usart1: serial@f0020000 { | |
173 | compatible = "atmel,at91sam9260-usart"; | |
174 | reg = <0xf0020000 0x100>; | |
5e8b3bc3 | 175 | interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
176 | pinctrl-names = "default"; |
177 | pinctrl-0 = <&pinctrl_usart1>; | |
d2e8190b BB |
178 | clocks = <&usart1_clk>; |
179 | clock-names = "usart"; | |
655ff266 LD |
180 | status = "disabled"; |
181 | }; | |
f3ab0527 BS |
182 | |
183 | pwm0: pwm@f002c000 { | |
184 | compatible = "atmel,sama5d3-pwm"; | |
185 | reg = <0xf002c000 0x300>; | |
186 | interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>; | |
187 | #pwm-cells = <3>; | |
188 | clocks = <&pwm_clk>; | |
189 | status = "disabled"; | |
190 | }; | |
655ff266 | 191 | |
655ff266 LD |
192 | isi: isi@f0034000 { |
193 | compatible = "atmel,at91sam9g45-isi"; | |
194 | reg = <0xf0034000 0x4000>; | |
5e8b3bc3 | 195 | interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
196 | status = "disabled"; |
197 | }; | |
198 | ||
199 | mmc1: mmc@f8000000 { | |
200 | compatible = "atmel,hsmci"; | |
201 | reg = <0xf8000000 0x600>; | |
5e8b3bc3 | 202 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>; |
d4ae89c8 | 203 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>; |
05c1bc97 | 204 | dma-names = "rxtx"; |
655ff266 LD |
205 | pinctrl-names = "default"; |
206 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | |
207 | status = "disabled"; | |
208 | #address-cells = <1>; | |
209 | #size-cells = <0>; | |
d2e8190b BB |
210 | clocks = <&mci1_clk>; |
211 | clock-names = "mci_clk"; | |
655ff266 LD |
212 | }; |
213 | ||
655ff266 LD |
214 | spi1: spi@f8008000 { |
215 | #address-cells = <1>; | |
216 | #size-cells = <0>; | |
b7ef678e | 217 | compatible = "atmel,at91rm9200-spi"; |
655ff266 | 218 | reg = <0xf8008000 0x100>; |
5e8b3bc3 | 219 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>; |
e543a73a NF |
220 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>, |
221 | <&dma1 2 AT91_DMA_CFG_PER_ID(16)>; | |
222 | dma-names = "tx", "rx"; | |
655ff266 LD |
223 | pinctrl-names = "default"; |
224 | pinctrl-0 = <&pinctrl_spi1>; | |
d2e8190b BB |
225 | clocks = <&spi1_clk>; |
226 | clock-names = "spi_clk"; | |
655ff266 LD |
227 | status = "disabled"; |
228 | }; | |
229 | ||
230 | ssc1: ssc@f800c000 { | |
231 | compatible = "atmel,at91sam9g45-ssc"; | |
232 | reg = <0xf800c000 0x4000>; | |
5e8b3bc3 | 233 | interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>; |
655ff266 LD |
234 | pinctrl-names = "default"; |
235 | pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>; | |
d2e8190b BB |
236 | clocks = <&ssc1_clk>; |
237 | clock-names = "pclk"; | |
655ff266 LD |
238 | status = "disabled"; |
239 | }; | |
240 | ||
655ff266 LD |
241 | adc0: adc@f8018000 { |
242 | compatible = "atmel,at91sam9260-adc"; | |
243 | reg = <0xf8018000 0x100>; | |
5e8b3bc3 | 244 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
245 | pinctrl-names = "default"; |
246 | pinctrl-0 = < | |
247 | &pinctrl_adc0_adtrg | |
248 | &pinctrl_adc0_ad0 | |
249 | &pinctrl_adc0_ad1 | |
250 | &pinctrl_adc0_ad2 | |
251 | &pinctrl_adc0_ad3 | |
252 | &pinctrl_adc0_ad4 | |
253 | &pinctrl_adc0_ad5 | |
254 | &pinctrl_adc0_ad6 | |
255 | &pinctrl_adc0_ad7 | |
256 | &pinctrl_adc0_ad8 | |
257 | &pinctrl_adc0_ad9 | |
258 | &pinctrl_adc0_ad10 | |
259 | &pinctrl_adc0_ad11 | |
260 | >; | |
d2e8190b BB |
261 | clocks = <&adc_clk>, |
262 | <&adc_op_clk>; | |
263 | clock-names = "adc_clk", "adc_op_clk"; | |
655ff266 LD |
264 | atmel,adc-channel-base = <0x50>; |
265 | atmel,adc-channels-used = <0xfff>; | |
266 | atmel,adc-drdy-mask = <0x1000000>; | |
267 | atmel,adc-num-channels = <12>; | |
268 | atmel,adc-startup-time = <40>; | |
269 | atmel,adc-status-register = <0x30>; | |
270 | atmel,adc-trigger-register = <0xc0>; | |
271 | atmel,adc-use-external; | |
272 | atmel,adc-vref = <3000>; | |
273 | atmel,adc-res = <10 12>; | |
274 | atmel,adc-res-names = "lowres", "highres"; | |
275 | status = "disabled"; | |
276 | ||
277 | trigger@0 { | |
278 | trigger-name = "external-rising"; | |
279 | trigger-value = <0x1>; | |
280 | trigger-external; | |
281 | }; | |
282 | trigger@1 { | |
283 | trigger-name = "external-falling"; | |
284 | trigger-value = <0x2>; | |
285 | trigger-external; | |
286 | }; | |
287 | trigger@2 { | |
288 | trigger-name = "external-any"; | |
289 | trigger-value = <0x3>; | |
290 | trigger-external; | |
291 | }; | |
292 | trigger@3 { | |
293 | trigger-name = "continuous"; | |
294 | trigger-value = <0x6>; | |
295 | }; | |
296 | }; | |
297 | ||
298 | tsadcc: tsadcc@f8018000 { | |
299 | compatible = "atmel,at91sam9x5-tsadcc"; | |
300 | reg = <0xf8018000 0x4000>; | |
5e8b3bc3 | 301 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
302 | atmel,tsadcc_clock = <300000>; |
303 | atmel,filtering_average = <0x03>; | |
304 | atmel,pendet_debounce = <0x08>; | |
305 | atmel,pendet_sensitivity = <0x02>; | |
306 | atmel,ts_sample_hold_time = <0x0a>; | |
307 | status = "disabled"; | |
308 | }; | |
309 | ||
310 | i2c2: i2c@f801c000 { | |
311 | compatible = "atmel,at91sam9x5-i2c"; | |
312 | reg = <0xf801c000 0x4000>; | |
5e8b3bc3 | 313 | interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>; |
d4ae89c8 LD |
314 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>, |
315 | <&dma1 2 AT91_DMA_CFG_PER_ID(12)>; | |
d9a63a45 | 316 | dma-names = "tx", "rx"; |
557844ec NF |
317 | pinctrl-names = "default"; |
318 | pinctrl-0 = <&pinctrl_i2c2>; | |
655ff266 LD |
319 | #address-cells = <1>; |
320 | #size-cells = <0>; | |
d2e8190b | 321 | clocks = <&twi2_clk>; |
655ff266 LD |
322 | status = "disabled"; |
323 | }; | |
324 | ||
325 | usart2: serial@f8020000 { | |
326 | compatible = "atmel,at91sam9260-usart"; | |
327 | reg = <0xf8020000 0x100>; | |
5e8b3bc3 | 328 | interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
329 | pinctrl-names = "default"; |
330 | pinctrl-0 = <&pinctrl_usart2>; | |
d2e8190b BB |
331 | clocks = <&usart2_clk>; |
332 | clock-names = "usart"; | |
655ff266 LD |
333 | status = "disabled"; |
334 | }; | |
335 | ||
336 | usart3: serial@f8024000 { | |
337 | compatible = "atmel,at91sam9260-usart"; | |
338 | reg = <0xf8024000 0x100>; | |
5e8b3bc3 | 339 | interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>; |
655ff266 LD |
340 | pinctrl-names = "default"; |
341 | pinctrl-0 = <&pinctrl_usart3>; | |
d2e8190b BB |
342 | clocks = <&usart3_clk>; |
343 | clock-names = "usart"; | |
655ff266 LD |
344 | status = "disabled"; |
345 | }; | |
346 | ||
655ff266 | 347 | sha@f8034000 { |
c76f266d | 348 | compatible = "atmel,at91sam9g46-sha"; |
655ff266 | 349 | reg = <0xf8034000 0x100>; |
5e8b3bc3 | 350 | interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>; |
9860c515 NF |
351 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>; |
352 | dma-names = "tx"; | |
655ff266 LD |
353 | }; |
354 | ||
355 | aes@f8038000 { | |
c76f266d | 356 | compatible = "atmel,at91sam9g46-aes"; |
655ff266 | 357 | reg = <0xf8038000 0x100>; |
07f7d503 | 358 | interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>; |
9860c515 NF |
359 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>, |
360 | <&dma1 2 AT91_DMA_CFG_PER_ID(19)>; | |
361 | dma-names = "tx", "rx"; | |
655ff266 LD |
362 | }; |
363 | ||
364 | tdes@f803c000 { | |
c76f266d | 365 | compatible = "atmel,at91sam9g46-tdes"; |
655ff266 | 366 | reg = <0xf803c000 0x100>; |
5e8b3bc3 | 367 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>; |
9860c515 NF |
368 | dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>, |
369 | <&dma1 2 AT91_DMA_CFG_PER_ID(21)>; | |
370 | dma-names = "tx", "rx"; | |
655ff266 LD |
371 | }; |
372 | ||
373 | dma0: dma-controller@ffffe600 { | |
374 | compatible = "atmel,at91sam9g45-dma"; | |
375 | reg = <0xffffe600 0x200>; | |
5e8b3bc3 | 376 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>; |
980ce7d9 | 377 | #dma-cells = <2>; |
d2e8190b BB |
378 | clocks = <&dma0_clk>; |
379 | clock-names = "dma_clk"; | |
655ff266 LD |
380 | }; |
381 | ||
382 | dma1: dma-controller@ffffe800 { | |
383 | compatible = "atmel,at91sam9g45-dma"; | |
384 | reg = <0xffffe800 0x200>; | |
5e8b3bc3 | 385 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>; |
980ce7d9 | 386 | #dma-cells = <2>; |
d2e8190b BB |
387 | clocks = <&dma1_clk>; |
388 | clock-names = "dma_clk"; | |
655ff266 LD |
389 | }; |
390 | ||
391 | ramc0: ramc@ffffea00 { | |
392 | compatible = "atmel,at91sam9g45-ddramc"; | |
393 | reg = <0xffffea00 0x200>; | |
394 | }; | |
395 | ||
396 | dbgu: serial@ffffee00 { | |
397 | compatible = "atmel,at91sam9260-usart"; | |
398 | reg = <0xffffee00 0x200>; | |
5e8b3bc3 | 399 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; |
655ff266 LD |
400 | pinctrl-names = "default"; |
401 | pinctrl-0 = <&pinctrl_dbgu>; | |
d2e8190b BB |
402 | clocks = <&dbgu_clk>; |
403 | clock-names = "usart"; | |
655ff266 LD |
404 | status = "disabled"; |
405 | }; | |
406 | ||
407 | aic: interrupt-controller@fffff000 { | |
408 | #interrupt-cells = <3>; | |
409 | compatible = "atmel,sama5d3-aic"; | |
410 | interrupt-controller; | |
411 | reg = <0xfffff000 0x200>; | |
412 | atmel,external-irqs = <47>; | |
413 | }; | |
414 | ||
415 | pinctrl@fffff200 { | |
416 | #address-cells = <1>; | |
417 | #size-cells = <1>; | |
418 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | |
419 | ranges = <0xfffff200 0xfffff200 0xa00>; | |
420 | atmel,mux-mask = < | |
421 | /* A B C */ | |
422 | 0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */ | |
423 | 0xffffffff 0x0ff8ffff 0x00000000 /* pioB */ | |
424 | 0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */ | |
425 | 0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */ | |
426 | 0xffffffff 0xbf9f8000 0x18000000 /* pioE */ | |
427 | >; | |
428 | ||
429 | /* shared pinctrl settings */ | |
430 | adc0 { | |
431 | pinctrl_adc0_adtrg: adc0_adtrg { | |
432 | atmel,pins = | |
c9d0f317 | 433 | <AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */ |
655ff266 LD |
434 | }; |
435 | pinctrl_adc0_ad0: adc0_ad0 { | |
436 | atmel,pins = | |
c9d0f317 | 437 | <AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */ |
655ff266 LD |
438 | }; |
439 | pinctrl_adc0_ad1: adc0_ad1 { | |
440 | atmel,pins = | |
c9d0f317 | 441 | <AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */ |
655ff266 LD |
442 | }; |
443 | pinctrl_adc0_ad2: adc0_ad2 { | |
444 | atmel,pins = | |
c9d0f317 | 445 | <AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */ |
655ff266 LD |
446 | }; |
447 | pinctrl_adc0_ad3: adc0_ad3 { | |
448 | atmel,pins = | |
c9d0f317 | 449 | <AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */ |
655ff266 LD |
450 | }; |
451 | pinctrl_adc0_ad4: adc0_ad4 { | |
452 | atmel,pins = | |
c9d0f317 | 453 | <AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */ |
655ff266 LD |
454 | }; |
455 | pinctrl_adc0_ad5: adc0_ad5 { | |
456 | atmel,pins = | |
c9d0f317 | 457 | <AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */ |
655ff266 LD |
458 | }; |
459 | pinctrl_adc0_ad6: adc0_ad6 { | |
460 | atmel,pins = | |
c9d0f317 | 461 | <AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */ |
655ff266 LD |
462 | }; |
463 | pinctrl_adc0_ad7: adc0_ad7 { | |
464 | atmel,pins = | |
c9d0f317 | 465 | <AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */ |
655ff266 LD |
466 | }; |
467 | pinctrl_adc0_ad8: adc0_ad8 { | |
468 | atmel,pins = | |
c9d0f317 | 469 | <AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */ |
655ff266 LD |
470 | }; |
471 | pinctrl_adc0_ad9: adc0_ad9 { | |
472 | atmel,pins = | |
c9d0f317 | 473 | <AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */ |
655ff266 LD |
474 | }; |
475 | pinctrl_adc0_ad10: adc0_ad10 { | |
476 | atmel,pins = | |
c9d0f317 | 477 | <AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */ |
655ff266 LD |
478 | }; |
479 | pinctrl_adc0_ad11: adc0_ad11 { | |
480 | atmel,pins = | |
c9d0f317 | 481 | <AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */ |
655ff266 LD |
482 | }; |
483 | }; | |
484 | ||
655ff266 LD |
485 | dbgu { |
486 | pinctrl_dbgu: dbgu-0 { | |
487 | atmel,pins = | |
c9d0f317 JCPV |
488 | <AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */ |
489 | AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */ | |
655ff266 LD |
490 | }; |
491 | }; | |
492 | ||
493 | i2c0 { | |
494 | pinctrl_i2c0: i2c0-0 { | |
495 | atmel,pins = | |
c9d0f317 JCPV |
496 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */ |
497 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */ | |
655ff266 LD |
498 | }; |
499 | }; | |
500 | ||
501 | i2c1 { | |
502 | pinctrl_i2c1: i2c1-0 { | |
503 | atmel,pins = | |
c9d0f317 JCPV |
504 | <AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */ |
505 | AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */ | |
655ff266 LD |
506 | }; |
507 | }; | |
508 | ||
557844ec NF |
509 | i2c2 { |
510 | pinctrl_i2c2: i2c2-0 { | |
511 | atmel,pins = | |
512 | <AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */ | |
513 | AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */ | |
514 | }; | |
515 | }; | |
516 | ||
655ff266 LD |
517 | isi { |
518 | pinctrl_isi: isi-0 { | |
519 | atmel,pins = | |
c9d0f317 JCPV |
520 | <AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */ |
521 | AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */ | |
522 | AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */ | |
523 | AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */ | |
524 | AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */ | |
525 | AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */ | |
526 | AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */ | |
527 | AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */ | |
528 | AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */ | |
529 | AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */ | |
530 | AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */ | |
531 | AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */ | |
532 | AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */ | |
655ff266 LD |
533 | }; |
534 | pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 { | |
535 | atmel,pins = | |
c9d0f317 | 536 | <AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */ |
655ff266 LD |
537 | }; |
538 | }; | |
539 | ||
655ff266 LD |
540 | mmc0 { |
541 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | |
542 | atmel,pins = | |
c9d0f317 JCPV |
543 | <AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */ |
544 | AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */ | |
545 | AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */ | |
655ff266 LD |
546 | }; |
547 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | |
548 | atmel,pins = | |
c9d0f317 JCPV |
549 | <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */ |
550 | AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */ | |
551 | AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */ | |
655ff266 LD |
552 | }; |
553 | pinctrl_mmc0_dat4_7: mmc0_dat4_7 { | |
554 | atmel,pins = | |
c9d0f317 JCPV |
555 | <AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */ |
556 | AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */ | |
557 | AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */ | |
558 | AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */ | |
655ff266 LD |
559 | }; |
560 | }; | |
561 | ||
562 | mmc1 { | |
563 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | |
564 | atmel,pins = | |
c9d0f317 JCPV |
565 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */ |
566 | AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */ | |
567 | AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */ | |
655ff266 LD |
568 | }; |
569 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | |
570 | atmel,pins = | |
c9d0f317 JCPV |
571 | <AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */ |
572 | AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */ | |
573 | AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */ | |
655ff266 LD |
574 | }; |
575 | }; | |
576 | ||
655ff266 LD |
577 | nand0 { |
578 | pinctrl_nand0_ale_cle: nand0_ale_cle-0 { | |
579 | atmel,pins = | |
c9d0f317 JCPV |
580 | <AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */ |
581 | AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */ | |
655ff266 LD |
582 | }; |
583 | }; | |
584 | ||
655ff266 LD |
585 | spi0 { |
586 | pinctrl_spi0: spi0-0 { | |
587 | atmel,pins = | |
c9d0f317 JCPV |
588 | <AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */ |
589 | AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */ | |
590 | AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */ | |
655ff266 LD |
591 | }; |
592 | }; | |
593 | ||
594 | spi1 { | |
595 | pinctrl_spi1: spi1-0 { | |
596 | atmel,pins = | |
c9d0f317 JCPV |
597 | <AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */ |
598 | AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */ | |
599 | AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */ | |
655ff266 LD |
600 | }; |
601 | }; | |
602 | ||
603 | ssc0 { | |
604 | pinctrl_ssc0_tx: ssc0_tx { | |
605 | atmel,pins = | |
c9d0f317 JCPV |
606 | <AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */ |
607 | AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */ | |
608 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */ | |
655ff266 LD |
609 | }; |
610 | ||
611 | pinctrl_ssc0_rx: ssc0_rx { | |
612 | atmel,pins = | |
c9d0f317 JCPV |
613 | <AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */ |
614 | AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */ | |
615 | AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */ | |
655ff266 LD |
616 | }; |
617 | }; | |
618 | ||
619 | ssc1 { | |
620 | pinctrl_ssc1_tx: ssc1_tx { | |
621 | atmel,pins = | |
c9d0f317 JCPV |
622 | <AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */ |
623 | AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */ | |
624 | AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */ | |
655ff266 LD |
625 | }; |
626 | ||
627 | pinctrl_ssc1_rx: ssc1_rx { | |
628 | atmel,pins = | |
c9d0f317 JCPV |
629 | <AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */ |
630 | AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */ | |
631 | AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */ | |
655ff266 LD |
632 | }; |
633 | }; | |
634 | ||
655ff266 LD |
635 | usart0 { |
636 | pinctrl_usart0: usart0-0 { | |
637 | atmel,pins = | |
c9d0f317 JCPV |
638 | <AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */ |
639 | AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */ | |
655ff266 LD |
640 | }; |
641 | ||
642 | pinctrl_usart0_rts_cts: usart0_rts_cts-0 { | |
643 | atmel,pins = | |
c9d0f317 JCPV |
644 | <AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */ |
645 | AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */ | |
655ff266 LD |
646 | }; |
647 | }; | |
648 | ||
649 | usart1 { | |
650 | pinctrl_usart1: usart1-0 { | |
651 | atmel,pins = | |
c9d0f317 JCPV |
652 | <AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */ |
653 | AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */ | |
655ff266 LD |
654 | }; |
655 | ||
656 | pinctrl_usart1_rts_cts: usart1_rts_cts-0 { | |
657 | atmel,pins = | |
c9d0f317 JCPV |
658 | <AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */ |
659 | AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */ | |
655ff266 LD |
660 | }; |
661 | }; | |
662 | ||
663 | usart2 { | |
664 | pinctrl_usart2: usart2-0 { | |
665 | atmel,pins = | |
c9d0f317 JCPV |
666 | <AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */ |
667 | AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */ | |
655ff266 LD |
668 | }; |
669 | ||
670 | pinctrl_usart2_rts_cts: usart2_rts_cts-0 { | |
671 | atmel,pins = | |
c9d0f317 JCPV |
672 | <AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */ |
673 | AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */ | |
655ff266 LD |
674 | }; |
675 | }; | |
676 | ||
677 | usart3 { | |
678 | pinctrl_usart3: usart3-0 { | |
679 | atmel,pins = | |
c9d0f317 JCPV |
680 | <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */ |
681 | AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */ | |
655ff266 LD |
682 | }; |
683 | ||
684 | pinctrl_usart3_rts_cts: usart3_rts_cts-0 { | |
685 | atmel,pins = | |
c9d0f317 JCPV |
686 | <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */ |
687 | AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */ | |
655ff266 LD |
688 | }; |
689 | }; | |
c9d0f317 JCPV |
690 | |
691 | ||
692 | pioA: gpio@fffff200 { | |
693 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
694 | reg = <0xfffff200 0x100>; | |
5e8b3bc3 | 695 | interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
696 | #gpio-cells = <2>; |
697 | gpio-controller; | |
698 | interrupt-controller; | |
699 | #interrupt-cells = <2>; | |
d2e8190b | 700 | clocks = <&pioA_clk>; |
c9d0f317 JCPV |
701 | }; |
702 | ||
703 | pioB: gpio@fffff400 { | |
704 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
705 | reg = <0xfffff400 0x100>; | |
5e8b3bc3 | 706 | interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
707 | #gpio-cells = <2>; |
708 | gpio-controller; | |
709 | interrupt-controller; | |
710 | #interrupt-cells = <2>; | |
d2e8190b | 711 | clocks = <&pioB_clk>; |
c9d0f317 JCPV |
712 | }; |
713 | ||
714 | pioC: gpio@fffff600 { | |
715 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
716 | reg = <0xfffff600 0x100>; | |
5e8b3bc3 | 717 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
718 | #gpio-cells = <2>; |
719 | gpio-controller; | |
720 | interrupt-controller; | |
721 | #interrupt-cells = <2>; | |
d2e8190b | 722 | clocks = <&pioC_clk>; |
c9d0f317 JCPV |
723 | }; |
724 | ||
725 | pioD: gpio@fffff800 { | |
726 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
727 | reg = <0xfffff800 0x100>; | |
5e8b3bc3 | 728 | interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
729 | #gpio-cells = <2>; |
730 | gpio-controller; | |
731 | interrupt-controller; | |
732 | #interrupt-cells = <2>; | |
d2e8190b | 733 | clocks = <&pioD_clk>; |
c9d0f317 JCPV |
734 | }; |
735 | ||
736 | pioE: gpio@fffffa00 { | |
737 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
738 | reg = <0xfffffa00 0x100>; | |
5e8b3bc3 | 739 | interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>; |
c9d0f317 JCPV |
740 | #gpio-cells = <2>; |
741 | gpio-controller; | |
742 | interrupt-controller; | |
743 | #interrupt-cells = <2>; | |
d2e8190b | 744 | clocks = <&pioE_clk>; |
c9d0f317 | 745 | }; |
655ff266 LD |
746 | }; |
747 | ||
748 | pmc: pmc@fffffc00 { | |
d2e8190b | 749 | compatible = "atmel,sama5d3-pmc"; |
655ff266 | 750 | reg = <0xfffffc00 0x120>; |
d2e8190b BB |
751 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
752 | interrupt-controller; | |
753 | #address-cells = <1>; | |
754 | #size-cells = <0>; | |
755 | #interrupt-cells = <1>; | |
756 | ||
757 | clk32k: slck { | |
758 | compatible = "fixed-clock"; | |
759 | #clock-cells = <0>; | |
760 | clock-frequency = <32768>; | |
761 | }; | |
762 | ||
763 | main: mainck { | |
764 | compatible = "atmel,at91rm9200-clk-main"; | |
765 | #clock-cells = <0>; | |
766 | interrupt-parent = <&pmc>; | |
767 | interrupts = <AT91_PMC_MOSCS>; | |
768 | clocks = <&clk32k>; | |
769 | }; | |
770 | ||
771 | plla: pllack { | |
772 | compatible = "atmel,sama5d3-clk-pll"; | |
773 | #clock-cells = <0>; | |
774 | interrupt-parent = <&pmc>; | |
775 | interrupts = <AT91_PMC_LOCKA>; | |
776 | clocks = <&main>; | |
777 | reg = <0>; | |
778 | atmel,clk-input-range = <8000000 50000000>; | |
779 | #atmel,pll-clk-output-range-cells = <4>; | |
780 | atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>; | |
781 | }; | |
782 | ||
783 | plladiv: plladivck { | |
784 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
785 | #clock-cells = <0>; | |
786 | clocks = <&plla>; | |
787 | }; | |
788 | ||
789 | utmi: utmick { | |
790 | compatible = "atmel,at91sam9x5-clk-utmi"; | |
791 | #clock-cells = <0>; | |
792 | interrupt-parent = <&pmc>; | |
793 | interrupts = <AT91_PMC_LOCKU>; | |
794 | clocks = <&main>; | |
795 | }; | |
796 | ||
797 | mck: masterck { | |
798 | compatible = "atmel,at91sam9x5-clk-master"; | |
799 | #clock-cells = <0>; | |
800 | interrupt-parent = <&pmc>; | |
801 | interrupts = <AT91_PMC_MCKRDY>; | |
802 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | |
803 | atmel,clk-output-range = <0 166000000>; | |
804 | atmel,clk-divisors = <1 2 4 3>; | |
805 | }; | |
806 | ||
807 | usb: usbck { | |
808 | compatible = "atmel,at91sam9x5-clk-usb"; | |
809 | #clock-cells = <0>; | |
810 | clocks = <&plladiv>, <&utmi>; | |
811 | }; | |
812 | ||
813 | prog: progck { | |
814 | compatible = "atmel,at91sam9x5-clk-programmable"; | |
815 | #address-cells = <1>; | |
816 | #size-cells = <0>; | |
817 | interrupt-parent = <&pmc>; | |
818 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
819 | ||
820 | prog0: prog0 { | |
821 | #clock-cells = <0>; | |
822 | reg = <0>; | |
823 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
824 | }; | |
825 | ||
826 | prog1: prog1 { | |
827 | #clock-cells = <0>; | |
828 | reg = <1>; | |
829 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
830 | }; | |
831 | ||
832 | prog2: prog2 { | |
833 | #clock-cells = <0>; | |
834 | reg = <2>; | |
835 | interrupts = <AT91_PMC_PCKRDY(2)>; | |
836 | }; | |
837 | }; | |
838 | ||
839 | smd: smdclk { | |
840 | compatible = "atmel,at91sam9x5-clk-smd"; | |
841 | #clock-cells = <0>; | |
842 | clocks = <&plladiv>, <&utmi>; | |
843 | }; | |
844 | ||
845 | systemck { | |
846 | compatible = "atmel,at91rm9200-clk-system"; | |
847 | #address-cells = <1>; | |
848 | #size-cells = <0>; | |
849 | ||
850 | ddrck: ddrck { | |
851 | #clock-cells = <0>; | |
852 | reg = <2>; | |
853 | clocks = <&mck>; | |
854 | }; | |
855 | ||
856 | smdck: smdck { | |
857 | #clock-cells = <0>; | |
858 | reg = <4>; | |
859 | clocks = <&smd>; | |
860 | }; | |
861 | ||
862 | uhpck: uhpck { | |
863 | #clock-cells = <0>; | |
864 | reg = <6>; | |
865 | clocks = <&usb>; | |
866 | }; | |
867 | ||
868 | udpck: udpck { | |
869 | #clock-cells = <0>; | |
870 | reg = <7>; | |
871 | clocks = <&usb>; | |
872 | }; | |
873 | ||
874 | pck0: pck0 { | |
875 | #clock-cells = <0>; | |
876 | reg = <8>; | |
877 | clocks = <&prog0>; | |
878 | }; | |
879 | ||
880 | pck1: pck1 { | |
881 | #clock-cells = <0>; | |
882 | reg = <9>; | |
883 | clocks = <&prog1>; | |
884 | }; | |
885 | ||
886 | pck2: pck2 { | |
887 | #clock-cells = <0>; | |
888 | reg = <10>; | |
889 | clocks = <&prog2>; | |
890 | }; | |
891 | }; | |
892 | ||
893 | periphck { | |
894 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
895 | #address-cells = <1>; | |
896 | #size-cells = <0>; | |
897 | clocks = <&mck>; | |
898 | ||
899 | dbgu_clk: dbgu_clk { | |
900 | #clock-cells = <0>; | |
901 | reg = <2>; | |
902 | }; | |
903 | ||
904 | pioA_clk: pioA_clk { | |
905 | #clock-cells = <0>; | |
906 | reg = <6>; | |
907 | }; | |
908 | ||
909 | pioB_clk: pioB_clk { | |
910 | #clock-cells = <0>; | |
911 | reg = <7>; | |
912 | }; | |
913 | ||
914 | pioC_clk: pioC_clk { | |
915 | #clock-cells = <0>; | |
916 | reg = <8>; | |
917 | }; | |
918 | ||
919 | pioD_clk: pioD_clk { | |
920 | #clock-cells = <0>; | |
921 | reg = <9>; | |
922 | }; | |
923 | ||
924 | pioE_clk: pioE_clk { | |
925 | #clock-cells = <0>; | |
926 | reg = <10>; | |
927 | }; | |
928 | ||
929 | usart0_clk: usart0_clk { | |
930 | #clock-cells = <0>; | |
931 | reg = <12>; | |
932 | atmel,clk-output-range = <0 66000000>; | |
933 | }; | |
934 | ||
935 | usart1_clk: usart1_clk { | |
936 | #clock-cells = <0>; | |
937 | reg = <13>; | |
938 | atmel,clk-output-range = <0 66000000>; | |
939 | }; | |
940 | ||
941 | usart2_clk: usart2_clk { | |
942 | #clock-cells = <0>; | |
943 | reg = <14>; | |
944 | atmel,clk-output-range = <0 66000000>; | |
945 | }; | |
946 | ||
947 | usart3_clk: usart3_clk { | |
948 | #clock-cells = <0>; | |
949 | reg = <15>; | |
950 | atmel,clk-output-range = <0 66000000>; | |
951 | }; | |
952 | ||
953 | twi0_clk: twi0_clk { | |
954 | reg = <18>; | |
955 | #clock-cells = <0>; | |
956 | atmel,clk-output-range = <0 16625000>; | |
957 | }; | |
958 | ||
959 | twi1_clk: twi1_clk { | |
960 | #clock-cells = <0>; | |
961 | reg = <19>; | |
962 | atmel,clk-output-range = <0 16625000>; | |
963 | }; | |
964 | ||
965 | twi2_clk: twi2_clk { | |
966 | #clock-cells = <0>; | |
967 | reg = <20>; | |
968 | atmel,clk-output-range = <0 16625000>; | |
969 | }; | |
970 | ||
971 | mci0_clk: mci0_clk { | |
972 | #clock-cells = <0>; | |
973 | reg = <21>; | |
974 | }; | |
975 | ||
976 | mci1_clk: mci1_clk { | |
977 | #clock-cells = <0>; | |
978 | reg = <22>; | |
979 | }; | |
980 | ||
981 | spi0_clk: spi0_clk { | |
982 | #clock-cells = <0>; | |
983 | reg = <24>; | |
984 | atmel,clk-output-range = <0 133000000>; | |
985 | }; | |
986 | ||
987 | spi1_clk: spi1_clk { | |
988 | #clock-cells = <0>; | |
989 | reg = <25>; | |
990 | atmel,clk-output-range = <0 133000000>; | |
991 | }; | |
992 | ||
993 | tcb0_clk: tcb0_clk { | |
994 | #clock-cells = <0>; | |
995 | reg = <26>; | |
996 | atmel,clk-output-range = <0 133000000>; | |
997 | }; | |
998 | ||
999 | pwm_clk: pwm_clk { | |
1000 | #clock-cells = <0>; | |
1001 | reg = <28>; | |
1002 | }; | |
1003 | ||
1004 | adc_clk: adc_clk { | |
1005 | #clock-cells = <0>; | |
1006 | reg = <29>; | |
1007 | atmel,clk-output-range = <0 66000000>; | |
1008 | }; | |
1009 | ||
1010 | dma0_clk: dma0_clk { | |
1011 | #clock-cells = <0>; | |
1012 | reg = <30>; | |
1013 | }; | |
1014 | ||
1015 | dma1_clk: dma1_clk { | |
1016 | #clock-cells = <0>; | |
1017 | reg = <31>; | |
1018 | }; | |
1019 | ||
1020 | uhphs_clk: uhphs_clk { | |
1021 | #clock-cells = <0>; | |
1022 | reg = <32>; | |
1023 | }; | |
1024 | ||
1025 | udphs_clk: udphs_clk { | |
1026 | #clock-cells = <0>; | |
1027 | reg = <33>; | |
1028 | }; | |
1029 | ||
1030 | isi_clk: isi_clk { | |
1031 | #clock-cells = <0>; | |
1032 | reg = <37>; | |
1033 | }; | |
1034 | ||
1035 | ssc0_clk: ssc0_clk { | |
1036 | #clock-cells = <0>; | |
1037 | reg = <38>; | |
1038 | atmel,clk-output-range = <0 66000000>; | |
1039 | }; | |
1040 | ||
1041 | ssc1_clk: ssc1_clk { | |
1042 | #clock-cells = <0>; | |
1043 | reg = <39>; | |
1044 | atmel,clk-output-range = <0 66000000>; | |
1045 | }; | |
1046 | ||
1047 | sha_clk: sha_clk { | |
1048 | #clock-cells = <0>; | |
1049 | reg = <42>; | |
1050 | }; | |
1051 | ||
1052 | aes_clk: aes_clk { | |
1053 | #clock-cells = <0>; | |
1054 | reg = <43>; | |
1055 | }; | |
1056 | ||
1057 | tdes_clk: tdes_clk { | |
1058 | #clock-cells = <0>; | |
1059 | reg = <44>; | |
1060 | }; | |
1061 | ||
1062 | trng_clk: trng_clk { | |
1063 | #clock-cells = <0>; | |
1064 | reg = <45>; | |
1065 | }; | |
1066 | ||
1067 | fuse_clk: fuse_clk { | |
1068 | #clock-cells = <0>; | |
1069 | reg = <48>; | |
1070 | }; | |
1071 | }; | |
655ff266 LD |
1072 | }; |
1073 | ||
1074 | rstc@fffffe00 { | |
1075 | compatible = "atmel,at91sam9g45-rstc"; | |
1076 | reg = <0xfffffe00 0x10>; | |
1077 | }; | |
1078 | ||
1079 | pit: timer@fffffe30 { | |
1080 | compatible = "atmel,at91sam9260-pit"; | |
1081 | reg = <0xfffffe30 0xf>; | |
5e8b3bc3 | 1082 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
d2e8190b | 1083 | clocks = <&mck>; |
655ff266 LD |
1084 | }; |
1085 | ||
1086 | watchdog@fffffe40 { | |
1087 | compatible = "atmel,at91sam9260-wdt"; | |
1088 | reg = <0xfffffe40 0x10>; | |
1089 | status = "disabled"; | |
1090 | }; | |
1091 | ||
1092 | rtc@fffffeb0 { | |
1093 | compatible = "atmel,at91rm9200-rtc"; | |
1094 | reg = <0xfffffeb0 0x30>; | |
5e8b3bc3 | 1095 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; |
655ff266 LD |
1096 | }; |
1097 | }; | |
1098 | ||
1099 | usb0: gadget@00500000 { | |
1100 | #address-cells = <1>; | |
1101 | #size-cells = <0>; | |
1102 | compatible = "atmel,at91sam9rl-udc"; | |
1103 | reg = <0x00500000 0x100000 | |
1104 | 0xf8030000 0x4000>; | |
5e8b3bc3 | 1105 | interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>; |
d2e8190b BB |
1106 | clocks = <&udphs_clk>, <&utmi>; |
1107 | clock-names = "pclk", "hclk"; | |
655ff266 LD |
1108 | status = "disabled"; |
1109 | ||
1110 | ep0 { | |
1111 | reg = <0>; | |
1112 | atmel,fifo-size = <64>; | |
1113 | atmel,nb-banks = <1>; | |
1114 | }; | |
1115 | ||
1116 | ep1 { | |
1117 | reg = <1>; | |
1118 | atmel,fifo-size = <1024>; | |
1119 | atmel,nb-banks = <3>; | |
1120 | atmel,can-dma; | |
1121 | atmel,can-isoc; | |
1122 | }; | |
1123 | ||
1124 | ep2 { | |
1125 | reg = <2>; | |
1126 | atmel,fifo-size = <1024>; | |
1127 | atmel,nb-banks = <3>; | |
1128 | atmel,can-dma; | |
1129 | atmel,can-isoc; | |
1130 | }; | |
1131 | ||
1132 | ep3 { | |
1133 | reg = <3>; | |
1134 | atmel,fifo-size = <1024>; | |
1135 | atmel,nb-banks = <2>; | |
1136 | atmel,can-dma; | |
1137 | }; | |
1138 | ||
1139 | ep4 { | |
1140 | reg = <4>; | |
1141 | atmel,fifo-size = <1024>; | |
1142 | atmel,nb-banks = <2>; | |
1143 | atmel,can-dma; | |
1144 | }; | |
1145 | ||
1146 | ep5 { | |
1147 | reg = <5>; | |
1148 | atmel,fifo-size = <1024>; | |
1149 | atmel,nb-banks = <2>; | |
1150 | atmel,can-dma; | |
1151 | }; | |
1152 | ||
1153 | ep6 { | |
1154 | reg = <6>; | |
1155 | atmel,fifo-size = <1024>; | |
1156 | atmel,nb-banks = <2>; | |
1157 | atmel,can-dma; | |
1158 | }; | |
1159 | ||
1160 | ep7 { | |
1161 | reg = <7>; | |
1162 | atmel,fifo-size = <1024>; | |
1163 | atmel,nb-banks = <2>; | |
1164 | atmel,can-dma; | |
1165 | }; | |
1166 | ||
1167 | ep8 { | |
1168 | reg = <8>; | |
1169 | atmel,fifo-size = <1024>; | |
1170 | atmel,nb-banks = <2>; | |
1171 | }; | |
1172 | ||
1173 | ep9 { | |
1174 | reg = <9>; | |
1175 | atmel,fifo-size = <1024>; | |
1176 | atmel,nb-banks = <2>; | |
1177 | }; | |
1178 | ||
1179 | ep10 { | |
1180 | reg = <10>; | |
1181 | atmel,fifo-size = <1024>; | |
1182 | atmel,nb-banks = <2>; | |
1183 | }; | |
1184 | ||
1185 | ep11 { | |
1186 | reg = <11>; | |
1187 | atmel,fifo-size = <1024>; | |
1188 | atmel,nb-banks = <2>; | |
1189 | }; | |
1190 | ||
1191 | ep12 { | |
1192 | reg = <12>; | |
1193 | atmel,fifo-size = <1024>; | |
1194 | atmel,nb-banks = <2>; | |
1195 | }; | |
1196 | ||
1197 | ep13 { | |
1198 | reg = <13>; | |
1199 | atmel,fifo-size = <1024>; | |
1200 | atmel,nb-banks = <2>; | |
1201 | }; | |
1202 | ||
1203 | ep14 { | |
1204 | reg = <14>; | |
1205 | atmel,fifo-size = <1024>; | |
1206 | atmel,nb-banks = <2>; | |
1207 | }; | |
1208 | ||
1209 | ep15 { | |
1210 | reg = <15>; | |
1211 | atmel,fifo-size = <1024>; | |
1212 | atmel,nb-banks = <2>; | |
1213 | }; | |
1214 | }; | |
1215 | ||
1216 | usb1: ohci@00600000 { | |
1217 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
1218 | reg = <0x00600000 0x100000>; | |
5e8b3bc3 | 1219 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
d2e8190b BB |
1220 | clocks = <&usb>, <&uhphs_clk>, <&udphs_clk>, |
1221 | <&uhpck>; | |
1222 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
655ff266 LD |
1223 | status = "disabled"; |
1224 | }; | |
1225 | ||
1226 | usb2: ehci@00700000 { | |
1227 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
1228 | reg = <0x00700000 0x100000>; | |
5e8b3bc3 | 1229 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>; |
d2e8190b BB |
1230 | clocks = <&usb>, <&uhphs_clk>, <&uhpck>; |
1231 | clock-names = "usb_clk", "ehci_clk", "uhpck"; | |
655ff266 LD |
1232 | status = "disabled"; |
1233 | }; | |
1234 | ||
1235 | nand0: nand@60000000 { | |
1236 | compatible = "atmel,at91rm9200-nand"; | |
1237 | #address-cells = <1>; | |
1238 | #size-cells = <1>; | |
8ae599ef | 1239 | ranges; |
655ff266 LD |
1240 | reg = < 0x60000000 0x01000000 /* EBI CS3 */ |
1241 | 0xffffc070 0x00000490 /* SMC PMECC regs */ | |
1242 | 0xffffc500 0x00000100 /* SMC PMECC Error Location regs */ | |
afa6a2a7 | 1243 | 0x00110000 0x00018000 /* ROM code */ |
655ff266 | 1244 | >; |
5e8b3bc3 | 1245 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>; |
655ff266 LD |
1246 | atmel,nand-addr-offset = <21>; |
1247 | atmel,nand-cmd-offset = <22>; | |
1248 | pinctrl-names = "default"; | |
1249 | pinctrl-0 = <&pinctrl_nand0_ale_cle>; | |
afa6a2a7 | 1250 | atmel,pmecc-lookup-table-offset = <0x0 0x8000>; |
655ff266 | 1251 | status = "disabled"; |
8ae599ef JW |
1252 | |
1253 | nfc@70000000 { | |
1254 | compatible = "atmel,sama5d3-nfc"; | |
1255 | #address-cells = <1>; | |
1256 | #size-cells = <1>; | |
1257 | reg = < | |
1258 | 0x70000000 0x10000000 /* NFC Command Registers */ | |
1259 | 0xffffc000 0x00000070 /* NFC HSMC regs */ | |
1260 | 0x00200000 0x00100000 /* NFC SRAM banks */ | |
1261 | >; | |
1262 | }; | |
655ff266 LD |
1263 | }; |
1264 | }; | |
1265 | }; |