Merge remote-tracking branch 'regmap/topic/core' into regmap-next
[deliverable/linux.git] / arch / arm / boot / dts / sama5d4.dtsi
CommitLineData
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1/*
2 * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC
3 *
4 * Copyright (C) 2014 Atmel,
5 * 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
1d2a0563 12 * a) This file is free software; you can redistribute it and/or
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13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
1d2a0563 17 * This file is distributed in the hope that it will be useful,
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18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/clock/at91.h>
b3c7a497 48#include <dt-bindings/dma/at91.h>
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49#include <dt-bindings/pinctrl/at91.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/gpio/gpio.h>
52
53/ {
54 model = "Atmel SAMA5D4 family SoC";
55 compatible = "atmel,sama5d4";
56 interrupt-parent = <&aic>;
57
58 aliases {
59 serial0 = &usart3;
60 serial1 = &usart4;
61 serial2 = &usart2;
62 gpio0 = &pioA;
63 gpio1 = &pioB;
64 gpio2 = &pioC;
65 gpio4 = &pioE;
66 tcb0 = &tcb0;
67 tcb1 = &tcb1;
68 i2c2 = &i2c2;
69 };
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
74 cpu@0 {
75 device_type = "cpu";
76 compatible = "arm,cortex-a5";
77 reg = <0>;
78 next-level-cache = <&L2>;
79 };
80 };
81
82 memory {
83 reg = <0x20000000 0x20000000>;
84 };
85
86 clocks {
87 slow_xtal: slow_xtal {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <0>;
91 };
92
93 main_xtal: main_xtal {
94 compatible = "fixed-clock";
95 #clock-cells = <0>;
96 clock-frequency = <0>;
97 };
98
99 adc_op_clk: adc_op_clk{
100 compatible = "fixed-clock";
101 #clock-cells = <0>;
102 clock-frequency = <1000000>;
103 };
104 };
105
106 ahb {
107 compatible = "simple-bus";
108 #address-cells = <1>;
109 #size-cells = <1>;
110 ranges;
111
112 usb0: gadget@00400000 {
113 #address-cells = <1>;
114 #size-cells = <0>;
115 compatible = "atmel,at91sam9rl-udc";
116 reg = <0x00400000 0x100000
117 0xfc02c000 0x4000>;
118 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>;
119 clocks = <&udphs_clk>, <&utmi>;
120 clock-names = "pclk", "hclk";
121 status = "disabled";
122
123 ep0 {
124 reg = <0>;
125 atmel,fifo-size = <64>;
126 atmel,nb-banks = <1>;
127 };
128
129 ep1 {
130 reg = <1>;
131 atmel,fifo-size = <1024>;
132 atmel,nb-banks = <3>;
133 atmel,can-dma;
134 atmel,can-isoc;
135 };
136
137 ep2 {
138 reg = <2>;
139 atmel,fifo-size = <1024>;
140 atmel,nb-banks = <3>;
141 atmel,can-dma;
142 atmel,can-isoc;
143 };
144
145 ep3 {
146 reg = <3>;
147 atmel,fifo-size = <1024>;
148 atmel,nb-banks = <2>;
149 atmel,can-dma;
150 atmel,can-isoc;
151 };
152
153 ep4 {
154 reg = <4>;
155 atmel,fifo-size = <1024>;
156 atmel,nb-banks = <2>;
157 atmel,can-dma;
158 atmel,can-isoc;
159 };
160
161 ep5 {
162 reg = <5>;
163 atmel,fifo-size = <1024>;
164 atmel,nb-banks = <2>;
165 atmel,can-dma;
166 atmel,can-isoc;
167 };
168
169 ep6 {
170 reg = <6>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <2>;
173 atmel,can-dma;
174 atmel,can-isoc;
175 };
176
177 ep7 {
178 reg = <7>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <2>;
181 atmel,can-dma;
182 atmel,can-isoc;
183 };
184
185 ep8 {
186 reg = <8>;
187 atmel,fifo-size = <1024>;
188 atmel,nb-banks = <2>;
189 atmel,can-isoc;
190 };
191
192 ep9 {
193 reg = <9>;
194 atmel,fifo-size = <1024>;
195 atmel,nb-banks = <2>;
196 atmel,can-isoc;
197 };
198
199 ep10 {
200 reg = <10>;
201 atmel,fifo-size = <1024>;
202 atmel,nb-banks = <2>;
203 atmel,can-isoc;
204 };
205
206 ep11 {
207 reg = <11>;
208 atmel,fifo-size = <1024>;
209 atmel,nb-banks = <2>;
210 atmel,can-isoc;
211 };
212
213 ep12 {
214 reg = <12>;
215 atmel,fifo-size = <1024>;
216 atmel,nb-banks = <2>;
217 atmel,can-isoc;
218 };
219
220 ep13 {
221 reg = <13>;
222 atmel,fifo-size = <1024>;
223 atmel,nb-banks = <2>;
224 atmel,can-isoc;
225 };
226
227 ep14 {
228 reg = <14>;
229 atmel,fifo-size = <1024>;
230 atmel,nb-banks = <2>;
231 atmel,can-isoc;
232 };
233
234 ep15 {
235 reg = <15>;
236 atmel,fifo-size = <1024>;
237 atmel,nb-banks = <2>;
238 atmel,can-isoc;
239 };
240 };
241
242 usb1: ohci@00500000 {
243 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
244 reg = <0x00500000 0x100000>;
245 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
246 clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
247 <&uhpck>;
248 clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
249 status = "disabled";
250 };
251
252 usb2: ehci@00600000 {
253 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
254 reg = <0x00600000 0x100000>;
255 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>;
256 clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
257 clock-names = "usb_clk", "ehci_clk", "uhpck";
258 status = "disabled";
259 };
260
261 L2: cache-controller@00a00000 {
262 compatible = "arm,pl310-cache";
263 reg = <0x00a00000 0x1000>;
264 interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>;
265 cache-unified;
266 cache-level = <2>;
267 };
268
269 nand0: nand@80000000 {
270 compatible = "atmel,at91rm9200-nand";
271 #address-cells = <1>;
272 #size-cells = <1>;
273 ranges;
274 reg = < 0x80000000 0x08000000 /* EBI CS3 */
275 0xfc05c070 0x00000490 /* SMC PMECC regs */
276 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */
277 >;
278 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>;
279 atmel,nand-addr-offset = <21>;
280 atmel,nand-cmd-offset = <22>;
281 atmel,nand-has-dma;
282 pinctrl-names = "default";
283 pinctrl-0 = <&pinctrl_nand>;
284 status = "disabled";
285
286 nfc@90000000 {
287 compatible = "atmel,sama5d3-nfc";
288 #address-cells = <1>;
289 #size-cells = <1>;
290 reg = <
291 0x90000000 0x10000000 /* NFC Command Registers */
292 0xfc05c000 0x00000070 /* NFC HSMC regs */
293 0x00100000 0x00100000 /* NFC SRAM banks */
294 >;
295 clocks = <&hsmc_clk>;
296 atmel,write-by-sram;
297 };
298 };
299
300 apb {
301 compatible = "simple-bus";
302 #address-cells = <1>;
303 #size-cells = <1>;
304 ranges;
305
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306 dma1: dma-controller@f0004000 {
307 compatible = "atmel,sama5d4-dma";
308 reg = <0xf0004000 0x200>;
309 interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>;
310 #dma-cells = <1>;
311 clocks = <&dma1_clk>;
312 clock-names = "dma_clk";
313 };
314
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315 ramc0: ramc@f0010000 {
316 compatible = "atmel,sama5d3-ddramc";
317 reg = <0xf0010000 0x200>;
318 clocks = <&ddrck>, <&mpddr_clk>;
319 clock-names = "ddrck", "mpddr";
320 };
321
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322 dma0: dma-controller@f0014000 {
323 compatible = "atmel,sama5d4-dma";
324 reg = <0xf0014000 0x200>;
325 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>;
326 #dma-cells = <1>;
327 clocks = <&dma0_clk>;
328 clock-names = "dma_clk";
329 };
330
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331 pmc: pmc@f0018000 {
332 compatible = "atmel,sama5d3-pmc";
333 reg = <0xf0018000 0x120>;
334 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
335 interrupt-controller;
336 #address-cells = <1>;
337 #size-cells = <0>;
338 #interrupt-cells = <1>;
339
340 main_rc_osc: main_rc_osc {
341 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
342 #clock-cells = <0>;
343 interrupt-parent = <&pmc>;
344 interrupts = <AT91_PMC_MOSCRCS>;
345 clock-frequency = <12000000>;
346 clock-accuracy = <100000000>;
347 };
348
349 main_osc: main_osc {
350 compatible = "atmel,at91rm9200-clk-main-osc";
351 #clock-cells = <0>;
352 interrupt-parent = <&pmc>;
353 interrupts = <AT91_PMC_MOSCS>;
354 clocks = <&main_xtal>;
355 };
356
357 main: mainck {
358 compatible = "atmel,at91sam9x5-clk-main";
359 #clock-cells = <0>;
360 interrupt-parent = <&pmc>;
361 interrupts = <AT91_PMC_MOSCSELS>;
362 clocks = <&main_rc_osc &main_osc>;
363 };
364
365 plla: pllack {
366 compatible = "atmel,sama5d3-clk-pll";
367 #clock-cells = <0>;
368 interrupt-parent = <&pmc>;
369 interrupts = <AT91_PMC_LOCKA>;
370 clocks = <&main>;
371 reg = <0>;
372 atmel,clk-input-range = <12000000 12000000>;
373 #atmel,pll-clk-output-range-cells = <4>;
374 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
375 };
376
377 plladiv: plladivck {
378 compatible = "atmel,at91sam9x5-clk-plldiv";
379 #clock-cells = <0>;
380 clocks = <&plla>;
381 };
382
383 utmi: utmick {
384 compatible = "atmel,at91sam9x5-clk-utmi";
385 #clock-cells = <0>;
386 interrupt-parent = <&pmc>;
387 interrupts = <AT91_PMC_LOCKU>;
388 clocks = <&main>;
389 };
390
391 mck: masterck {
392 compatible = "atmel,at91sam9x5-clk-master";
393 #clock-cells = <0>;
394 interrupt-parent = <&pmc>;
395 interrupts = <AT91_PMC_MCKRDY>;
396 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
397 atmel,clk-output-range = <125000000 177000000>;
398 atmel,clk-divisors = <1 2 4 3>;
399 };
400
401 h32ck: h32mxck {
402 #clock-cells = <0>;
403 compatible = "atmel,sama5d4-clk-h32mx";
404 clocks = <&mck>;
405 };
406
407 usb: usbck {
408 compatible = "atmel,at91sam9x5-clk-usb";
409 #clock-cells = <0>;
410 clocks = <&plladiv>, <&utmi>;
411 };
412
413 prog: progck {
414 compatible = "atmel,at91sam9x5-clk-programmable";
415 #address-cells = <1>;
416 #size-cells = <0>;
417 interrupt-parent = <&pmc>;
418 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
419
420 prog0: prog0 {
421 #clock-cells = <0>;
422 reg = <0>;
423 interrupts = <AT91_PMC_PCKRDY(0)>;
424 };
425
426 prog1: prog1 {
427 #clock-cells = <0>;
428 reg = <1>;
429 interrupts = <AT91_PMC_PCKRDY(1)>;
430 };
431
432 prog2: prog2 {
433 #clock-cells = <0>;
434 reg = <2>;
435 interrupts = <AT91_PMC_PCKRDY(2)>;
436 };
437 };
438
439 smd: smdclk {
440 compatible = "atmel,at91sam9x5-clk-smd";
441 #clock-cells = <0>;
442 clocks = <&plladiv>, <&utmi>;
443 };
444
445 systemck {
446 compatible = "atmel,at91rm9200-clk-system";
447 #address-cells = <1>;
448 #size-cells = <0>;
449
450 ddrck: ddrck {
451 #clock-cells = <0>;
452 reg = <2>;
453 clocks = <&mck>;
454 };
455
456 lcdck: lcdck {
457 #clock-cells = <0>;
458 reg = <4>;
459 clocks = <&smd>;
460 };
461
462 smdck: smdck {
463 #clock-cells = <0>;
464 reg = <4>;
465 clocks = <&smd>;
466 };
467
468 uhpck: uhpck {
469 #clock-cells = <0>;
470 reg = <6>;
471 clocks = <&usb>;
472 };
473
474 udpck: udpck {
475 #clock-cells = <0>;
476 reg = <7>;
477 clocks = <&usb>;
478 };
479
480 pck0: pck0 {
481 #clock-cells = <0>;
482 reg = <8>;
483 clocks = <&prog0>;
484 };
485
486 pck1: pck1 {
487 #clock-cells = <0>;
488 reg = <9>;
489 clocks = <&prog1>;
490 };
491
492 pck2: pck2 {
493 #clock-cells = <0>;
494 reg = <10>;
495 clocks = <&prog2>;
496 };
497 };
498
499 periph32ck {
500 compatible = "atmel,at91sam9x5-clk-peripheral";
501 #address-cells = <1>;
502 #size-cells = <0>;
503 clocks = <&h32ck>;
504
505 pioD_clk: pioD_clk {
506 #clock-cells = <0>;
507 reg = <5>;
508 };
509
510 usart0_clk: usart0_clk {
511 #clock-cells = <0>;
512 reg = <6>;
513 };
514
515 usart1_clk: usart1_clk {
516 #clock-cells = <0>;
517 reg = <7>;
518 };
519
520 icm_clk: icm_clk {
521 #clock-cells = <0>;
522 reg = <9>;
523 };
524
525 aes_clk: aes_clk {
526 #clock-cells = <0>;
527 reg = <12>;
528 };
529
530 tdes_clk: tdes_clk {
531 #clock-cells = <0>;
532 reg = <14>;
533 };
534
535 sha_clk: sha_clk {
536 #clock-cells = <0>;
537 reg = <15>;
538 };
539
540 matrix1_clk: matrix1_clk {
541 #clock-cells = <0>;
542 reg = <17>;
543 };
544
545 hsmc_clk: hsmc_clk {
546 #clock-cells = <0>;
547 reg = <22>;
548 };
549
550 pioA_clk: pioA_clk {
551 #clock-cells = <0>;
552 reg = <23>;
553 };
554
555 pioB_clk: pioB_clk {
556 #clock-cells = <0>;
557 reg = <24>;
558 };
559
560 pioC_clk: pioC_clk {
561 #clock-cells = <0>;
562 reg = <25>;
563 };
564
565 pioE_clk: pioE_clk {
566 #clock-cells = <0>;
567 reg = <26>;
568 };
569
570 uart0_clk: uart0_clk {
571 #clock-cells = <0>;
572 reg = <27>;
573 };
574
575 uart1_clk: uart1_clk {
576 #clock-cells = <0>;
577 reg = <28>;
578 };
579
580 usart2_clk: usart2_clk {
581 #clock-cells = <0>;
582 reg = <29>;
583 };
584
585 usart3_clk: usart3_clk {
586 #clock-cells = <0>;
587 reg = <30>;
588 };
589
590 usart4_clk: usart4_clk {
591 #clock-cells = <0>;
592 reg = <31>;
593 };
594
595 twi0_clk: twi0_clk {
596 reg = <32>;
597 #clock-cells = <0>;
598 };
599
600 twi1_clk: twi1_clk {
601 #clock-cells = <0>;
602 reg = <33>;
603 };
604
605 twi2_clk: twi2_clk {
606 #clock-cells = <0>;
607 reg = <34>;
608 };
609
610 mci0_clk: mci0_clk {
611 #clock-cells = <0>;
612 reg = <35>;
613 };
614
615 mci1_clk: mci1_clk {
616 #clock-cells = <0>;
617 reg = <36>;
618 };
619
620 spi0_clk: spi0_clk {
621 #clock-cells = <0>;
622 reg = <37>;
623 };
624
625 spi1_clk: spi1_clk {
626 #clock-cells = <0>;
627 reg = <38>;
628 };
629
630 spi2_clk: spi2_clk {
631 #clock-cells = <0>;
632 reg = <39>;
633 };
634
635 tcb0_clk: tcb0_clk {
636 #clock-cells = <0>;
637 reg = <40>;
638 };
639
640 tcb1_clk: tcb1_clk {
641 #clock-cells = <0>;
642 reg = <41>;
643 };
644
645 tcb2_clk: tcb2_clk {
646 #clock-cells = <0>;
647 reg = <42>;
648 };
649
650 pwm_clk: pwm_clk {
651 #clock-cells = <0>;
652 reg = <43>;
653 };
654
655 adc_clk: adc_clk {
656 #clock-cells = <0>;
657 reg = <44>;
658 };
659
660 dbgu_clk: dbgu_clk {
661 #clock-cells = <0>;
662 reg = <45>;
663 };
664
665 uhphs_clk: uhphs_clk {
666 #clock-cells = <0>;
667 reg = <46>;
668 };
669
670 udphs_clk: udphs_clk {
671 #clock-cells = <0>;
672 reg = <47>;
673 };
674
675 ssc0_clk: ssc0_clk {
676 #clock-cells = <0>;
677 reg = <48>;
678 };
679
680 ssc1_clk: ssc1_clk {
681 #clock-cells = <0>;
682 reg = <49>;
683 };
684
685 trng_clk: trng_clk {
686 #clock-cells = <0>;
687 reg = <53>;
688 };
689
690 macb0_clk: macb0_clk {
691 #clock-cells = <0>;
692 reg = <54>;
693 };
694
695 macb1_clk: macb1_clk {
696 #clock-cells = <0>;
697 reg = <55>;
698 };
699
700 fuse_clk: fuse_clk {
701 #clock-cells = <0>;
702 reg = <57>;
703 };
704
705 securam_clk: securam_clk {
706 #clock-cells = <0>;
707 reg = <59>;
708 };
709
710 smd_clk: smd_clk {
711 #clock-cells = <0>;
712 reg = <61>;
713 };
714
715 twi3_clk: twi3_clk {
716 #clock-cells = <0>;
717 reg = <62>;
718 };
719
720 catb_clk: catb_clk {
721 #clock-cells = <0>;
722 reg = <63>;
723 };
724 };
725
726 periph64ck {
727 compatible = "atmel,at91sam9x5-clk-peripheral";
728 #address-cells = <1>;
729 #size-cells = <0>;
730 clocks = <&mck>;
731
732 dma0_clk: dma0_clk {
733 #clock-cells = <0>;
734 reg = <8>;
735 };
736
737 cpkcc_clk: cpkcc_clk {
738 #clock-cells = <0>;
739 reg = <10>;
740 };
741
742 aesb_clk: aesb_clk {
743 #clock-cells = <0>;
744 reg = <13>;
745 };
746
747 mpddr_clk: mpddr_clk {
748 #clock-cells = <0>;
749 reg = <16>;
750 };
751
752 matrix0_clk: matrix0_clk {
753 #clock-cells = <0>;
754 reg = <18>;
755 };
756
757 vdec_clk: vdec_clk {
758 #clock-cells = <0>;
759 reg = <19>;
760 };
761
762 dma1_clk: dma1_clk {
763 #clock-cells = <0>;
764 reg = <50>;
765 };
766
767 lcd_clk: lcd_clk {
768 #clock-cells = <0>;
769 reg = <51>;
770 };
771
772 isi_clk: isi_clk {
773 #clock-cells = <0>;
774 reg = <52>;
775 };
776 };
777 };
778
779 mmc0: mmc@f8000000 {
780 compatible = "atmel,hsmci";
781 reg = <0xf8000000 0x600>;
782 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
b3c7a497
LD
783 dmas = <&dma1
784 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
785 | AT91_XDMAC_DT_PERID(0))>;
786 dma-names = "rxtx";
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787 pinctrl-names = "default";
788 pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>;
789 status = "disabled";
790 #address-cells = <1>;
791 #size-cells = <0>;
792 clocks = <&mci0_clk>;
793 clock-names = "mci_clk";
794 };
795
796 spi0: spi@f8010000 {
797 #address-cells = <1>;
798 #size-cells = <0>;
799 compatible = "atmel,at91rm9200-spi";
800 reg = <0xf8010000 0x100>;
801 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>;
b3c7a497
LD
802 dmas = <&dma1
803 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
804 | AT91_XDMAC_DT_PERID(10))>,
805 <&dma1
806 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
807 | AT91_XDMAC_DT_PERID(11))>;
808 dma-names = "tx", "rx";
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NF
809 pinctrl-names = "default";
810 pinctrl-0 = <&pinctrl_spi0>;
811 clocks = <&spi0_clk>;
812 clock-names = "spi_clk";
813 status = "disabled";
814 };
815
816 i2c0: i2c@f8014000 {
817 compatible = "atmel,at91sam9x5-i2c";
818 reg = <0xf8014000 0x4000>;
819 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>;
b3c7a497
LD
820 dmas = <&dma1
821 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
822 | AT91_XDMAC_DT_PERID(2))>,
823 <&dma1
824 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
825 | AT91_XDMAC_DT_PERID(3))>;
826 dma-names = "tx", "rx";
7c661394
NF
827 pinctrl-names = "default";
828 pinctrl-0 = <&pinctrl_i2c0>;
829 #address-cells = <1>;
830 #size-cells = <0>;
831 clocks = <&twi0_clk>;
832 status = "disabled";
833 };
834
835 tcb0: timer@f801c000 {
836 compatible = "atmel,at91sam9x5-tcb";
837 reg = <0xf801c000 0x100>;
838 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>;
839 clocks = <&tcb0_clk>;
840 clock-names = "t0_clk";
841 };
842
843 macb0: ethernet@f8020000 {
844 compatible = "atmel,sama5d4-gem";
845 reg = <0xf8020000 0x100>;
846 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>;
847 pinctrl-names = "default";
848 pinctrl-0 = <&pinctrl_macb0_rmii>;
849 clocks = <&macb0_clk>, <&macb0_clk>;
850 clock-names = "hclk", "pclk";
851 status = "disabled";
852 };
853
854 i2c2: i2c@f8024000 {
855 compatible = "atmel,at91sam9x5-i2c";
856 reg = <0xf8024000 0x4000>;
84f017a7 857 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>;
b3c7a497
LD
858 dmas = <&dma1
859 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
860 | AT91_XDMAC_DT_PERID(6))>,
861 <&dma1
862 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
863 | AT91_XDMAC_DT_PERID(7))>;
864 dma-names = "tx", "rx";
7c661394
NF
865 pinctrl-names = "default";
866 pinctrl-0 = <&pinctrl_i2c2>;
867 #address-cells = <1>;
868 #size-cells = <0>;
869 clocks = <&twi2_clk>;
870 status = "disabled";
871 };
872
873 mmc1: mmc@fc000000 {
874 compatible = "atmel,hsmci";
875 reg = <0xfc000000 0x600>;
876 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
b3c7a497
LD
877 dmas = <&dma1
878 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
879 | AT91_XDMAC_DT_PERID(1))>;
880 dma-names = "rxtx";
7c661394
NF
881 pinctrl-names = "default";
882 pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
883 status = "disabled";
884 #address-cells = <1>;
885 #size-cells = <0>;
886 clocks = <&mci1_clk>;
887 clock-names = "mci_clk";
888 };
889
890 usart2: serial@fc008000 {
891 compatible = "atmel,at91sam9260-usart";
892 reg = <0xfc008000 0x100>;
893 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD
894 dmas = <&dma1
895 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
896 | AT91_XDMAC_DT_PERID(16))>,
897 <&dma1
898 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
899 | AT91_XDMAC_DT_PERID(17))>;
900 dma-names = "tx", "rx";
7c661394
NF
901 pinctrl-names = "default";
902 pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>;
903 clocks = <&usart2_clk>;
904 clock-names = "usart";
905 status = "disabled";
906 };
907
908 usart3: serial@fc00c000 {
909 compatible = "atmel,at91sam9260-usart";
910 reg = <0xfc00c000 0x100>;
911 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD
912 dmas = <&dma1
913 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
914 | AT91_XDMAC_DT_PERID(18))>,
915 <&dma1
916 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
917 | AT91_XDMAC_DT_PERID(19))>;
918 dma-names = "tx", "rx";
7c661394
NF
919 pinctrl-names = "default";
920 pinctrl-0 = <&pinctrl_usart3>;
921 clocks = <&usart3_clk>;
922 clock-names = "usart";
923 status = "disabled";
924 };
925
926 usart4: serial@fc010000 {
927 compatible = "atmel,at91sam9260-usart";
928 reg = <0xfc010000 0x100>;
929 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>;
b3c7a497
LD
930 dmas = <&dma1
931 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
932 | AT91_XDMAC_DT_PERID(20))>,
933 <&dma1
934 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
935 | AT91_XDMAC_DT_PERID(21))>;
936 dma-names = "tx", "rx";
7c661394
NF
937 pinctrl-names = "default";
938 pinctrl-0 = <&pinctrl_usart4>;
939 clocks = <&usart4_clk>;
940 clock-names = "usart";
941 status = "disabled";
942 };
943
944 tcb1: timer@fc020000 {
945 compatible = "atmel,at91sam9x5-tcb";
946 reg = <0xfc020000 0x100>;
947 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>;
948 clocks = <&tcb1_clk>;
949 clock-names = "t0_clk";
950 };
951
952 adc0: adc@fc034000 {
953 compatible = "atmel,at91sam9x5-adc";
954 reg = <0xfc034000 0x100>;
955 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>;
956 pinctrl-names = "default";
957 pinctrl-0 = <
958 /* external trigger is conflict with USBA_VBUS */
959 &pinctrl_adc0_ad0
960 &pinctrl_adc0_ad1
961 &pinctrl_adc0_ad2
962 &pinctrl_adc0_ad3
963 &pinctrl_adc0_ad4
964 >;
965 clocks = <&adc_clk>,
966 <&adc_op_clk>;
967 clock-names = "adc_clk", "adc_op_clk";
968 atmel,adc-channels-used = <0x01f>;
969 atmel,adc-startup-time = <40>;
970 atmel,adc-use-external;
971 atmel,adc-vref = <3000>;
972 atmel,adc-res = <8 10>;
973 atmel,adc-sample-hold-time = <11>;
974 atmel,adc-res-names = "lowres", "highres";
975 atmel,adc-ts-pressure-threshold = <10000>;
976 status = "disabled";
977
978 trigger@0 {
979 trigger-name = "external-rising";
980 trigger-value = <0x1>;
981 trigger-external;
982 };
983 trigger@1 {
984 trigger-name = "external-falling";
985 trigger-value = <0x2>;
986 trigger-external;
987 };
988 trigger@2 {
989 trigger-name = "external-any";
990 trigger-value = <0x3>;
991 trigger-external;
992 };
993 trigger@3 {
994 trigger-name = "continuous";
995 trigger-value = <0x6>;
996 };
997 };
998
999 rstc@fc068600 {
1000 compatible = "atmel,at91sam9g45-rstc";
1001 reg = <0xfc068600 0x10>;
1002 };
1003
1004 shdwc@fc068610 {
1005 compatible = "atmel,at91sam9x5-shdwc";
1006 reg = <0xfc068610 0x10>;
1007 };
1008
1009 pit: timer@fc068630 {
1010 compatible = "atmel,at91sam9260-pit";
0068b2e1 1011 reg = <0xfc068630 0x10>;
7c661394
NF
1012 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1013 clocks = <&h32ck>;
1014 };
1015
1016 watchdog@fc068640 {
1017 compatible = "atmel,at91sam9260-wdt";
1018 reg = <0xfc068640 0x10>;
1019 status = "disabled";
1020 };
1021
1022 sckc@fc068650 {
1023 compatible = "atmel,at91sam9x5-sckc";
1024 reg = <0xfc068650 0x4>;
1025
1026 slow_rc_osc: slow_rc_osc {
1027 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
1028 #clock-cells = <0>;
1029 clock-frequency = <32768>;
1030 clock-accuracy = <250000000>;
1031 atmel,startup-time-usec = <75>;
1032 };
1033
1034 slow_osc: slow_osc {
1035 compatible = "atmel,at91sam9x5-clk-slow-osc";
1036 #clock-cells = <0>;
1037 clocks = <&slow_xtal>;
1038 atmel,startup-time-usec = <1200000>;
1039 };
1040
1041 clk32k: slowck {
1042 compatible = "atmel,at91sam9x5-clk-slow";
1043 #clock-cells = <0>;
1044 clocks = <&slow_rc_osc &slow_osc>;
1045 };
1046 };
1047
1048 rtc@fc0686b0 {
1049 compatible = "atmel,at91rm9200-rtc";
1050 reg = <0xfc0686b0 0x30>;
1051 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
1052 };
1053
1054 dbgu: serial@fc069000 {
1055 compatible = "atmel,at91sam9260-usart";
1056 reg = <0xfc069000 0x200>;
1057 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
1058 pinctrl-names = "default";
1059 pinctrl-0 = <&pinctrl_dbgu>;
1060 clocks = <&dbgu_clk>;
1061 clock-names = "usart";
1062 status = "disabled";
1063 };
1064
1065
1066 pinctrl@fc06a000 {
1067 #address-cells = <1>;
1068 #size-cells = <1>;
1069 compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
1070 ranges = <0xfc06a000 0xfc06a000 0x4000>;
1071 /* WARNING: revisit as pin spec has changed */
1072 atmel,mux-mask = <
1073 /* A B C */
1074 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */
1075 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */
1076 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */
1077 0x00000000 0x00000000 0x00000000 /* pioD */
1078 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */
1079 >;
1080
1081 pioA: gpio@fc06a000 {
1082 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1083 reg = <0xfc06a000 0x100>;
1084 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>;
1085 #gpio-cells = <2>;
1086 gpio-controller;
1087 interrupt-controller;
1088 #interrupt-cells = <2>;
1089 clocks = <&pioA_clk>;
1090 };
1091
1092 pioB: gpio@fc06b000 {
1093 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1094 reg = <0xfc06b000 0x100>;
1095 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>;
1096 #gpio-cells = <2>;
1097 gpio-controller;
1098 interrupt-controller;
1099 #interrupt-cells = <2>;
1100 clocks = <&pioB_clk>;
1101 };
1102
1103 pioC: gpio@fc06c000 {
1104 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1105 reg = <0xfc06c000 0x100>;
1106 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>;
1107 #gpio-cells = <2>;
1108 gpio-controller;
1109 interrupt-controller;
1110 #interrupt-cells = <2>;
1111 clocks = <&pioC_clk>;
1112 };
1113
1114 pioE: gpio@fc06d000 {
1115 compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
1116 reg = <0xfc06d000 0x100>;
1117 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>;
1118 #gpio-cells = <2>;
1119 gpio-controller;
1120 interrupt-controller;
1121 #interrupt-cells = <2>;
1122 clocks = <&pioE_clk>;
1123 };
1124
1125 /* pinctrl pin settings */
1126 adc0 {
1127 pinctrl_adc0_adtrg: adc0_adtrg {
1128 atmel,pins =
1129 <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */
1130 };
1131 pinctrl_adc0_ad0: adc0_ad0 {
1132 atmel,pins =
1133 <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1134 };
1135 pinctrl_adc0_ad1: adc0_ad1 {
1136 atmel,pins =
1137 <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1138 };
1139 pinctrl_adc0_ad2: adc0_ad2 {
1140 atmel,pins =
1141 <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1142 };
1143 pinctrl_adc0_ad3: adc0_ad3 {
1144 atmel,pins =
1145 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1146 };
1147 pinctrl_adc0_ad4: adc0_ad4 {
1148 atmel,pins =
1149 <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1150 };
1151 };
1152
1153 dbgu {
1154 pinctrl_dbgu: dbgu-0 {
1155 atmel,pins =
1156 <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */
1157 <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */
1158 };
1159 };
1160
1161 i2c0 {
1162 pinctrl_i2c0: i2c0-0 {
1163 atmel,pins =
1164 <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE
1165 AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>;
1166 };
1167 };
1168
1169 i2c2 {
1170 pinctrl_i2c2: i2c2-0 {
1171 atmel,pins =
1172 <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */
1173 AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */
1174 };
1175 };
1176
1177 macb0 {
1178 pinctrl_macb0_rmii: macb0_rmii-0 {
1179 atmel,pins =
1180 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */
1181 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */
1182 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */
1183 AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */
1184 AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */
1185 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */
1186 AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */
1187 AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */
1188 AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */
1189 AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */
1190 >;
1191 };
1192 };
1193
1194 mmc0 {
1195 pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
1196 atmel,pins =
1197 <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */
1198 AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */
1199 AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */
1200 >;
1201 };
1202 pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
1203 atmel,pins =
1204 <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */
1205 AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */
1206 AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */
1207 >;
1208 };
1209 };
1210
1211 mmc1 {
1212 pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
1213 atmel,pins =
1214 <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */
1215 AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */
1216 AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */
1217 >;
1218 };
1219 pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
1220 atmel,pins =
1221 <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */
1222 AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */
1223 AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */
1224 >;
1225 };
1226 };
1227
1228 nand0 {
1229 pinctrl_nand: nand-0 {
1230 atmel,pins =
1231 <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */
1232 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */
1233
1234 AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */
1235 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */
1236
1237 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */
1238 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */
1239 AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */
1240 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */
1241 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */
1242 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */
1243 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */
1244 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */
1245 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */
1246 AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */
1247 };
1248 };
1249
1250 spi0 {
1251 pinctrl_spi0: spi0-0 {
1252 atmel,pins =
1253 <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */
1254 AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */
1255 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */
1256 >;
1257 };
1258 };
1259
1260 usart2 {
1261 pinctrl_usart2: usart2-0 {
1262 atmel,pins =
1263 <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */
1264 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */
1265 >;
1266 };
1267 pinctrl_usart2_rts: usart2_rts-0 {
1268 atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */
1269 };
1270 pinctrl_usart2_cts: usart2_cts-0 {
1271 atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */
1272 };
1273 };
1274
1275 usart3 {
1276 pinctrl_usart3: usart3-0 {
1277 atmel,pins =
1278 <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1279 AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1280 >;
1281 };
1282 };
1283
1284 usart4 {
1285 pinctrl_usart4: usart4-0 {
1286 atmel,pins =
1287 <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */
1288 AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */
1289 >;
1290 };
1291 pinctrl_usart4_rts: usart4_rts-0 {
1292 atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */
1293 };
1294 pinctrl_usart4_cts: usart4_cts-0 {
1295 atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */
1296 };
1297 };
1298 };
1299
1300 aic: interrupt-controller@fc06e000 {
1301 #interrupt-cells = <3>;
1302 compatible = "atmel,sama5d4-aic";
1303 interrupt-controller;
1304 reg = <0xfc06e000 0x200>;
1305 atmel,external-irqs = <56>;
1306 };
1307 };
1308 };
1309};
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