projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7c661394 NF |
1 | /* |
| 2 | * sama5d4.dtsi - Device Tree Include file for SAMA5D4 family SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2014 Atmel, | |
| 5 | * 2014 Nicolas Ferre <nicolas.ferre@atmel.com> | |
| 6 | * | |
| 7 | * This file is dual-licensed: you can use it either under the terms | |
| 8 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 9 | * licensing only applies to this file, and not this project as a | |
| 10 | * whole. | |
| 11 | * | |
| 1d2a0563 | 12 | * a) This file is free software; you can redistribute it and/or |
| 7c661394 NF |
13 | * modify it under the terms of the GNU General Public License as |
| 14 | * published by the Free Software Foundation; either version 2 of the | |
| 15 | * License, or (at your option) any later version. | |
| 16 | * | |
| 1d2a0563 | 17 | * This file is distributed in the hope that it will be useful, |
| 7c661394 NF |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 20 | * GNU General Public License for more details. | |
| 21 | * | |
| 22 | * Or, alternatively, | |
| 23 | * | |
| 24 | * b) Permission is hereby granted, free of charge, to any person | |
| 25 | * obtaining a copy of this software and associated documentation | |
| 26 | * files (the "Software"), to deal in the Software without | |
| 27 | * restriction, including without limitation the rights to use, | |
| 28 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 29 | * sell copies of the Software, and to permit persons to whom the | |
| 30 | * Software is furnished to do so, subject to the following | |
| 31 | * conditions: | |
| 32 | * | |
| 33 | * The above copyright notice and this permission notice shall be | |
| 34 | * included in all copies or substantial portions of the Software. | |
| 35 | * | |
| 36 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 37 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 38 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 39 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 40 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 41 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 42 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 43 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 44 | */ | |
| 45 | ||
| 46 | #include "skeleton.dtsi" | |
| 47 | #include <dt-bindings/clock/at91.h> | |
| b3c7a497 | 48 | #include <dt-bindings/dma/at91.h> |
| 7c661394 NF |
49 | #include <dt-bindings/pinctrl/at91.h> |
| 50 | #include <dt-bindings/interrupt-controller/irq.h> | |
| 51 | #include <dt-bindings/gpio/gpio.h> | |
| 52 | ||
| 53 | / { | |
| 54 | model = "Atmel SAMA5D4 family SoC"; | |
| 55 | compatible = "atmel,sama5d4"; | |
| 56 | interrupt-parent = <&aic>; | |
| 57 | ||
| 58 | aliases { | |
| 59 | serial0 = &usart3; | |
| 60 | serial1 = &usart4; | |
| 61 | serial2 = &usart2; | |
| 62 | gpio0 = &pioA; | |
| 63 | gpio1 = &pioB; | |
| 64 | gpio2 = &pioC; | |
| 1de77b7f | 65 | gpio3 = &pioD; |
| 7c661394 NF |
66 | gpio4 = &pioE; |
| 67 | tcb0 = &tcb0; | |
| 68 | tcb1 = &tcb1; | |
| a547f60a | 69 | i2c0 = &i2c0; |
| 7c661394 NF |
70 | i2c2 = &i2c2; |
| 71 | }; | |
| 72 | cpus { | |
| 73 | #address-cells = <1>; | |
| 74 | #size-cells = <0>; | |
| 75 | ||
| 76 | cpu@0 { | |
| 77 | device_type = "cpu"; | |
| 78 | compatible = "arm,cortex-a5"; | |
| 79 | reg = <0>; | |
| 80 | next-level-cache = <&L2>; | |
| 81 | }; | |
| 82 | }; | |
| 83 | ||
| 84 | memory { | |
| 85 | reg = <0x20000000 0x20000000>; | |
| 86 | }; | |
| 87 | ||
| 88 | clocks { | |
| 89 | slow_xtal: slow_xtal { | |
| 90 | compatible = "fixed-clock"; | |
| 91 | #clock-cells = <0>; | |
| 92 | clock-frequency = <0>; | |
| 93 | }; | |
| 94 | ||
| 95 | main_xtal: main_xtal { | |
| 96 | compatible = "fixed-clock"; | |
| 97 | #clock-cells = <0>; | |
| 98 | clock-frequency = <0>; | |
| 99 | }; | |
| 100 | ||
| 101 | adc_op_clk: adc_op_clk{ | |
| 102 | compatible = "fixed-clock"; | |
| 103 | #clock-cells = <0>; | |
| 104 | clock-frequency = <1000000>; | |
| 105 | }; | |
| 106 | }; | |
| 107 | ||
| f04660e4 AB |
108 | ns_sram: sram@00210000 { |
| 109 | compatible = "mmio-sram"; | |
| 110 | reg = <0x00210000 0x10000>; | |
| 111 | }; | |
| 112 | ||
| 7c661394 NF |
113 | ahb { |
| 114 | compatible = "simple-bus"; | |
| 115 | #address-cells = <1>; | |
| 116 | #size-cells = <1>; | |
| 117 | ranges; | |
| 118 | ||
| 119 | usb0: gadget@00400000 { | |
| 120 | #address-cells = <1>; | |
| 121 | #size-cells = <0>; | |
| 122 | compatible = "atmel,at91sam9rl-udc"; | |
| 123 | reg = <0x00400000 0x100000 | |
| 124 | 0xfc02c000 0x4000>; | |
| 125 | interrupts = <47 IRQ_TYPE_LEVEL_HIGH 2>; | |
| 126 | clocks = <&udphs_clk>, <&utmi>; | |
| 127 | clock-names = "pclk", "hclk"; | |
| 128 | status = "disabled"; | |
| 129 | ||
| 130 | ep0 { | |
| 131 | reg = <0>; | |
| 132 | atmel,fifo-size = <64>; | |
| 133 | atmel,nb-banks = <1>; | |
| 134 | }; | |
| 135 | ||
| 136 | ep1 { | |
| 137 | reg = <1>; | |
| 138 | atmel,fifo-size = <1024>; | |
| 139 | atmel,nb-banks = <3>; | |
| 140 | atmel,can-dma; | |
| 141 | atmel,can-isoc; | |
| 142 | }; | |
| 143 | ||
| 144 | ep2 { | |
| 145 | reg = <2>; | |
| 146 | atmel,fifo-size = <1024>; | |
| 147 | atmel,nb-banks = <3>; | |
| 148 | atmel,can-dma; | |
| 149 | atmel,can-isoc; | |
| 150 | }; | |
| 151 | ||
| 152 | ep3 { | |
| 153 | reg = <3>; | |
| 154 | atmel,fifo-size = <1024>; | |
| 155 | atmel,nb-banks = <2>; | |
| 156 | atmel,can-dma; | |
| 157 | atmel,can-isoc; | |
| 158 | }; | |
| 159 | ||
| 160 | ep4 { | |
| 161 | reg = <4>; | |
| 162 | atmel,fifo-size = <1024>; | |
| 163 | atmel,nb-banks = <2>; | |
| 164 | atmel,can-dma; | |
| 165 | atmel,can-isoc; | |
| 166 | }; | |
| 167 | ||
| 168 | ep5 { | |
| 169 | reg = <5>; | |
| 170 | atmel,fifo-size = <1024>; | |
| 171 | atmel,nb-banks = <2>; | |
| 172 | atmel,can-dma; | |
| 173 | atmel,can-isoc; | |
| 174 | }; | |
| 175 | ||
| 176 | ep6 { | |
| 177 | reg = <6>; | |
| 178 | atmel,fifo-size = <1024>; | |
| 179 | atmel,nb-banks = <2>; | |
| 180 | atmel,can-dma; | |
| 181 | atmel,can-isoc; | |
| 182 | }; | |
| 183 | ||
| 184 | ep7 { | |
| 185 | reg = <7>; | |
| 186 | atmel,fifo-size = <1024>; | |
| 187 | atmel,nb-banks = <2>; | |
| 188 | atmel,can-dma; | |
| 189 | atmel,can-isoc; | |
| 190 | }; | |
| 191 | ||
| 192 | ep8 { | |
| 193 | reg = <8>; | |
| 194 | atmel,fifo-size = <1024>; | |
| 195 | atmel,nb-banks = <2>; | |
| 196 | atmel,can-isoc; | |
| 197 | }; | |
| 198 | ||
| 199 | ep9 { | |
| 200 | reg = <9>; | |
| 201 | atmel,fifo-size = <1024>; | |
| 202 | atmel,nb-banks = <2>; | |
| 203 | atmel,can-isoc; | |
| 204 | }; | |
| 205 | ||
| 206 | ep10 { | |
| 207 | reg = <10>; | |
| 208 | atmel,fifo-size = <1024>; | |
| 209 | atmel,nb-banks = <2>; | |
| 210 | atmel,can-isoc; | |
| 211 | }; | |
| 212 | ||
| 213 | ep11 { | |
| 214 | reg = <11>; | |
| 215 | atmel,fifo-size = <1024>; | |
| 216 | atmel,nb-banks = <2>; | |
| 217 | atmel,can-isoc; | |
| 218 | }; | |
| 219 | ||
| 220 | ep12 { | |
| 221 | reg = <12>; | |
| 222 | atmel,fifo-size = <1024>; | |
| 223 | atmel,nb-banks = <2>; | |
| 224 | atmel,can-isoc; | |
| 225 | }; | |
| 226 | ||
| 227 | ep13 { | |
| 228 | reg = <13>; | |
| 229 | atmel,fifo-size = <1024>; | |
| 230 | atmel,nb-banks = <2>; | |
| 231 | atmel,can-isoc; | |
| 232 | }; | |
| 233 | ||
| 234 | ep14 { | |
| 235 | reg = <14>; | |
| 236 | atmel,fifo-size = <1024>; | |
| 237 | atmel,nb-banks = <2>; | |
| 238 | atmel,can-isoc; | |
| 239 | }; | |
| 240 | ||
| 241 | ep15 { | |
| 242 | reg = <15>; | |
| 243 | atmel,fifo-size = <1024>; | |
| 244 | atmel,nb-banks = <2>; | |
| 245 | atmel,can-isoc; | |
| 246 | }; | |
| 247 | }; | |
| 248 | ||
| 249 | usb1: ohci@00500000 { | |
| 250 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; | |
| 251 | reg = <0x00500000 0x100000>; | |
| 252 | interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; | |
| 253 | clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, | |
| 254 | <&uhpck>; | |
| 255 | clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck"; | |
| 256 | status = "disabled"; | |
| 257 | }; | |
| 258 | ||
| 259 | usb2: ehci@00600000 { | |
| 260 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; | |
| 261 | reg = <0x00600000 0x100000>; | |
| 262 | interrupts = <46 IRQ_TYPE_LEVEL_HIGH 2>; | |
| 263 | clocks = <&usb>, <&uhphs_clk>, <&uhpck>; | |
| 264 | clock-names = "usb_clk", "ehci_clk", "uhpck"; | |
| 265 | status = "disabled"; | |
| 266 | }; | |
| 267 | ||
| 268 | L2: cache-controller@00a00000 { | |
| 269 | compatible = "arm,pl310-cache"; | |
| 270 | reg = <0x00a00000 0x1000>; | |
| 271 | interrupts = <67 IRQ_TYPE_LEVEL_HIGH 4>; | |
| 272 | cache-unified; | |
| 273 | cache-level = <2>; | |
| 274 | }; | |
| 275 | ||
| 276 | nand0: nand@80000000 { | |
| fda077c0 | 277 | compatible = "atmel,sama5d4-nand", "atmel,at91rm9200-nand"; |
| 7c661394 NF |
278 | #address-cells = <1>; |
| 279 | #size-cells = <1>; | |
| 280 | ranges; | |
| 281 | reg = < 0x80000000 0x08000000 /* EBI CS3 */ | |
| 282 | 0xfc05c070 0x00000490 /* SMC PMECC regs */ | |
| 283 | 0xfc05c500 0x00000100 /* SMC PMECC Error Location regs */ | |
| 284 | >; | |
| 285 | interrupts = <22 IRQ_TYPE_LEVEL_HIGH 6>; | |
| 286 | atmel,nand-addr-offset = <21>; | |
| 287 | atmel,nand-cmd-offset = <22>; | |
| 288 | atmel,nand-has-dma; | |
| 289 | pinctrl-names = "default"; | |
| 290 | pinctrl-0 = <&pinctrl_nand>; | |
| 291 | status = "disabled"; | |
| 292 | ||
| 293 | nfc@90000000 { | |
| 294 | compatible = "atmel,sama5d3-nfc"; | |
| 295 | #address-cells = <1>; | |
| 296 | #size-cells = <1>; | |
| 297 | reg = < | |
| 298 | 0x90000000 0x10000000 /* NFC Command Registers */ | |
| 299 | 0xfc05c000 0x00000070 /* NFC HSMC regs */ | |
| 300 | 0x00100000 0x00100000 /* NFC SRAM banks */ | |
| 301 | >; | |
| 302 | clocks = <&hsmc_clk>; | |
| 303 | atmel,write-by-sram; | |
| 304 | }; | |
| 305 | }; | |
| 306 | ||
| 307 | apb { | |
| 308 | compatible = "simple-bus"; | |
| 309 | #address-cells = <1>; | |
| 310 | #size-cells = <1>; | |
| 311 | ranges; | |
| 312 | ||
| b3c7a497 LD |
313 | dma1: dma-controller@f0004000 { |
| 314 | compatible = "atmel,sama5d4-dma"; | |
| 315 | reg = <0xf0004000 0x200>; | |
| 316 | interrupts = <50 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 317 | #dma-cells = <1>; | |
| 318 | clocks = <&dma1_clk>; | |
| 319 | clock-names = "dma_clk"; | |
| 320 | }; | |
| 321 | ||
| 7c661394 NF |
322 | ramc0: ramc@f0010000 { |
| 323 | compatible = "atmel,sama5d3-ddramc"; | |
| 324 | reg = <0xf0010000 0x200>; | |
| 325 | clocks = <&ddrck>, <&mpddr_clk>; | |
| 326 | clock-names = "ddrck", "mpddr"; | |
| 327 | }; | |
| 328 | ||
| b3c7a497 LD |
329 | dma0: dma-controller@f0014000 { |
| 330 | compatible = "atmel,sama5d4-dma"; | |
| 331 | reg = <0xf0014000 0x200>; | |
| 332 | interrupts = <8 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 333 | #dma-cells = <1>; | |
| 334 | clocks = <&dma0_clk>; | |
| 335 | clock-names = "dma_clk"; | |
| 336 | }; | |
| 337 | ||
| 7c661394 NF |
338 | pmc: pmc@f0018000 { |
| 339 | compatible = "atmel,sama5d3-pmc"; | |
| 340 | reg = <0xf0018000 0x120>; | |
| 341 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 342 | interrupt-controller; | |
| 343 | #address-cells = <1>; | |
| 344 | #size-cells = <0>; | |
| 345 | #interrupt-cells = <1>; | |
| 346 | ||
| 347 | main_rc_osc: main_rc_osc { | |
| 348 | compatible = "atmel,at91sam9x5-clk-main-rc-osc"; | |
| 349 | #clock-cells = <0>; | |
| 350 | interrupt-parent = <&pmc>; | |
| 351 | interrupts = <AT91_PMC_MOSCRCS>; | |
| 352 | clock-frequency = <12000000>; | |
| 353 | clock-accuracy = <100000000>; | |
| 354 | }; | |
| 355 | ||
| 356 | main_osc: main_osc { | |
| 357 | compatible = "atmel,at91rm9200-clk-main-osc"; | |
| 358 | #clock-cells = <0>; | |
| 359 | interrupt-parent = <&pmc>; | |
| 360 | interrupts = <AT91_PMC_MOSCS>; | |
| 361 | clocks = <&main_xtal>; | |
| 362 | }; | |
| 363 | ||
| 364 | main: mainck { | |
| 365 | compatible = "atmel,at91sam9x5-clk-main"; | |
| 366 | #clock-cells = <0>; | |
| 367 | interrupt-parent = <&pmc>; | |
| 368 | interrupts = <AT91_PMC_MOSCSELS>; | |
| 369 | clocks = <&main_rc_osc &main_osc>; | |
| 370 | }; | |
| 371 | ||
| 372 | plla: pllack { | |
| 373 | compatible = "atmel,sama5d3-clk-pll"; | |
| 374 | #clock-cells = <0>; | |
| 375 | interrupt-parent = <&pmc>; | |
| 376 | interrupts = <AT91_PMC_LOCKA>; | |
| 377 | clocks = <&main>; | |
| 378 | reg = <0>; | |
| 379 | atmel,clk-input-range = <12000000 12000000>; | |
| 380 | #atmel,pll-clk-output-range-cells = <4>; | |
| 381 | atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; | |
| 382 | }; | |
| 383 | ||
| 384 | plladiv: plladivck { | |
| 385 | compatible = "atmel,at91sam9x5-clk-plldiv"; | |
| 386 | #clock-cells = <0>; | |
| 387 | clocks = <&plla>; | |
| 388 | }; | |
| 389 | ||
| 390 | utmi: utmick { | |
| 391 | compatible = "atmel,at91sam9x5-clk-utmi"; | |
| 392 | #clock-cells = <0>; | |
| 393 | interrupt-parent = <&pmc>; | |
| 394 | interrupts = <AT91_PMC_LOCKU>; | |
| 395 | clocks = <&main>; | |
| 396 | }; | |
| 397 | ||
| 398 | mck: masterck { | |
| 399 | compatible = "atmel,at91sam9x5-clk-master"; | |
| 400 | #clock-cells = <0>; | |
| 401 | interrupt-parent = <&pmc>; | |
| 402 | interrupts = <AT91_PMC_MCKRDY>; | |
| 403 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>; | |
| 404 | atmel,clk-output-range = <125000000 177000000>; | |
| 405 | atmel,clk-divisors = <1 2 4 3>; | |
| 406 | }; | |
| 407 | ||
| 408 | h32ck: h32mxck { | |
| 409 | #clock-cells = <0>; | |
| 410 | compatible = "atmel,sama5d4-clk-h32mx"; | |
| 411 | clocks = <&mck>; | |
| 412 | }; | |
| 413 | ||
| 414 | usb: usbck { | |
| 415 | compatible = "atmel,at91sam9x5-clk-usb"; | |
| 416 | #clock-cells = <0>; | |
| 417 | clocks = <&plladiv>, <&utmi>; | |
| 418 | }; | |
| 419 | ||
| 420 | prog: progck { | |
| 421 | compatible = "atmel,at91sam9x5-clk-programmable"; | |
| 422 | #address-cells = <1>; | |
| 423 | #size-cells = <0>; | |
| 424 | interrupt-parent = <&pmc>; | |
| 425 | clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>; | |
| 426 | ||
| 427 | prog0: prog0 { | |
| 428 | #clock-cells = <0>; | |
| 429 | reg = <0>; | |
| 430 | interrupts = <AT91_PMC_PCKRDY(0)>; | |
| 431 | }; | |
| 432 | ||
| 433 | prog1: prog1 { | |
| 434 | #clock-cells = <0>; | |
| 435 | reg = <1>; | |
| 436 | interrupts = <AT91_PMC_PCKRDY(1)>; | |
| 437 | }; | |
| 438 | ||
| 439 | prog2: prog2 { | |
| 440 | #clock-cells = <0>; | |
| 441 | reg = <2>; | |
| 442 | interrupts = <AT91_PMC_PCKRDY(2)>; | |
| 443 | }; | |
| 444 | }; | |
| 445 | ||
| 446 | smd: smdclk { | |
| 447 | compatible = "atmel,at91sam9x5-clk-smd"; | |
| 448 | #clock-cells = <0>; | |
| 449 | clocks = <&plladiv>, <&utmi>; | |
| 450 | }; | |
| 451 | ||
| 452 | systemck { | |
| 453 | compatible = "atmel,at91rm9200-clk-system"; | |
| 454 | #address-cells = <1>; | |
| 455 | #size-cells = <0>; | |
| 456 | ||
| 457 | ddrck: ddrck { | |
| 458 | #clock-cells = <0>; | |
| 459 | reg = <2>; | |
| 460 | clocks = <&mck>; | |
| 461 | }; | |
| 462 | ||
| 463 | lcdck: lcdck { | |
| 464 | #clock-cells = <0>; | |
| 465 | reg = <4>; | |
| 466 | clocks = <&smd>; | |
| 467 | }; | |
| 468 | ||
| 469 | smdck: smdck { | |
| 470 | #clock-cells = <0>; | |
| 471 | reg = <4>; | |
| 472 | clocks = <&smd>; | |
| 473 | }; | |
| 474 | ||
| 475 | uhpck: uhpck { | |
| 476 | #clock-cells = <0>; | |
| 477 | reg = <6>; | |
| 478 | clocks = <&usb>; | |
| 479 | }; | |
| 480 | ||
| 481 | udpck: udpck { | |
| 482 | #clock-cells = <0>; | |
| 483 | reg = <7>; | |
| 484 | clocks = <&usb>; | |
| 485 | }; | |
| 486 | ||
| 487 | pck0: pck0 { | |
| 488 | #clock-cells = <0>; | |
| 489 | reg = <8>; | |
| 490 | clocks = <&prog0>; | |
| 491 | }; | |
| 492 | ||
| 493 | pck1: pck1 { | |
| 494 | #clock-cells = <0>; | |
| 495 | reg = <9>; | |
| 496 | clocks = <&prog1>; | |
| 497 | }; | |
| 498 | ||
| 499 | pck2: pck2 { | |
| 500 | #clock-cells = <0>; | |
| 501 | reg = <10>; | |
| 502 | clocks = <&prog2>; | |
| 503 | }; | |
| 504 | }; | |
| 505 | ||
| 506 | periph32ck { | |
| 507 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
| 508 | #address-cells = <1>; | |
| 509 | #size-cells = <0>; | |
| 510 | clocks = <&h32ck>; | |
| 511 | ||
| 512 | pioD_clk: pioD_clk { | |
| 513 | #clock-cells = <0>; | |
| 514 | reg = <5>; | |
| 515 | }; | |
| 516 | ||
| 517 | usart0_clk: usart0_clk { | |
| 518 | #clock-cells = <0>; | |
| 519 | reg = <6>; | |
| 520 | }; | |
| 521 | ||
| 522 | usart1_clk: usart1_clk { | |
| 523 | #clock-cells = <0>; | |
| 524 | reg = <7>; | |
| 525 | }; | |
| 526 | ||
| 527 | icm_clk: icm_clk { | |
| 528 | #clock-cells = <0>; | |
| 529 | reg = <9>; | |
| 530 | }; | |
| 531 | ||
| 532 | aes_clk: aes_clk { | |
| 533 | #clock-cells = <0>; | |
| 534 | reg = <12>; | |
| 535 | }; | |
| 536 | ||
| 537 | tdes_clk: tdes_clk { | |
| 538 | #clock-cells = <0>; | |
| 539 | reg = <14>; | |
| 540 | }; | |
| 541 | ||
| 542 | sha_clk: sha_clk { | |
| 543 | #clock-cells = <0>; | |
| 544 | reg = <15>; | |
| 545 | }; | |
| 546 | ||
| 547 | matrix1_clk: matrix1_clk { | |
| 548 | #clock-cells = <0>; | |
| 549 | reg = <17>; | |
| 550 | }; | |
| 551 | ||
| 552 | hsmc_clk: hsmc_clk { | |
| 553 | #clock-cells = <0>; | |
| 554 | reg = <22>; | |
| 555 | }; | |
| 556 | ||
| 557 | pioA_clk: pioA_clk { | |
| 558 | #clock-cells = <0>; | |
| 559 | reg = <23>; | |
| 560 | }; | |
| 561 | ||
| 562 | pioB_clk: pioB_clk { | |
| 563 | #clock-cells = <0>; | |
| 564 | reg = <24>; | |
| 565 | }; | |
| 566 | ||
| 567 | pioC_clk: pioC_clk { | |
| 568 | #clock-cells = <0>; | |
| 569 | reg = <25>; | |
| 570 | }; | |
| 571 | ||
| 572 | pioE_clk: pioE_clk { | |
| 573 | #clock-cells = <0>; | |
| 574 | reg = <26>; | |
| 575 | }; | |
| 576 | ||
| 577 | uart0_clk: uart0_clk { | |
| 578 | #clock-cells = <0>; | |
| 579 | reg = <27>; | |
| 580 | }; | |
| 581 | ||
| 582 | uart1_clk: uart1_clk { | |
| 583 | #clock-cells = <0>; | |
| 584 | reg = <28>; | |
| 585 | }; | |
| 586 | ||
| 587 | usart2_clk: usart2_clk { | |
| 588 | #clock-cells = <0>; | |
| 589 | reg = <29>; | |
| 590 | }; | |
| 591 | ||
| 592 | usart3_clk: usart3_clk { | |
| 593 | #clock-cells = <0>; | |
| 594 | reg = <30>; | |
| 595 | }; | |
| 596 | ||
| 597 | usart4_clk: usart4_clk { | |
| 598 | #clock-cells = <0>; | |
| 599 | reg = <31>; | |
| 600 | }; | |
| 601 | ||
| 602 | twi0_clk: twi0_clk { | |
| 603 | reg = <32>; | |
| 604 | #clock-cells = <0>; | |
| 605 | }; | |
| 606 | ||
| 607 | twi1_clk: twi1_clk { | |
| 608 | #clock-cells = <0>; | |
| 609 | reg = <33>; | |
| 610 | }; | |
| 611 | ||
| 612 | twi2_clk: twi2_clk { | |
| 613 | #clock-cells = <0>; | |
| 614 | reg = <34>; | |
| 615 | }; | |
| 616 | ||
| 617 | mci0_clk: mci0_clk { | |
| 618 | #clock-cells = <0>; | |
| 619 | reg = <35>; | |
| 620 | }; | |
| 621 | ||
| 622 | mci1_clk: mci1_clk { | |
| 623 | #clock-cells = <0>; | |
| 624 | reg = <36>; | |
| 625 | }; | |
| 626 | ||
| 627 | spi0_clk: spi0_clk { | |
| 628 | #clock-cells = <0>; | |
| 629 | reg = <37>; | |
| 630 | }; | |
| 631 | ||
| 632 | spi1_clk: spi1_clk { | |
| 633 | #clock-cells = <0>; | |
| 634 | reg = <38>; | |
| 635 | }; | |
| 636 | ||
| 637 | spi2_clk: spi2_clk { | |
| 638 | #clock-cells = <0>; | |
| 639 | reg = <39>; | |
| 640 | }; | |
| 641 | ||
| 642 | tcb0_clk: tcb0_clk { | |
| 643 | #clock-cells = <0>; | |
| 644 | reg = <40>; | |
| 645 | }; | |
| 646 | ||
| 647 | tcb1_clk: tcb1_clk { | |
| 648 | #clock-cells = <0>; | |
| 649 | reg = <41>; | |
| 650 | }; | |
| 651 | ||
| 652 | tcb2_clk: tcb2_clk { | |
| 653 | #clock-cells = <0>; | |
| 654 | reg = <42>; | |
| 655 | }; | |
| 656 | ||
| 657 | pwm_clk: pwm_clk { | |
| 658 | #clock-cells = <0>; | |
| 659 | reg = <43>; | |
| 660 | }; | |
| 661 | ||
| 662 | adc_clk: adc_clk { | |
| 663 | #clock-cells = <0>; | |
| 664 | reg = <44>; | |
| 665 | }; | |
| 666 | ||
| 667 | dbgu_clk: dbgu_clk { | |
| 668 | #clock-cells = <0>; | |
| 669 | reg = <45>; | |
| 670 | }; | |
| 671 | ||
| 672 | uhphs_clk: uhphs_clk { | |
| 673 | #clock-cells = <0>; | |
| 674 | reg = <46>; | |
| 675 | }; | |
| 676 | ||
| 677 | udphs_clk: udphs_clk { | |
| 678 | #clock-cells = <0>; | |
| 679 | reg = <47>; | |
| 680 | }; | |
| 681 | ||
| 682 | ssc0_clk: ssc0_clk { | |
| 683 | #clock-cells = <0>; | |
| 684 | reg = <48>; | |
| 685 | }; | |
| 686 | ||
| 687 | ssc1_clk: ssc1_clk { | |
| 688 | #clock-cells = <0>; | |
| 689 | reg = <49>; | |
| 690 | }; | |
| 691 | ||
| 692 | trng_clk: trng_clk { | |
| 693 | #clock-cells = <0>; | |
| 694 | reg = <53>; | |
| 695 | }; | |
| 696 | ||
| 697 | macb0_clk: macb0_clk { | |
| 698 | #clock-cells = <0>; | |
| 699 | reg = <54>; | |
| 700 | }; | |
| 701 | ||
| 702 | macb1_clk: macb1_clk { | |
| 703 | #clock-cells = <0>; | |
| 704 | reg = <55>; | |
| 705 | }; | |
| 706 | ||
| 707 | fuse_clk: fuse_clk { | |
| 708 | #clock-cells = <0>; | |
| 709 | reg = <57>; | |
| 710 | }; | |
| 711 | ||
| 712 | securam_clk: securam_clk { | |
| 713 | #clock-cells = <0>; | |
| 714 | reg = <59>; | |
| 715 | }; | |
| 716 | ||
| 717 | smd_clk: smd_clk { | |
| 718 | #clock-cells = <0>; | |
| 719 | reg = <61>; | |
| 720 | }; | |
| 721 | ||
| 722 | twi3_clk: twi3_clk { | |
| 723 | #clock-cells = <0>; | |
| 724 | reg = <62>; | |
| 725 | }; | |
| 726 | ||
| 727 | catb_clk: catb_clk { | |
| 728 | #clock-cells = <0>; | |
| 729 | reg = <63>; | |
| 730 | }; | |
| 731 | }; | |
| 732 | ||
| 733 | periph64ck { | |
| 734 | compatible = "atmel,at91sam9x5-clk-peripheral"; | |
| 735 | #address-cells = <1>; | |
| 736 | #size-cells = <0>; | |
| 737 | clocks = <&mck>; | |
| 738 | ||
| 739 | dma0_clk: dma0_clk { | |
| 740 | #clock-cells = <0>; | |
| 741 | reg = <8>; | |
| 742 | }; | |
| 743 | ||
| 744 | cpkcc_clk: cpkcc_clk { | |
| 745 | #clock-cells = <0>; | |
| 746 | reg = <10>; | |
| 747 | }; | |
| 748 | ||
| 749 | aesb_clk: aesb_clk { | |
| 750 | #clock-cells = <0>; | |
| 751 | reg = <13>; | |
| 752 | }; | |
| 753 | ||
| 754 | mpddr_clk: mpddr_clk { | |
| 755 | #clock-cells = <0>; | |
| 756 | reg = <16>; | |
| 757 | }; | |
| 758 | ||
| 759 | matrix0_clk: matrix0_clk { | |
| 760 | #clock-cells = <0>; | |
| 761 | reg = <18>; | |
| 762 | }; | |
| 763 | ||
| 764 | vdec_clk: vdec_clk { | |
| 765 | #clock-cells = <0>; | |
| 766 | reg = <19>; | |
| 767 | }; | |
| 768 | ||
| 769 | dma1_clk: dma1_clk { | |
| 770 | #clock-cells = <0>; | |
| 771 | reg = <50>; | |
| 772 | }; | |
| 773 | ||
| b6d7d3f1 | 774 | lcdc_clk: lcdc_clk { |
| 7c661394 NF |
775 | #clock-cells = <0>; |
| 776 | reg = <51>; | |
| 777 | }; | |
| 778 | ||
| 779 | isi_clk: isi_clk { | |
| 780 | #clock-cells = <0>; | |
| 781 | reg = <52>; | |
| 782 | }; | |
| 783 | }; | |
| 784 | }; | |
| 785 | ||
| 786 | mmc0: mmc@f8000000 { | |
| 787 | compatible = "atmel,hsmci"; | |
| 788 | reg = <0xf8000000 0x600>; | |
| 789 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; | |
| b3c7a497 LD |
790 | dmas = <&dma1 |
| 791 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 792 | | AT91_XDMAC_DT_PERID(0))>; | |
| 793 | dma-names = "rxtx"; | |
| 7c661394 NF |
794 | pinctrl-names = "default"; |
| 795 | pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3>; | |
| 796 | status = "disabled"; | |
| 797 | #address-cells = <1>; | |
| 798 | #size-cells = <0>; | |
| 799 | clocks = <&mci0_clk>; | |
| 800 | clock-names = "mci_clk"; | |
| 801 | }; | |
| 802 | ||
| 803 | spi0: spi@f8010000 { | |
| 804 | #address-cells = <1>; | |
| 805 | #size-cells = <0>; | |
| 806 | compatible = "atmel,at91rm9200-spi"; | |
| 807 | reg = <0xf8010000 0x100>; | |
| 808 | interrupts = <37 IRQ_TYPE_LEVEL_HIGH 3>; | |
| b3c7a497 LD |
809 | dmas = <&dma1 |
| 810 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 811 | | AT91_XDMAC_DT_PERID(10))>, | |
| 812 | <&dma1 | |
| 813 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 814 | | AT91_XDMAC_DT_PERID(11))>; | |
| 815 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
816 | pinctrl-names = "default"; |
| 817 | pinctrl-0 = <&pinctrl_spi0>; | |
| 818 | clocks = <&spi0_clk>; | |
| 819 | clock-names = "spi_clk"; | |
| 820 | status = "disabled"; | |
| 821 | }; | |
| 822 | ||
| 823 | i2c0: i2c@f8014000 { | |
| 824 | compatible = "atmel,at91sam9x5-i2c"; | |
| 825 | reg = <0xf8014000 0x4000>; | |
| 826 | interrupts = <32 IRQ_TYPE_LEVEL_HIGH 6>; | |
| b3c7a497 LD |
827 | dmas = <&dma1 |
| 828 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 829 | | AT91_XDMAC_DT_PERID(2))>, | |
| 830 | <&dma1 | |
| 831 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 832 | | AT91_XDMAC_DT_PERID(3))>; | |
| 833 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
834 | pinctrl-names = "default"; |
| 835 | pinctrl-0 = <&pinctrl_i2c0>; | |
| 836 | #address-cells = <1>; | |
| 837 | #size-cells = <0>; | |
| 838 | clocks = <&twi0_clk>; | |
| 839 | status = "disabled"; | |
| 840 | }; | |
| 841 | ||
| 842 | tcb0: timer@f801c000 { | |
| 843 | compatible = "atmel,at91sam9x5-tcb"; | |
| 844 | reg = <0xf801c000 0x100>; | |
| 845 | interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 846 | clocks = <&tcb0_clk>; | |
| 847 | clock-names = "t0_clk"; | |
| 848 | }; | |
| 849 | ||
| 850 | macb0: ethernet@f8020000 { | |
| 851 | compatible = "atmel,sama5d4-gem"; | |
| 852 | reg = <0xf8020000 0x100>; | |
| 853 | interrupts = <54 IRQ_TYPE_LEVEL_HIGH 3>; | |
| 854 | pinctrl-names = "default"; | |
| 855 | pinctrl-0 = <&pinctrl_macb0_rmii>; | |
| 856 | clocks = <&macb0_clk>, <&macb0_clk>; | |
| 857 | clock-names = "hclk", "pclk"; | |
| 858 | status = "disabled"; | |
| 859 | }; | |
| 860 | ||
| 861 | i2c2: i2c@f8024000 { | |
| 862 | compatible = "atmel,at91sam9x5-i2c"; | |
| 863 | reg = <0xf8024000 0x4000>; | |
| 84f017a7 | 864 | interrupts = <34 IRQ_TYPE_LEVEL_HIGH 6>; |
| b3c7a497 LD |
865 | dmas = <&dma1 |
| 866 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 867 | | AT91_XDMAC_DT_PERID(6))>, | |
| 868 | <&dma1 | |
| 869 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 870 | | AT91_XDMAC_DT_PERID(7))>; | |
| 871 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
872 | pinctrl-names = "default"; |
| 873 | pinctrl-0 = <&pinctrl_i2c2>; | |
| 874 | #address-cells = <1>; | |
| 875 | #size-cells = <0>; | |
| 876 | clocks = <&twi2_clk>; | |
| 877 | status = "disabled"; | |
| 878 | }; | |
| 879 | ||
| c3ef0b0c AB |
880 | sfr: sfr@f8028000 { |
| 881 | compatible = "atmel,sama5d4-sfr", "syscon"; | |
| 882 | reg = <0xf8028000 0x60>; | |
| 883 | }; | |
| 884 | ||
| 7c661394 NF |
885 | mmc1: mmc@fc000000 { |
| 886 | compatible = "atmel,hsmci"; | |
| 887 | reg = <0xfc000000 0x600>; | |
| 888 | interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>; | |
| b3c7a497 LD |
889 | dmas = <&dma1 |
| 890 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 891 | | AT91_XDMAC_DT_PERID(1))>; | |
| 892 | dma-names = "rxtx"; | |
| 7c661394 NF |
893 | pinctrl-names = "default"; |
| 894 | pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>; | |
| 895 | status = "disabled"; | |
| 896 | #address-cells = <1>; | |
| 897 | #size-cells = <0>; | |
| 898 | clocks = <&mci1_clk>; | |
| 899 | clock-names = "mci_clk"; | |
| 900 | }; | |
| 901 | ||
| 902 | usart2: serial@fc008000 { | |
| 903 | compatible = "atmel,at91sam9260-usart"; | |
| 904 | reg = <0xfc008000 0x100>; | |
| 905 | interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>; | |
| b3c7a497 LD |
906 | dmas = <&dma1 |
| 907 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 908 | | AT91_XDMAC_DT_PERID(16))>, | |
| 909 | <&dma1 | |
| 910 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 911 | | AT91_XDMAC_DT_PERID(17))>; | |
| 912 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
913 | pinctrl-names = "default"; |
| 914 | pinctrl-0 = <&pinctrl_usart2 &pinctrl_usart2_rts &pinctrl_usart2_cts>; | |
| 915 | clocks = <&usart2_clk>; | |
| 916 | clock-names = "usart"; | |
| 917 | status = "disabled"; | |
| 918 | }; | |
| 919 | ||
| 920 | usart3: serial@fc00c000 { | |
| 921 | compatible = "atmel,at91sam9260-usart"; | |
| 922 | reg = <0xfc00c000 0x100>; | |
| 923 | interrupts = <30 IRQ_TYPE_LEVEL_HIGH 5>; | |
| b3c7a497 LD |
924 | dmas = <&dma1 |
| 925 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 926 | | AT91_XDMAC_DT_PERID(18))>, | |
| 927 | <&dma1 | |
| 928 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 929 | | AT91_XDMAC_DT_PERID(19))>; | |
| 930 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
931 | pinctrl-names = "default"; |
| 932 | pinctrl-0 = <&pinctrl_usart3>; | |
| 933 | clocks = <&usart3_clk>; | |
| 934 | clock-names = "usart"; | |
| 935 | status = "disabled"; | |
| 936 | }; | |
| 937 | ||
| 938 | usart4: serial@fc010000 { | |
| 939 | compatible = "atmel,at91sam9260-usart"; | |
| 940 | reg = <0xfc010000 0x100>; | |
| 941 | interrupts = <31 IRQ_TYPE_LEVEL_HIGH 5>; | |
| b3c7a497 LD |
942 | dmas = <&dma1 |
| 943 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 944 | | AT91_XDMAC_DT_PERID(20))>, | |
| 945 | <&dma1 | |
| 946 | (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | |
| 947 | | AT91_XDMAC_DT_PERID(21))>; | |
| 948 | dma-names = "tx", "rx"; | |
| 7c661394 NF |
949 | pinctrl-names = "default"; |
| 950 | pinctrl-0 = <&pinctrl_usart4>; | |
| 951 | clocks = <&usart4_clk>; | |
| 952 | clock-names = "usart"; | |
| 953 | status = "disabled"; | |
| 954 | }; | |
| 955 | ||
| 956 | tcb1: timer@fc020000 { | |
| 957 | compatible = "atmel,at91sam9x5-tcb"; | |
| 958 | reg = <0xfc020000 0x100>; | |
| 959 | interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; | |
| 960 | clocks = <&tcb1_clk>; | |
| 961 | clock-names = "t0_clk"; | |
| 962 | }; | |
| 963 | ||
| 964 | adc0: adc@fc034000 { | |
| 965 | compatible = "atmel,at91sam9x5-adc"; | |
| 966 | reg = <0xfc034000 0x100>; | |
| 967 | interrupts = <44 IRQ_TYPE_LEVEL_HIGH 5>; | |
| 968 | pinctrl-names = "default"; | |
| 969 | pinctrl-0 = < | |
| 970 | /* external trigger is conflict with USBA_VBUS */ | |
| 971 | &pinctrl_adc0_ad0 | |
| 972 | &pinctrl_adc0_ad1 | |
| 973 | &pinctrl_adc0_ad2 | |
| 974 | &pinctrl_adc0_ad3 | |
| 975 | &pinctrl_adc0_ad4 | |
| 976 | >; | |
| 977 | clocks = <&adc_clk>, | |
| 978 | <&adc_op_clk>; | |
| 979 | clock-names = "adc_clk", "adc_op_clk"; | |
| 980 | atmel,adc-channels-used = <0x01f>; | |
| 981 | atmel,adc-startup-time = <40>; | |
| 982 | atmel,adc-use-external; | |
| 983 | atmel,adc-vref = <3000>; | |
| 984 | atmel,adc-res = <8 10>; | |
| 985 | atmel,adc-sample-hold-time = <11>; | |
| 986 | atmel,adc-res-names = "lowres", "highres"; | |
| 987 | atmel,adc-ts-pressure-threshold = <10000>; | |
| 988 | status = "disabled"; | |
| 989 | ||
| 990 | trigger@0 { | |
| 991 | trigger-name = "external-rising"; | |
| 992 | trigger-value = <0x1>; | |
| 993 | trigger-external; | |
| 994 | }; | |
| 995 | trigger@1 { | |
| 996 | trigger-name = "external-falling"; | |
| 997 | trigger-value = <0x2>; | |
| 998 | trigger-external; | |
| 999 | }; | |
| 1000 | trigger@2 { | |
| 1001 | trigger-name = "external-any"; | |
| 1002 | trigger-value = <0x3>; | |
| 1003 | trigger-external; | |
| 1004 | }; | |
| 1005 | trigger@3 { | |
| 1006 | trigger-name = "continuous"; | |
| 1007 | trigger-value = <0x6>; | |
| 1008 | }; | |
| 1009 | }; | |
| 1010 | ||
| 1011 | rstc@fc068600 { | |
| 1012 | compatible = "atmel,at91sam9g45-rstc"; | |
| 1013 | reg = <0xfc068600 0x10>; | |
| 1014 | }; | |
| 1015 | ||
| 1016 | shdwc@fc068610 { | |
| 1017 | compatible = "atmel,at91sam9x5-shdwc"; | |
| 1018 | reg = <0xfc068610 0x10>; | |
| 1019 | }; | |
| 1020 | ||
| 1021 | pit: timer@fc068630 { | |
| 1022 | compatible = "atmel,at91sam9260-pit"; | |
| 0068b2e1 | 1023 | reg = <0xfc068630 0x10>; |
| 7c661394 NF |
1024 | interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>; |
| 1025 | clocks = <&h32ck>; | |
| 1026 | }; | |
| 1027 | ||
| 1028 | watchdog@fc068640 { | |
| 1029 | compatible = "atmel,at91sam9260-wdt"; | |
| 1030 | reg = <0xfc068640 0x10>; | |
| 1031 | status = "disabled"; | |
| 1032 | }; | |
| 1033 | ||
| 1034 | sckc@fc068650 { | |
| 1035 | compatible = "atmel,at91sam9x5-sckc"; | |
| 1036 | reg = <0xfc068650 0x4>; | |
| 1037 | ||
| 1038 | slow_rc_osc: slow_rc_osc { | |
| 1039 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; | |
| 1040 | #clock-cells = <0>; | |
| 1041 | clock-frequency = <32768>; | |
| 1042 | clock-accuracy = <250000000>; | |
| 1043 | atmel,startup-time-usec = <75>; | |
| 1044 | }; | |
| 1045 | ||
| 1046 | slow_osc: slow_osc { | |
| 1047 | compatible = "atmel,at91sam9x5-clk-slow-osc"; | |
| 1048 | #clock-cells = <0>; | |
| 1049 | clocks = <&slow_xtal>; | |
| 1050 | atmel,startup-time-usec = <1200000>; | |
| 1051 | }; | |
| 1052 | ||
| 1053 | clk32k: slowck { | |
| 1054 | compatible = "atmel,at91sam9x5-clk-slow"; | |
| 1055 | #clock-cells = <0>; | |
| 1056 | clocks = <&slow_rc_osc &slow_osc>; | |
| 1057 | }; | |
| 1058 | }; | |
| 1059 | ||
| 1060 | rtc@fc0686b0 { | |
| 1061 | compatible = "atmel,at91rm9200-rtc"; | |
| 1062 | reg = <0xfc0686b0 0x30>; | |
| 1063 | interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 1064 | }; | |
| 1065 | ||
| 1066 | dbgu: serial@fc069000 { | |
| 1067 | compatible = "atmel,at91sam9260-usart"; | |
| 1068 | reg = <0xfc069000 0x200>; | |
| 1069 | interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>; | |
| 1070 | pinctrl-names = "default"; | |
| 1071 | pinctrl-0 = <&pinctrl_dbgu>; | |
| 1072 | clocks = <&dbgu_clk>; | |
| 1073 | clock-names = "usart"; | |
| 1074 | status = "disabled"; | |
| 1075 | }; | |
| 1076 | ||
| 1077 | ||
| 1078 | pinctrl@fc06a000 { | |
| 1079 | #address-cells = <1>; | |
| 1080 | #size-cells = <1>; | |
| 1081 | compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus"; | |
| 1082 | ranges = <0xfc06a000 0xfc06a000 0x4000>; | |
| 1083 | /* WARNING: revisit as pin spec has changed */ | |
| 1084 | atmel,mux-mask = < | |
| 1085 | /* A B C */ | |
| 1086 | 0xffffffff 0x3ffcfe7c 0x1c010101 /* pioA */ | |
| 1087 | 0x7fffffff 0xfffccc3a 0x3f00cc3a /* pioB */ | |
| 1088 | 0xffffffff 0x3ff83fff 0xff00ffff /* pioC */ | |
| 1089 | 0x00000000 0x00000000 0x00000000 /* pioD */ | |
| 1090 | 0xffffffff 0x7fffffff 0x76fff1bf /* pioE */ | |
| 1091 | >; | |
| 1092 | ||
| 1093 | pioA: gpio@fc06a000 { | |
| 1094 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1095 | reg = <0xfc06a000 0x100>; | |
| 1096 | interrupts = <23 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1097 | #gpio-cells = <2>; | |
| 1098 | gpio-controller; | |
| 1099 | interrupt-controller; | |
| 1100 | #interrupt-cells = <2>; | |
| 1101 | clocks = <&pioA_clk>; | |
| 1102 | }; | |
| 1103 | ||
| 1104 | pioB: gpio@fc06b000 { | |
| 1105 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1106 | reg = <0xfc06b000 0x100>; | |
| 1107 | interrupts = <24 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1108 | #gpio-cells = <2>; | |
| 1109 | gpio-controller; | |
| 1110 | interrupt-controller; | |
| 1111 | #interrupt-cells = <2>; | |
| 1112 | clocks = <&pioB_clk>; | |
| 1113 | }; | |
| 1114 | ||
| 1115 | pioC: gpio@fc06c000 { | |
| 1116 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1117 | reg = <0xfc06c000 0x100>; | |
| 1118 | interrupts = <25 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1119 | #gpio-cells = <2>; | |
| 1120 | gpio-controller; | |
| 1121 | interrupt-controller; | |
| 1122 | #interrupt-cells = <2>; | |
| 1123 | clocks = <&pioC_clk>; | |
| 1124 | }; | |
| 1125 | ||
| 1de77b7f LD |
1126 | pioD: gpio@fc068000 { |
| 1127 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1128 | reg = <0xfc068000 0x100>; | |
| 1129 | interrupts = <5 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1130 | #gpio-cells = <2>; | |
| 1131 | gpio-controller; | |
| 1132 | interrupt-controller; | |
| 1133 | #interrupt-cells = <2>; | |
| 1134 | clocks = <&pioD_clk>; | |
| 1135 | status = "disabled"; | |
| 1136 | }; | |
| 1137 | ||
| 7c661394 NF |
1138 | pioE: gpio@fc06d000 { |
| 1139 | compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio"; | |
| 1140 | reg = <0xfc06d000 0x100>; | |
| 1141 | interrupts = <26 IRQ_TYPE_LEVEL_HIGH 1>; | |
| 1142 | #gpio-cells = <2>; | |
| 1143 | gpio-controller; | |
| 1144 | interrupt-controller; | |
| 1145 | #interrupt-cells = <2>; | |
| 1146 | clocks = <&pioE_clk>; | |
| 1147 | }; | |
| 1148 | ||
| 1149 | /* pinctrl pin settings */ | |
| 1150 | adc0 { | |
| 1151 | pinctrl_adc0_adtrg: adc0_adtrg { | |
| 1152 | atmel,pins = | |
| 1153 | <AT91_PIOE 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* conflicts with USBA_VBUS */ | |
| 1154 | }; | |
| 1155 | pinctrl_adc0_ad0: adc0_ad0 { | |
| 1156 | atmel,pins = | |
| 1157 | <AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1158 | }; | |
| 1159 | pinctrl_adc0_ad1: adc0_ad1 { | |
| 1160 | atmel,pins = | |
| 1161 | <AT91_PIOC 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1162 | }; | |
| 1163 | pinctrl_adc0_ad2: adc0_ad2 { | |
| 1164 | atmel,pins = | |
| 1165 | <AT91_PIOC 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1166 | }; | |
| 1167 | pinctrl_adc0_ad3: adc0_ad3 { | |
| 1168 | atmel,pins = | |
| 1169 | <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1170 | }; | |
| 1171 | pinctrl_adc0_ad4: adc0_ad4 { | |
| 1172 | atmel,pins = | |
| 1173 | <AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1174 | }; | |
| 1175 | }; | |
| 1176 | ||
| 1177 | dbgu { | |
| 1178 | pinctrl_dbgu: dbgu-0 { | |
| 1179 | atmel,pins = | |
| 1180 | <AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE>, /* conflicts with D14 and TDI */ | |
| 1181 | <AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* conflicts with D15 and TDO */ | |
| 1182 | }; | |
| 1183 | }; | |
| 1184 | ||
| 1185 | i2c0 { | |
| 1186 | pinctrl_i2c0: i2c0-0 { | |
| 1187 | atmel,pins = | |
| 1188 | <AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE | |
| 1189 | AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; | |
| 1190 | }; | |
| 1191 | }; | |
| 1192 | ||
| 1193 | i2c2 { | |
| 1194 | pinctrl_i2c2: i2c2-0 { | |
| 1195 | atmel,pins = | |
| 1196 | <AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* TWD2, conflicts with RD0 and PWML1 */ | |
| 1197 | AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* TWCK2, conflicts with RF0 */ | |
| 1198 | }; | |
| 1199 | }; | |
| 1200 | ||
| 1201 | macb0 { | |
| 1202 | pinctrl_macb0_rmii: macb0_rmii-0 { | |
| 1203 | atmel,pins = | |
| 1204 | <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX0 */ | |
| 1205 | AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TX1 */ | |
| 1206 | AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX0 */ | |
| 1207 | AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RX1 */ | |
| 1208 | AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXDV */ | |
| 1209 | AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_RXER */ | |
| 1210 | AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXEN */ | |
| 1211 | AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_TXCK */ | |
| 1212 | AT91_PIOB 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDC */ | |
| 1213 | AT91_PIOB 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* G0_MDIO */ | |
| 1214 | >; | |
| 1215 | }; | |
| 1216 | }; | |
| 1217 | ||
| 1218 | mmc0 { | |
| 1219 | pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 { | |
| 1220 | atmel,pins = | |
| 1221 | <AT91_PIOC 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* MCI0_CK, conflict with PCK1(ISI_MCK) */ | |
| 1222 | AT91_PIOC 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_CDB, conflict with NAND_D0 */ | |
| 1223 | AT91_PIOC 6 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB0, conflict with NAND_D1 */ | |
| 1224 | >; | |
| 1225 | }; | |
| 1226 | pinctrl_mmc0_dat1_3: mmc0_dat1_3 { | |
| 1227 | atmel,pins = | |
| 1228 | <AT91_PIOC 7 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB1, conflict with NAND_D2 */ | |
| 1229 | AT91_PIOC 8 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB2, conflict with NAND_D3 */ | |
| 1230 | AT91_PIOC 9 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* MCI0_DB3, conflict with NAND_D4 */ | |
| 1231 | >; | |
| 1232 | }; | |
| 1233 | }; | |
| 1234 | ||
| 1235 | mmc1 { | |
| 1236 | pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 { | |
| 1237 | atmel,pins = | |
| 1238 | <AT91_PIOE 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* MCI1_CK */ | |
| 1239 | AT91_PIOE 19 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_CDA */ | |
| 1240 | AT91_PIOE 20 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA0 */ | |
| 1241 | >; | |
| 1242 | }; | |
| 1243 | pinctrl_mmc1_dat1_3: mmc1_dat1_3 { | |
| 1244 | atmel,pins = | |
| 1245 | <AT91_PIOE 21 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA1 */ | |
| 1246 | AT91_PIOE 22 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA2 */ | |
| 1247 | AT91_PIOE 23 AT91_PERIPH_C AT91_PINCTRL_PULL_UP /* MCI1_DA3 */ | |
| 1248 | >; | |
| 1249 | }; | |
| 1250 | }; | |
| 1251 | ||
| 1252 | nand0 { | |
| 1253 | pinctrl_nand: nand-0 { | |
| 1254 | atmel,pins = | |
| 1255 | <AT91_PIOC 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC13 periph A Read Enable */ | |
| 1256 | AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A Write Enable */ | |
| 1257 | ||
| 1258 | AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC17 ALE */ | |
| 1259 | AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC18 CLE */ | |
| 1260 | ||
| 1261 | AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC15 NCS3/Chip Enable */ | |
| 1262 | AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PC16 NANDRDY */ | |
| 1263 | AT91_PIOC 5 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC5 Data bit 0 */ | |
| 1264 | AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 Data bit 1 */ | |
| 1265 | AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 Data bit 2 */ | |
| 1266 | AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 Data bit 3 */ | |
| 1267 | AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 Data bit 4 */ | |
| 1268 | AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 Data bit 5 */ | |
| 1269 | AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A Data bit 6 */ | |
| 1270 | AT91_PIOC 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC12 periph A Data bit 7 */ | |
| 1271 | }; | |
| 1272 | }; | |
| 1273 | ||
| 1274 | spi0 { | |
| 1275 | pinctrl_spi0: spi0-0 { | |
| 1276 | atmel,pins = | |
| 1277 | <AT91_PIOC 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MISO */ | |
| 1278 | AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_MOSI */ | |
| 1279 | AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* SPI0_SPCK */ | |
| 1280 | >; | |
| 1281 | }; | |
| 1282 | }; | |
| 1283 | ||
| 1284 | usart2 { | |
| 1285 | pinctrl_usart2: usart2-0 { | |
| 1286 | atmel,pins = | |
| 1287 | <AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD - conflicts with G0_CRS, ISI_HSYNC */ | |
| 1288 | AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD - conflicts with G0_COL, PCK2 */ | |
| 1289 | >; | |
| 1290 | }; | |
| 1291 | pinctrl_usart2_rts: usart2_rts-0 { | |
| 1292 | atmel,pins = <AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_RX3, PWMH1 */ | |
| 1293 | }; | |
| 1294 | pinctrl_usart2_cts: usart2_cts-0 { | |
| 1295 | atmel,pins = <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with G0_TXER, ISI_VSYNC */ | |
| 1296 | }; | |
| 1297 | }; | |
| 1298 | ||
| 1299 | usart3 { | |
| 1300 | pinctrl_usart3: usart3-0 { | |
| 1301 | atmel,pins = | |
| 1302 | <AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ | |
| 1303 | AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ | |
| 1304 | >; | |
| 1305 | }; | |
| 1306 | }; | |
| 1307 | ||
| 1308 | usart4 { | |
| 1309 | pinctrl_usart4: usart4-0 { | |
| 1310 | atmel,pins = | |
| 1311 | <AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* RXD */ | |
| 1312 | AT91_PIOE 27 AT91_PERIPH_B AT91_PINCTRL_PULL_UP /* TXD */ | |
| 1313 | >; | |
| 1314 | }; | |
| 1315 | pinctrl_usart4_rts: usart4_rts-0 { | |
| 1316 | atmel,pins = <AT91_PIOE 28 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* conflicts with NWAIT, A19 */ | |
| 1317 | }; | |
| 1318 | pinctrl_usart4_cts: usart4_cts-0 { | |
| 1319 | atmel,pins = <AT91_PIOE 0 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* conflicts with A0/NBS0, MCI0_CDB */ | |
| 1320 | }; | |
| 1321 | }; | |
| 1322 | }; | |
| 1323 | ||
| 1324 | aic: interrupt-controller@fc06e000 { | |
| 1325 | #interrupt-cells = <3>; | |
| 1326 | compatible = "atmel,sama5d4-aic"; | |
| 1327 | interrupt-controller; | |
| 1328 | reg = <0xfc06e000 0x200>; | |
| 1329 | atmel,external-irqs = <56>; | |
| 1330 | }; | |
| 1331 | }; | |
| 1332 | }; | |
| 1333 | }; |