Commit | Line | Data |
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a3f22db5 SH |
1 | /* |
2 | * Device Tree Source for the SH73A0 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /include/ "skeleton.dtsi" | |
12 | ||
00df6113 | 13 | #include <dt-bindings/clock/sh73a0-clock.h> |
30225743 | 14 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
5f75e73c LP |
15 | #include <dt-bindings/interrupt-controller/irq.h> |
16 | ||
a3f22db5 SH |
17 | / { |
18 | compatible = "renesas,sh73a0"; | |
f170b97c | 19 | interrupt-parent = <&gic>; |
a3f22db5 SH |
20 | |
21 | cpus { | |
c5795aec SH |
22 | #address-cells = <1>; |
23 | #size-cells = <0>; | |
24 | ||
a3f22db5 | 25 | cpu@0 { |
c5795aec | 26 | device_type = "cpu"; |
a3f22db5 | 27 | compatible = "arm,cortex-a9"; |
c5795aec | 28 | reg = <0>; |
13bd825b | 29 | clock-frequency = <1196000000>; |
bee7a18e | 30 | power-domains = <&pd_a2sl>; |
c8d9fdbe | 31 | next-level-cache = <&L2>; |
a3f22db5 SH |
32 | }; |
33 | cpu@1 { | |
c5795aec | 34 | device_type = "cpu"; |
a3f22db5 | 35 | compatible = "arm,cortex-a9"; |
c5795aec | 36 | reg = <1>; |
13bd825b | 37 | clock-frequency = <1196000000>; |
bee7a18e | 38 | power-domains = <&pd_a2sl>; |
c8d9fdbe | 39 | next-level-cache = <&L2>; |
a3f22db5 | 40 | }; |
30225743 GU |
41 | }; |
42 | ||
43 | timer@f0000600 { | |
44 | compatible = "arm,cortex-a9-twd-timer"; | |
45 | reg = <0xf0000600 0x20>; | |
46 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; | |
47 | clocks = <&twd_clk>; | |
a3f22db5 SH |
48 | }; |
49 | ||
50 | gic: interrupt-controller@f0001000 { | |
51 | compatible = "arm,cortex-a9-gic"; | |
52 | #interrupt-cells = <3>; | |
a3f22db5 SH |
53 | interrupt-controller; |
54 | reg = <0xf0001000 0x1000>, | |
55 | <0xf0000100 0x100>; | |
56 | }; | |
48609533 | 57 | |
c8d9fdbe GU |
58 | L2: cache-controller { |
59 | compatible = "arm,pl310-cache"; | |
60 | reg = <0xf0100000 0x1000>; | |
10bbad96 | 61 | interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; |
c8d9fdbe GU |
62 | power-domains = <&pd_a3sm>; |
63 | arm,data-latency = <3 3 3>; | |
64 | arm,tag-latency = <2 2 2>; | |
65 | arm,shared-override; | |
66 | cache-unified; | |
67 | cache-level = <2>; | |
68 | }; | |
69 | ||
29828c87 GU |
70 | sbsc2: memory-controller@fb400000 { |
71 | compatible = "renesas,sbsc-sh73a0"; | |
72 | reg = <0xfb400000 0x400>; | |
10bbad96 SH |
73 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, |
74 | <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
29828c87 | 75 | interrupt-names = "sec", "temp"; |
bee7a18e | 76 | power-domains = <&pd_a4bc1>; |
29828c87 GU |
77 | }; |
78 | ||
79 | sbsc1: memory-controller@fe400000 { | |
80 | compatible = "renesas,sbsc-sh73a0"; | |
81 | reg = <0xfe400000 0x400>; | |
10bbad96 SH |
82 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, |
83 | <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
29828c87 | 84 | interrupt-names = "sec", "temp"; |
bee7a18e | 85 | power-domains = <&pd_a4bc0>; |
29828c87 GU |
86 | }; |
87 | ||
4c90483a MD |
88 | pmu { |
89 | compatible = "arm,cortex-a9-pmu"; | |
10bbad96 SH |
90 | interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, |
91 | <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
4c90483a MD |
92 | }; |
93 | ||
6a5336a7 UH |
94 | cmt1: timer@e6138000 { |
95 | compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; | |
96 | reg = <0xe6138000 0x200>; | |
10bbad96 | 97 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
bee7a18e GU |
98 | clocks = <&mstp3_clks SH73A0_CLK_CMT1>; |
99 | clock-names = "fck"; | |
100 | power-domains = <&pd_c5>; | |
6a5336a7 UH |
101 | |
102 | renesas,channels-mask = <0x3f>; | |
103 | ||
104 | status = "disabled"; | |
105 | }; | |
106 | ||
4239baee | 107 | irqpin0: interrupt-controller@e6900000 { |
8bb44445 | 108 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
558f8740 GL |
109 | #interrupt-cells = <2>; |
110 | interrupt-controller; | |
111 | reg = <0xe6900000 4>, | |
112 | <0xe6900010 4>, | |
113 | <0xe6900020 1>, | |
114 | <0xe6900040 1>, | |
115 | <0xe6900060 1>; | |
10bbad96 SH |
116 | interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH |
117 | GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH | |
118 | GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH | |
119 | GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH | |
120 | GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH | |
121 | GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH | |
122 | GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH | |
123 | GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; | |
56a215d6 | 124 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
bee7a18e | 125 | power-domains = <&pd_a4s>; |
48bdf06d | 126 | control-parent; |
558f8740 GL |
127 | }; |
128 | ||
4239baee | 129 | irqpin1: interrupt-controller@e6900004 { |
8bb44445 | 130 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
558f8740 GL |
131 | #interrupt-cells = <2>; |
132 | interrupt-controller; | |
133 | reg = <0xe6900004 4>, | |
134 | <0xe6900014 4>, | |
135 | <0xe6900024 1>, | |
136 | <0xe6900044 1>, | |
137 | <0xe6900064 1>; | |
10bbad96 SH |
138 | interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH |
139 | GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH | |
140 | GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH | |
141 | GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH | |
142 | GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH | |
143 | GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH | |
144 | GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH | |
145 | GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; | |
56a215d6 | 146 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
bee7a18e | 147 | power-domains = <&pd_a4s>; |
558f8740 GL |
148 | control-parent; |
149 | }; | |
150 | ||
4239baee | 151 | irqpin2: interrupt-controller@e6900008 { |
8bb44445 | 152 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
558f8740 GL |
153 | #interrupt-cells = <2>; |
154 | interrupt-controller; | |
155 | reg = <0xe6900008 4>, | |
156 | <0xe6900018 4>, | |
157 | <0xe6900028 1>, | |
158 | <0xe6900048 1>, | |
159 | <0xe6900068 1>; | |
10bbad96 SH |
160 | interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH |
161 | GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH | |
162 | GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH | |
163 | GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH | |
164 | GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH | |
165 | GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH | |
166 | GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH | |
167 | GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
56a215d6 | 168 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
bee7a18e | 169 | power-domains = <&pd_a4s>; |
48bdf06d | 170 | control-parent; |
558f8740 GL |
171 | }; |
172 | ||
4239baee | 173 | irqpin3: interrupt-controller@e690000c { |
8bb44445 | 174 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
558f8740 GL |
175 | #interrupt-cells = <2>; |
176 | interrupt-controller; | |
177 | reg = <0xe690000c 4>, | |
178 | <0xe690001c 4>, | |
179 | <0xe690002c 1>, | |
180 | <0xe690004c 1>, | |
181 | <0xe690006c 1>; | |
10bbad96 SH |
182 | interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH |
183 | GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH | |
184 | GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH | |
185 | GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH | |
186 | GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH | |
187 | GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH | |
188 | GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH | |
189 | GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
56a215d6 | 190 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
bee7a18e | 191 | power-domains = <&pd_a4s>; |
48bdf06d | 192 | control-parent; |
558f8740 GL |
193 | }; |
194 | ||
561a1a31 | 195 | i2c0: i2c@e6820000 { |
48609533 SH |
196 | #address-cells = <1>; |
197 | #size-cells = <0>; | |
dd4dc874 | 198 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 199 | reg = <0xe6820000 0x425>; |
10bbad96 SH |
200 | interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH |
201 | GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH | |
202 | GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH | |
203 | GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 204 | clocks = <&mstp1_clks SH73A0_CLK_IIC0>; |
bee7a18e | 205 | power-domains = <&pd_a3sp>; |
eda3a4fa | 206 | status = "disabled"; |
48609533 SH |
207 | }; |
208 | ||
561a1a31 | 209 | i2c1: i2c@e6822000 { |
48609533 SH |
210 | #address-cells = <1>; |
211 | #size-cells = <0>; | |
dd4dc874 | 212 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 213 | reg = <0xe6822000 0x425>; |
10bbad96 SH |
214 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH |
215 | GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH | |
216 | GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH | |
217 | GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 218 | clocks = <&mstp3_clks SH73A0_CLK_IIC1>; |
bee7a18e | 219 | power-domains = <&pd_a3sp>; |
eda3a4fa | 220 | status = "disabled"; |
48609533 SH |
221 | }; |
222 | ||
561a1a31 | 223 | i2c2: i2c@e6824000 { |
48609533 SH |
224 | #address-cells = <1>; |
225 | #size-cells = <0>; | |
dd4dc874 | 226 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 227 | reg = <0xe6824000 0x425>; |
10bbad96 SH |
228 | interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH |
229 | GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH | |
230 | GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH | |
231 | GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 232 | clocks = <&mstp0_clks SH73A0_CLK_IIC2>; |
bee7a18e | 233 | power-domains = <&pd_a3sp>; |
eda3a4fa | 234 | status = "disabled"; |
48609533 SH |
235 | }; |
236 | ||
561a1a31 | 237 | i2c3: i2c@e6826000 { |
48609533 SH |
238 | #address-cells = <1>; |
239 | #size-cells = <0>; | |
dd4dc874 | 240 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 241 | reg = <0xe6826000 0x425>; |
10bbad96 SH |
242 | interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH |
243 | GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH | |
244 | GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH | |
245 | GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 246 | clocks = <&mstp4_clks SH73A0_CLK_IIC3>; |
bee7a18e | 247 | power-domains = <&pd_a3sp>; |
eda3a4fa | 248 | status = "disabled"; |
48609533 SH |
249 | }; |
250 | ||
561a1a31 | 251 | i2c4: i2c@e6828000 { |
48609533 SH |
252 | #address-cells = <1>; |
253 | #size-cells = <0>; | |
dd4dc874 | 254 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 255 | reg = <0xe6828000 0x425>; |
10bbad96 SH |
256 | interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH |
257 | GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH | |
258 | GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH | |
259 | GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 260 | clocks = <&mstp4_clks SH73A0_CLK_IIC4>; |
bee7a18e | 261 | power-domains = <&pd_c5>; |
eda3a4fa | 262 | status = "disabled"; |
48609533 | 263 | }; |
546e5d3e | 264 | |
33f6be3b | 265 | mmcif: mmc@e6bd0000 { |
546e5d3e GL |
266 | compatible = "renesas,sh-mmcif"; |
267 | reg = <0xe6bd0000 0x100>; | |
10bbad96 SH |
268 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH |
269 | GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 270 | clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; |
bee7a18e | 271 | power-domains = <&pd_a3sp>; |
546e5d3e GL |
272 | reg-io-width = <4>; |
273 | status = "disabled"; | |
274 | }; | |
275 | ||
d74f61fe GU |
276 | msiof0: spi@e6e20000 { |
277 | compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; | |
278 | reg = <0xe6e20000 0x0064>; | |
10bbad96 | 279 | interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; |
d74f61fe GU |
280 | clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>; |
281 | power-domains = <&pd_a3sp>; | |
282 | #address-cells = <1>; | |
283 | #size-cells = <0>; | |
284 | status = "disabled"; | |
285 | }; | |
286 | ||
287 | msiof1: spi@e6e10000 { | |
288 | compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; | |
289 | reg = <0xe6e10000 0x0064>; | |
10bbad96 | 290 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
d74f61fe GU |
291 | clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>; |
292 | power-domains = <&pd_a3sp>; | |
293 | #address-cells = <1>; | |
294 | #size-cells = <0>; | |
295 | status = "disabled"; | |
296 | }; | |
297 | ||
298 | msiof2: spi@e6e00000 { | |
299 | compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; | |
300 | reg = <0xe6e00000 0x0064>; | |
10bbad96 | 301 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
d74f61fe GU |
302 | clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>; |
303 | power-domains = <&pd_a3sp>; | |
304 | #address-cells = <1>; | |
305 | #size-cells = <0>; | |
306 | status = "disabled"; | |
307 | }; | |
308 | ||
309 | msiof3: spi@e6c90000 { | |
310 | compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof"; | |
311 | reg = <0xe6c90000 0x0064>; | |
10bbad96 | 312 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
d74f61fe GU |
313 | clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>; |
314 | power-domains = <&pd_a3sp>; | |
315 | #address-cells = <1>; | |
316 | #size-cells = <0>; | |
317 | status = "disabled"; | |
318 | }; | |
319 | ||
33f6be3b | 320 | sdhi0: sd@ee100000 { |
e8a8b8a3 | 321 | compatible = "renesas,sdhi-sh73a0"; |
546e5d3e | 322 | reg = <0xee100000 0x100>; |
10bbad96 SH |
323 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH |
324 | GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH | |
325 | GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 326 | clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; |
bee7a18e | 327 | power-domains = <&pd_a3sp>; |
a463f731 | 328 | cap-sd-highspeed; |
546e5d3e GL |
329 | status = "disabled"; |
330 | }; | |
331 | ||
332 | /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ | |
33f6be3b | 333 | sdhi1: sd@ee120000 { |
e8a8b8a3 | 334 | compatible = "renesas,sdhi-sh73a0"; |
546e5d3e | 335 | reg = <0xee120000 0x100>; |
10bbad96 SH |
336 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH |
337 | GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 338 | clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; |
bee7a18e | 339 | power-domains = <&pd_a3sp>; |
546e5d3e | 340 | toshiba,mmc-wrprotect-disable; |
a463f731 | 341 | cap-sd-highspeed; |
546e5d3e GL |
342 | status = "disabled"; |
343 | }; | |
344 | ||
33f6be3b | 345 | sdhi2: sd@ee140000 { |
e8a8b8a3 | 346 | compatible = "renesas,sdhi-sh73a0"; |
546e5d3e | 347 | reg = <0xee140000 0x100>; |
10bbad96 SH |
348 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH |
349 | GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 350 | clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; |
bee7a18e | 351 | power-domains = <&pd_a3sp>; |
546e5d3e | 352 | toshiba,mmc-wrprotect-disable; |
a463f731 | 353 | cap-sd-highspeed; |
546e5d3e GL |
354 | status = "disabled"; |
355 | }; | |
3f59007e | 356 | |
2131421b SH |
357 | scifa0: serial@e6c40000 { |
358 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
359 | reg = <0xe6c40000 0x100>; | |
10bbad96 | 360 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 361 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; |
46ae0e37 | 362 | clock-names = "fck"; |
bee7a18e | 363 | power-domains = <&pd_a3sp>; |
2131421b SH |
364 | status = "disabled"; |
365 | }; | |
366 | ||
367 | scifa1: serial@e6c50000 { | |
368 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
369 | reg = <0xe6c50000 0x100>; | |
10bbad96 | 370 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 371 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; |
46ae0e37 | 372 | clock-names = "fck"; |
bee7a18e | 373 | power-domains = <&pd_a3sp>; |
2131421b SH |
374 | status = "disabled"; |
375 | }; | |
376 | ||
377 | scifa2: serial@e6c60000 { | |
378 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
379 | reg = <0xe6c60000 0x100>; | |
10bbad96 | 380 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 381 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; |
46ae0e37 | 382 | clock-names = "fck"; |
bee7a18e | 383 | power-domains = <&pd_a3sp>; |
2131421b SH |
384 | status = "disabled"; |
385 | }; | |
386 | ||
387 | scifa3: serial@e6c70000 { | |
388 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
389 | reg = <0xe6c70000 0x100>; | |
10bbad96 | 390 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 391 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; |
46ae0e37 | 392 | clock-names = "fck"; |
bee7a18e | 393 | power-domains = <&pd_a3sp>; |
2131421b SH |
394 | status = "disabled"; |
395 | }; | |
396 | ||
397 | scifa4: serial@e6c80000 { | |
398 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
399 | reg = <0xe6c80000 0x100>; | |
10bbad96 | 400 | interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 401 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; |
46ae0e37 | 402 | clock-names = "fck"; |
bee7a18e | 403 | power-domains = <&pd_a3sp>; |
2131421b SH |
404 | status = "disabled"; |
405 | }; | |
406 | ||
407 | scifa5: serial@e6cb0000 { | |
408 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
409 | reg = <0xe6cb0000 0x100>; | |
10bbad96 | 410 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 411 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; |
46ae0e37 | 412 | clock-names = "fck"; |
bee7a18e | 413 | power-domains = <&pd_a3sp>; |
2131421b SH |
414 | status = "disabled"; |
415 | }; | |
416 | ||
417 | scifa6: serial@e6cc0000 { | |
418 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
419 | reg = <0xe6cc0000 0x100>; | |
10bbad96 | 420 | interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 421 | clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; |
46ae0e37 | 422 | clock-names = "fck"; |
bee7a18e | 423 | power-domains = <&pd_a3sp>; |
2131421b SH |
424 | status = "disabled"; |
425 | }; | |
426 | ||
427 | scifa7: serial@e6cd0000 { | |
428 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
429 | reg = <0xe6cd0000 0x100>; | |
10bbad96 | 430 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 431 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; |
46ae0e37 | 432 | clock-names = "fck"; |
bee7a18e | 433 | power-domains = <&pd_a3sp>; |
2131421b SH |
434 | status = "disabled"; |
435 | }; | |
436 | ||
dfaac7b7 | 437 | scifb: serial@e6c30000 { |
2131421b SH |
438 | compatible = "renesas,scifb-sh73a0", "renesas,scifb"; |
439 | reg = <0xe6c30000 0x100>; | |
10bbad96 | 440 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 | 441 | clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; |
46ae0e37 | 442 | clock-names = "fck"; |
bee7a18e | 443 | power-domains = <&pd_a3sp>; |
2131421b SH |
444 | status = "disabled"; |
445 | }; | |
446 | ||
3f59007e LP |
447 | pfc: pfc@e6050000 { |
448 | compatible = "renesas,pfc-sh73a0"; | |
449 | reg = <0xe6050000 0x8000>, | |
450 | <0xe605801c 0x1c>; | |
451 | gpio-controller; | |
452 | #gpio-cells = <2>; | |
94bdc48d GU |
453 | gpio-ranges = |
454 | <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>, | |
455 | <&pfc 288 288 22>; | |
aba76d28 LP |
456 | interrupts-extended = |
457 | <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, | |
458 | <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, | |
459 | <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, | |
460 | <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, | |
461 | <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, | |
462 | <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, | |
463 | <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, | |
464 | <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; | |
bee7a18e GU |
465 | power-domains = <&pd_c5>; |
466 | }; | |
467 | ||
468 | sysc: system-controller@e6180000 { | |
469 | compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile"; | |
470 | reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>; | |
471 | ||
472 | pm-domains { | |
473 | pd_c5: c5 { | |
474 | #address-cells = <1>; | |
475 | #size-cells = <0>; | |
476 | #power-domain-cells = <0>; | |
477 | ||
478 | pd_c4: c4@0 { | |
479 | reg = <0>; | |
480 | #power-domain-cells = <0>; | |
481 | }; | |
482 | ||
483 | pd_d4: d4@1 { | |
484 | reg = <1>; | |
485 | #power-domain-cells = <0>; | |
486 | }; | |
487 | ||
488 | pd_a4bc0: a4bc0@4 { | |
489 | reg = <4>; | |
490 | #power-domain-cells = <0>; | |
491 | }; | |
492 | ||
493 | pd_a4bc1: a4bc1@5 { | |
494 | reg = <5>; | |
495 | #power-domain-cells = <0>; | |
496 | }; | |
497 | ||
498 | pd_a4lc0: a4lc0@6 { | |
499 | reg = <6>; | |
500 | #power-domain-cells = <0>; | |
501 | }; | |
502 | ||
503 | pd_a4lc1: a4lc1@7 { | |
504 | reg = <7>; | |
505 | #power-domain-cells = <0>; | |
506 | }; | |
507 | ||
508 | pd_a4mp: a4mp@8 { | |
509 | reg = <8>; | |
510 | #address-cells = <1>; | |
511 | #size-cells = <0>; | |
512 | #power-domain-cells = <0>; | |
513 | ||
514 | pd_a3mp: a3mp@9 { | |
515 | reg = <9>; | |
516 | #power-domain-cells = <0>; | |
517 | }; | |
518 | ||
519 | pd_a3vc: a3vc@10 { | |
520 | reg = <10>; | |
521 | #power-domain-cells = <0>; | |
522 | }; | |
523 | }; | |
524 | ||
525 | pd_a4rm: a4rm@12 { | |
526 | reg = <12>; | |
527 | #address-cells = <1>; | |
528 | #size-cells = <0>; | |
529 | #power-domain-cells = <0>; | |
530 | ||
531 | pd_a3r: a3r@13 { | |
532 | reg = <13>; | |
533 | #address-cells = <1>; | |
534 | #size-cells = <0>; | |
535 | #power-domain-cells = <0>; | |
536 | ||
537 | pd_a2rv: a2rv@14 { | |
538 | reg = <14>; | |
539 | #address-cells = <1>; | |
540 | #size-cells = <0>; | |
541 | #power-domain-cells = <0>; | |
542 | }; | |
543 | }; | |
544 | }; | |
545 | ||
546 | pd_a4s: a4s@16 { | |
547 | reg = <16>; | |
548 | #address-cells = <1>; | |
549 | #size-cells = <0>; | |
550 | #power-domain-cells = <0>; | |
551 | ||
552 | pd_a3sp: a3sp@17 { | |
553 | reg = <17>; | |
554 | #power-domain-cells = <0>; | |
555 | }; | |
556 | ||
557 | pd_a3sg: a3sg@18 { | |
558 | reg = <18>; | |
559 | #power-domain-cells = <0>; | |
560 | }; | |
561 | ||
562 | pd_a3sm: a3sm@19 { | |
563 | reg = <19>; | |
564 | #address-cells = <1>; | |
565 | #size-cells = <0>; | |
566 | #power-domain-cells = <0>; | |
567 | ||
568 | pd_a2sl: a2sl@20 { | |
569 | reg = <20>; | |
570 | #power-domain-cells = <0>; | |
571 | }; | |
572 | }; | |
573 | }; | |
574 | }; | |
575 | }; | |
3f59007e | 576 | }; |
63b1303d KM |
577 | |
578 | sh_fsi2: sound@ec230000 { | |
579 | #sound-dai-cells = <1>; | |
f76452fd | 580 | compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; |
63b1303d | 581 | reg = <0xec230000 0x400>; |
10bbad96 | 582 | interrupts = <GIC_SPI 146 0x4>; |
bee7a18e | 583 | power-domains = <&pd_a4mp>; |
63b1303d KM |
584 | status = "disabled"; |
585 | }; | |
00df6113 | 586 | |
217b6e65 GU |
587 | bsc: bus@fec10000 { |
588 | compatible = "renesas,bsc-sh73a0", "renesas,bsc", | |
589 | "simple-pm-bus"; | |
590 | #address-cells = <1>; | |
591 | #size-cells = <1>; | |
592 | ranges = <0 0 0x20000000>; | |
593 | reg = <0xfec10000 0x400>; | |
10bbad96 | 594 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
217b6e65 | 595 | clocks = <&zb_clk>; |
bee7a18e | 596 | power-domains = <&pd_a4s>; |
217b6e65 GU |
597 | }; |
598 | ||
00df6113 UH |
599 | clocks { |
600 | #address-cells = <1>; | |
601 | #size-cells = <1>; | |
602 | ranges; | |
603 | ||
604 | /* External root clocks */ | |
605 | extalr_clk: extalr_clk { | |
606 | compatible = "fixed-clock"; | |
607 | #clock-cells = <0>; | |
608 | clock-frequency = <32768>; | |
609 | clock-output-names = "extalr"; | |
610 | }; | |
611 | extal1_clk: extal1_clk { | |
612 | compatible = "fixed-clock"; | |
613 | #clock-cells = <0>; | |
614 | clock-frequency = <26000000>; | |
615 | clock-output-names = "extal1"; | |
616 | }; | |
617 | extal2_clk: extal2_clk { | |
618 | compatible = "fixed-clock"; | |
619 | #clock-cells = <0>; | |
620 | clock-output-names = "extal2"; | |
621 | }; | |
622 | extcki_clk: extcki_clk { | |
623 | compatible = "fixed-clock"; | |
624 | #clock-cells = <0>; | |
625 | clock-output-names = "extcki"; | |
626 | }; | |
627 | fsiack_clk: fsiack_clk { | |
628 | compatible = "fixed-clock"; | |
629 | #clock-cells = <0>; | |
630 | clock-frequency = <0>; | |
631 | clock-output-names = "fsiack"; | |
632 | }; | |
633 | fsibck_clk: fsibck_clk { | |
634 | compatible = "fixed-clock"; | |
635 | #clock-cells = <0>; | |
636 | clock-frequency = <0>; | |
637 | clock-output-names = "fsibck"; | |
638 | }; | |
639 | ||
640 | /* Special CPG clocks */ | |
641 | cpg_clocks: cpg_clocks@e6150000 { | |
642 | compatible = "renesas,sh73a0-cpg-clocks"; | |
643 | reg = <0xe6150000 0x10000>; | |
644 | clocks = <&extal1_clk>, <&extal2_clk>; | |
645 | #clock-cells = <1>; | |
646 | clock-output-names = "main", "pll0", "pll1", "pll2", | |
647 | "pll3", "dsi0phy", "dsi1phy", | |
648 | "zg", "m3", "b", "m1", "m2", | |
649 | "z", "zx", "hp"; | |
650 | }; | |
651 | ||
652 | /* Variable factor clocks (DIV6) */ | |
653 | vclk1_clk: vclk1_clk@e6150008 { | |
654 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
655 | reg = <0xe6150008 4>; | |
09940bf0 UH |
656 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
657 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, | |
658 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, | |
659 | <0>; | |
00df6113 UH |
660 | #clock-cells = <0>; |
661 | clock-output-names = "vclk1"; | |
662 | }; | |
663 | vclk2_clk: vclk2_clk@e615000c { | |
664 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
665 | reg = <0xe615000c 4>; | |
09940bf0 UH |
666 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
667 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, | |
668 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, | |
669 | <0>; | |
00df6113 UH |
670 | #clock-cells = <0>; |
671 | clock-output-names = "vclk2"; | |
672 | }; | |
673 | vclk3_clk: vclk3_clk@e615001c { | |
674 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
675 | reg = <0xe615001c 4>; | |
09940bf0 UH |
676 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
677 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, | |
678 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, | |
679 | <0>; | |
00df6113 UH |
680 | #clock-cells = <0>; |
681 | clock-output-names = "vclk3"; | |
682 | }; | |
683 | zb_clk: zb_clk@e6150010 { | |
684 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
685 | reg = <0xe6150010 4>; | |
09940bf0 UH |
686 | clocks = <&pll1_div2_clk>, <0>, |
687 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
688 | #clock-cells = <0>; |
689 | clock-output-names = "zb"; | |
690 | }; | |
691 | flctl_clk: flctl_clk@e6150014 { | |
692 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
693 | reg = <0xe6150014 4>; | |
09940bf0 UH |
694 | clocks = <&pll1_div2_clk>, <0>, |
695 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
696 | #clock-cells = <0>; |
697 | clock-output-names = "flctlck"; | |
698 | }; | |
699 | sdhi0_clk: sdhi0_clk@e6150074 { | |
700 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
701 | reg = <0xe6150074 4>; | |
09940bf0 UH |
702 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
703 | <&pll1_div13_clk>, <0>; | |
00df6113 UH |
704 | #clock-cells = <0>; |
705 | clock-output-names = "sdhi0ck"; | |
706 | }; | |
707 | sdhi1_clk: sdhi1_clk@e6150078 { | |
708 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
709 | reg = <0xe6150078 4>; | |
09940bf0 UH |
710 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
711 | <&pll1_div13_clk>, <0>; | |
00df6113 UH |
712 | #clock-cells = <0>; |
713 | clock-output-names = "sdhi1ck"; | |
714 | }; | |
715 | sdhi2_clk: sdhi2_clk@e615007c { | |
716 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
717 | reg = <0xe615007c 4>; | |
09940bf0 UH |
718 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
719 | <&pll1_div13_clk>, <0>; | |
00df6113 UH |
720 | #clock-cells = <0>; |
721 | clock-output-names = "sdhi2ck"; | |
722 | }; | |
723 | fsia_clk: fsia_clk@e6150018 { | |
724 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
725 | reg = <0xe6150018 4>; | |
09940bf0 UH |
726 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
727 | <&fsiack_clk>, <&fsiack_clk>; | |
00df6113 UH |
728 | #clock-cells = <0>; |
729 | clock-output-names = "fsia"; | |
730 | }; | |
731 | fsib_clk: fsib_clk@e6150090 { | |
732 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
733 | reg = <0xe6150090 4>; | |
09940bf0 UH |
734 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
735 | <&fsibck_clk>, <&fsibck_clk>; | |
00df6113 UH |
736 | #clock-cells = <0>; |
737 | clock-output-names = "fsib"; | |
738 | }; | |
739 | sub_clk: sub_clk@e6150080 { | |
740 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
741 | reg = <0xe6150080 4>; | |
09940bf0 UH |
742 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
743 | <&extal2_clk>, <&extal2_clk>; | |
00df6113 UH |
744 | #clock-cells = <0>; |
745 | clock-output-names = "sub"; | |
746 | }; | |
747 | spua_clk: spua_clk@e6150084 { | |
748 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
749 | reg = <0xe6150084 4>; | |
09940bf0 UH |
750 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
751 | <&extal2_clk>, <&extal2_clk>; | |
00df6113 UH |
752 | #clock-cells = <0>; |
753 | clock-output-names = "spua"; | |
754 | }; | |
755 | spuv_clk: spuv_clk@e6150094 { | |
756 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
757 | reg = <0xe6150094 4>; | |
09940bf0 UH |
758 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
759 | <&extal2_clk>, <&extal2_clk>; | |
00df6113 UH |
760 | #clock-cells = <0>; |
761 | clock-output-names = "spuv"; | |
762 | }; | |
763 | msu_clk: msu_clk@e6150088 { | |
764 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
765 | reg = <0xe6150088 4>; | |
09940bf0 UH |
766 | clocks = <&pll1_div2_clk>, <0>, |
767 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
768 | #clock-cells = <0>; |
769 | clock-output-names = "msu"; | |
770 | }; | |
771 | hsi_clk: hsi_clk@e615008c { | |
772 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
773 | reg = <0xe615008c 4>; | |
09940bf0 UH |
774 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
775 | <&pll1_div7_clk>, <0>; | |
00df6113 UH |
776 | #clock-cells = <0>; |
777 | clock-output-names = "hsi"; | |
778 | }; | |
779 | mfg1_clk: mfg1_clk@e6150098 { | |
780 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
781 | reg = <0xe6150098 4>; | |
09940bf0 UH |
782 | clocks = <&pll1_div2_clk>, <0>, |
783 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
784 | #clock-cells = <0>; |
785 | clock-output-names = "mfg1"; | |
786 | }; | |
787 | mfg2_clk: mfg2_clk@e615009c { | |
788 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
789 | reg = <0xe615009c 4>; | |
09940bf0 UH |
790 | clocks = <&pll1_div2_clk>, <0>, |
791 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
792 | #clock-cells = <0>; |
793 | clock-output-names = "mfg2"; | |
794 | }; | |
795 | dsit_clk: dsit_clk@e6150060 { | |
796 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
797 | reg = <0xe6150060 4>; | |
09940bf0 UH |
798 | clocks = <&pll1_div2_clk>, <0>, |
799 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
800 | #clock-cells = <0>; |
801 | clock-output-names = "dsit"; | |
802 | }; | |
803 | dsi0p_clk: dsi0p_clk@e6150064 { | |
804 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
805 | reg = <0xe6150064 4>; | |
09940bf0 UH |
806 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
807 | <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, | |
808 | <&extcki_clk>, <0>, <0>, <0>; | |
00df6113 UH |
809 | #clock-cells = <0>; |
810 | clock-output-names = "dsi0pck"; | |
811 | }; | |
812 | ||
813 | /* Fixed factor clocks */ | |
814 | main_div2_clk: main_div2_clk { | |
815 | compatible = "fixed-factor-clock"; | |
816 | clocks = <&cpg_clocks SH73A0_CLK_MAIN>; | |
817 | #clock-cells = <0>; | |
818 | clock-div = <2>; | |
819 | clock-mult = <1>; | |
820 | clock-output-names = "main_div2"; | |
821 | }; | |
822 | pll1_div2_clk: pll1_div2_clk { | |
823 | compatible = "fixed-factor-clock"; | |
824 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
825 | #clock-cells = <0>; | |
826 | clock-div = <2>; | |
827 | clock-mult = <1>; | |
828 | clock-output-names = "pll1_div2"; | |
829 | }; | |
830 | pll1_div7_clk: pll1_div7_clk { | |
831 | compatible = "fixed-factor-clock"; | |
832 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
833 | #clock-cells = <0>; | |
834 | clock-div = <7>; | |
835 | clock-mult = <1>; | |
836 | clock-output-names = "pll1_div7"; | |
837 | }; | |
838 | pll1_div13_clk: pll1_div13_clk { | |
839 | compatible = "fixed-factor-clock"; | |
840 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
841 | #clock-cells = <0>; | |
842 | clock-div = <13>; | |
843 | clock-mult = <1>; | |
844 | clock-output-names = "pll1_div13"; | |
845 | }; | |
846 | twd_clk: twd_clk { | |
847 | compatible = "fixed-factor-clock"; | |
848 | clocks = <&cpg_clocks SH73A0_CLK_Z>; | |
849 | #clock-cells = <0>; | |
850 | clock-div = <4>; | |
851 | clock-mult = <1>; | |
852 | clock-output-names = "twd"; | |
853 | }; | |
854 | ||
855 | /* Gate clocks */ | |
856 | mstp0_clks: mstp0_clks@e6150130 { | |
857 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
858 | reg = <0xe6150130 4>, <0xe6150030 4>; | |
23d711ab | 859 | clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>; |
00df6113 UH |
860 | #clock-cells = <1>; |
861 | clock-indices = < | |
23d711ab | 862 | SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0 |
00df6113 UH |
863 | >; |
864 | clock-output-names = | |
23d711ab | 865 | "iic2", "msiof0"; |
00df6113 UH |
866 | }; |
867 | mstp1_clks: mstp1_clks@e6150134 { | |
868 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
869 | reg = <0xe6150134 4>, <0xe6150038 4>; | |
870 | clocks = <&cpg_clocks SH73A0_CLK_B>, | |
871 | <&cpg_clocks SH73A0_CLK_B>, | |
872 | <&cpg_clocks SH73A0_CLK_B>, | |
873 | <&cpg_clocks SH73A0_CLK_B>, | |
874 | <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, | |
875 | <&cpg_clocks SH73A0_CLK_HP>, | |
876 | <&cpg_clocks SH73A0_CLK_ZG>, | |
877 | <&cpg_clocks SH73A0_CLK_B>; | |
878 | #clock-cells = <1>; | |
879 | clock-indices = < | |
880 | SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 | |
881 | SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 | |
882 | SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 | |
883 | SH73A0_CLK_IIC0 SH73A0_CLK_SGX | |
884 | SH73A0_CLK_LCDC0 | |
885 | >; | |
886 | clock-output-names = | |
887 | "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", | |
888 | "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; | |
889 | }; | |
890 | mstp2_clks: mstp2_clks@e6150138 { | |
891 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
892 | reg = <0xe6150138 4>, <0xe6150040 4>; | |
893 | clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, | |
894 | <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, | |
23d711ab GU |
895 | <&sub_clk>, <&sub_clk>, <&sub_clk>, |
896 | <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
897 | <&sub_clk>, <&sub_clk>, <&sub_clk>; | |
00df6113 UH |
898 | #clock-cells = <1>; |
899 | clock-indices = < | |
900 | SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC | |
23d711ab GU |
901 | SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3 |
902 | SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5 | |
903 | SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2 | |
904 | SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1 | |
905 | SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3 | |
906 | SH73A0_CLK_SCIFA4 | |
00df6113 UH |
907 | >; |
908 | clock-output-names = | |
23d711ab GU |
909 | "scifa7", "sy_dmac", "mp_dmac", "msiof3", |
910 | "msiof1", "scifa5", "scifb", "msiof2", | |
911 | "scifa0", "scifa1", "scifa2", "scifa3", | |
912 | "scifa4"; | |
00df6113 UH |
913 | }; |
914 | mstp3_clks: mstp3_clks@e615013c { | |
915 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
916 | reg = <0xe615013c 4>, <0xe6150048 4>; | |
917 | clocks = <&sub_clk>, <&extalr_clk>, | |
918 | <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, | |
919 | <&cpg_clocks SH73A0_CLK_HP>, | |
920 | <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, | |
921 | <&sdhi0_clk>, <&sdhi1_clk>, | |
922 | <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, | |
923 | <&main_div2_clk>, <&main_div2_clk>, | |
924 | <&main_div2_clk>, <&main_div2_clk>, | |
925 | <&main_div2_clk>; | |
926 | #clock-cells = <1>; | |
927 | clock-indices = < | |
928 | SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 | |
929 | SH73A0_CLK_FSI SH73A0_CLK_IRDA | |
930 | SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL | |
931 | SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 | |
932 | SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 | |
933 | SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 | |
934 | SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 | |
935 | SH73A0_CLK_TPU4 | |
936 | >; | |
937 | clock-output-names = | |
938 | "scifa6", "cmt1", "fsi", "irda", "iic1", | |
939 | "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", | |
940 | "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; | |
941 | }; | |
942 | mstp4_clks: mstp4_clks@e6150140 { | |
943 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
944 | reg = <0xe6150140 4>, <0xe615004c 4>; | |
945 | clocks = <&cpg_clocks SH73A0_CLK_HP>, | |
946 | <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; | |
947 | #clock-cells = <1>; | |
948 | clock-indices = < | |
949 | SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 | |
950 | SH73A0_CLK_KEYSC | |
951 | >; | |
952 | clock-output-names = | |
953 | "iic3", "iic4", "keysc"; | |
954 | }; | |
56a215d6 GU |
955 | mstp5_clks: mstp5_clks@e6150144 { |
956 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
957 | reg = <0xe6150144 4>, <0xe615003c 4>; | |
958 | clocks = <&cpg_clocks SH73A0_CLK_HP>; | |
959 | #clock-cells = <1>; | |
960 | clock-indices = < | |
961 | SH73A0_CLK_INTCA0 | |
962 | >; | |
963 | clock-output-names = | |
964 | "intca0"; | |
965 | }; | |
00df6113 | 966 | }; |
a3f22db5 | 967 | }; |