Commit | Line | Data |
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a3f22db5 SH |
1 | /* |
2 | * Device Tree Source for the SH73A0 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /include/ "skeleton.dtsi" | |
12 | ||
00df6113 | 13 | #include <dt-bindings/clock/sh73a0-clock.h> |
5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/irq.h> |
15 | ||
a3f22db5 SH |
16 | / { |
17 | compatible = "renesas,sh73a0"; | |
f170b97c | 18 | interrupt-parent = <&gic>; |
a3f22db5 SH |
19 | |
20 | cpus { | |
c5795aec SH |
21 | #address-cells = <1>; |
22 | #size-cells = <0>; | |
23 | ||
a3f22db5 | 24 | cpu@0 { |
c5795aec | 25 | device_type = "cpu"; |
a3f22db5 | 26 | compatible = "arm,cortex-a9"; |
c5795aec | 27 | reg = <0>; |
13bd825b | 28 | clock-frequency = <1196000000>; |
a3f22db5 SH |
29 | }; |
30 | cpu@1 { | |
c5795aec | 31 | device_type = "cpu"; |
a3f22db5 | 32 | compatible = "arm,cortex-a9"; |
c5795aec | 33 | reg = <1>; |
13bd825b | 34 | clock-frequency = <1196000000>; |
a3f22db5 SH |
35 | }; |
36 | }; | |
37 | ||
38 | gic: interrupt-controller@f0001000 { | |
39 | compatible = "arm,cortex-a9-gic"; | |
40 | #interrupt-cells = <3>; | |
a3f22db5 SH |
41 | interrupt-controller; |
42 | reg = <0xf0001000 0x1000>, | |
43 | <0xf0000100 0x100>; | |
44 | }; | |
48609533 | 45 | |
29828c87 GU |
46 | sbsc2: memory-controller@fb400000 { |
47 | compatible = "renesas,sbsc-sh73a0"; | |
48 | reg = <0xfb400000 0x400>; | |
49 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, | |
50 | <0 38 IRQ_TYPE_LEVEL_HIGH>; | |
51 | interrupt-names = "sec", "temp"; | |
52 | }; | |
53 | ||
54 | sbsc1: memory-controller@fe400000 { | |
55 | compatible = "renesas,sbsc-sh73a0"; | |
56 | reg = <0xfe400000 0x400>; | |
57 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, | |
58 | <0 36 IRQ_TYPE_LEVEL_HIGH>; | |
59 | interrupt-names = "sec", "temp"; | |
60 | }; | |
61 | ||
4c90483a MD |
62 | pmu { |
63 | compatible = "arm,cortex-a9-pmu"; | |
5f75e73c LP |
64 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>, |
65 | <0 56 IRQ_TYPE_LEVEL_HIGH>; | |
4c90483a MD |
66 | }; |
67 | ||
6a5336a7 UH |
68 | cmt1: timer@e6138000 { |
69 | compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; | |
70 | reg = <0xe6138000 0x200>; | |
71 | interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; | |
72 | ||
73 | renesas,channels-mask = <0x3f>; | |
74 | ||
f73e1e28 UH |
75 | clocks = <&mstp3_clks SH73A0_CLK_CMT1>; |
76 | clock-names = "fck"; | |
6a5336a7 UH |
77 | status = "disabled"; |
78 | }; | |
79 | ||
558f8740 | 80 | irqpin0: irqpin@e6900000 { |
8bb44445 | 81 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
558f8740 GL |
82 | #interrupt-cells = <2>; |
83 | interrupt-controller; | |
84 | reg = <0xe6900000 4>, | |
85 | <0xe6900010 4>, | |
86 | <0xe6900020 1>, | |
87 | <0xe6900040 1>, | |
88 | <0xe6900060 1>; | |
5f75e73c LP |
89 | interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH |
90 | 0 2 IRQ_TYPE_LEVEL_HIGH | |
91 | 0 3 IRQ_TYPE_LEVEL_HIGH | |
92 | 0 4 IRQ_TYPE_LEVEL_HIGH | |
93 | 0 5 IRQ_TYPE_LEVEL_HIGH | |
94 | 0 6 IRQ_TYPE_LEVEL_HIGH | |
95 | 0 7 IRQ_TYPE_LEVEL_HIGH | |
96 | 0 8 IRQ_TYPE_LEVEL_HIGH>; | |
56a215d6 | 97 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
48bdf06d | 98 | control-parent; |
558f8740 GL |
99 | }; |
100 | ||
101 | irqpin1: irqpin@e6900004 { | |
8bb44445 | 102 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
558f8740 GL |
103 | #interrupt-cells = <2>; |
104 | interrupt-controller; | |
105 | reg = <0xe6900004 4>, | |
106 | <0xe6900014 4>, | |
107 | <0xe6900024 1>, | |
108 | <0xe6900044 1>, | |
109 | <0xe6900064 1>; | |
5f75e73c LP |
110 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH |
111 | 0 10 IRQ_TYPE_LEVEL_HIGH | |
112 | 0 11 IRQ_TYPE_LEVEL_HIGH | |
113 | 0 12 IRQ_TYPE_LEVEL_HIGH | |
114 | 0 13 IRQ_TYPE_LEVEL_HIGH | |
115 | 0 14 IRQ_TYPE_LEVEL_HIGH | |
116 | 0 15 IRQ_TYPE_LEVEL_HIGH | |
117 | 0 16 IRQ_TYPE_LEVEL_HIGH>; | |
56a215d6 | 118 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
558f8740 GL |
119 | control-parent; |
120 | }; | |
121 | ||
122 | irqpin2: irqpin@e6900008 { | |
8bb44445 | 123 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
558f8740 GL |
124 | #interrupt-cells = <2>; |
125 | interrupt-controller; | |
126 | reg = <0xe6900008 4>, | |
127 | <0xe6900018 4>, | |
128 | <0xe6900028 1>, | |
129 | <0xe6900048 1>, | |
130 | <0xe6900068 1>; | |
5f75e73c LP |
131 | interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH |
132 | 0 18 IRQ_TYPE_LEVEL_HIGH | |
133 | 0 19 IRQ_TYPE_LEVEL_HIGH | |
134 | 0 20 IRQ_TYPE_LEVEL_HIGH | |
135 | 0 21 IRQ_TYPE_LEVEL_HIGH | |
136 | 0 22 IRQ_TYPE_LEVEL_HIGH | |
137 | 0 23 IRQ_TYPE_LEVEL_HIGH | |
138 | 0 24 IRQ_TYPE_LEVEL_HIGH>; | |
56a215d6 | 139 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
48bdf06d | 140 | control-parent; |
558f8740 GL |
141 | }; |
142 | ||
143 | irqpin3: irqpin@e690000c { | |
8bb44445 | 144 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
558f8740 GL |
145 | #interrupt-cells = <2>; |
146 | interrupt-controller; | |
147 | reg = <0xe690000c 4>, | |
148 | <0xe690001c 4>, | |
149 | <0xe690002c 1>, | |
150 | <0xe690004c 1>, | |
151 | <0xe690006c 1>; | |
5f75e73c LP |
152 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH |
153 | 0 26 IRQ_TYPE_LEVEL_HIGH | |
154 | 0 27 IRQ_TYPE_LEVEL_HIGH | |
155 | 0 28 IRQ_TYPE_LEVEL_HIGH | |
156 | 0 29 IRQ_TYPE_LEVEL_HIGH | |
157 | 0 30 IRQ_TYPE_LEVEL_HIGH | |
158 | 0 31 IRQ_TYPE_LEVEL_HIGH | |
159 | 0 32 IRQ_TYPE_LEVEL_HIGH>; | |
56a215d6 | 160 | clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; |
48bdf06d | 161 | control-parent; |
558f8740 GL |
162 | }; |
163 | ||
561a1a31 | 164 | i2c0: i2c@e6820000 { |
48609533 SH |
165 | #address-cells = <1>; |
166 | #size-cells = <0>; | |
dd4dc874 | 167 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 168 | reg = <0xe6820000 0x425>; |
5f75e73c LP |
169 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH |
170 | 0 168 IRQ_TYPE_LEVEL_HIGH | |
171 | 0 169 IRQ_TYPE_LEVEL_HIGH | |
172 | 0 170 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 173 | clocks = <&mstp1_clks SH73A0_CLK_IIC0>; |
eda3a4fa | 174 | status = "disabled"; |
48609533 SH |
175 | }; |
176 | ||
561a1a31 | 177 | i2c1: i2c@e6822000 { |
48609533 SH |
178 | #address-cells = <1>; |
179 | #size-cells = <0>; | |
dd4dc874 | 180 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 181 | reg = <0xe6822000 0x425>; |
5f75e73c LP |
182 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH |
183 | 0 52 IRQ_TYPE_LEVEL_HIGH | |
184 | 0 53 IRQ_TYPE_LEVEL_HIGH | |
185 | 0 54 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 186 | clocks = <&mstp3_clks SH73A0_CLK_IIC1>; |
eda3a4fa | 187 | status = "disabled"; |
48609533 SH |
188 | }; |
189 | ||
561a1a31 | 190 | i2c2: i2c@e6824000 { |
48609533 SH |
191 | #address-cells = <1>; |
192 | #size-cells = <0>; | |
dd4dc874 | 193 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 194 | reg = <0xe6824000 0x425>; |
5f75e73c LP |
195 | interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH |
196 | 0 172 IRQ_TYPE_LEVEL_HIGH | |
197 | 0 173 IRQ_TYPE_LEVEL_HIGH | |
198 | 0 174 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 199 | clocks = <&mstp0_clks SH73A0_CLK_IIC2>; |
eda3a4fa | 200 | status = "disabled"; |
48609533 SH |
201 | }; |
202 | ||
561a1a31 | 203 | i2c3: i2c@e6826000 { |
48609533 SH |
204 | #address-cells = <1>; |
205 | #size-cells = <0>; | |
dd4dc874 | 206 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 207 | reg = <0xe6826000 0x425>; |
5f75e73c LP |
208 | interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH |
209 | 0 184 IRQ_TYPE_LEVEL_HIGH | |
210 | 0 185 IRQ_TYPE_LEVEL_HIGH | |
211 | 0 186 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 212 | clocks = <&mstp4_clks SH73A0_CLK_IIC3>; |
eda3a4fa | 213 | status = "disabled"; |
48609533 SH |
214 | }; |
215 | ||
561a1a31 | 216 | i2c4: i2c@e6828000 { |
48609533 SH |
217 | #address-cells = <1>; |
218 | #size-cells = <0>; | |
dd4dc874 | 219 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
48609533 | 220 | reg = <0xe6828000 0x425>; |
5f75e73c LP |
221 | interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH |
222 | 0 188 IRQ_TYPE_LEVEL_HIGH | |
223 | 0 189 IRQ_TYPE_LEVEL_HIGH | |
224 | 0 190 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 225 | clocks = <&mstp4_clks SH73A0_CLK_IIC4>; |
eda3a4fa | 226 | status = "disabled"; |
48609533 | 227 | }; |
546e5d3e | 228 | |
33f6be3b | 229 | mmcif: mmc@e6bd0000 { |
546e5d3e GL |
230 | compatible = "renesas,sh-mmcif"; |
231 | reg = <0xe6bd0000 0x100>; | |
5f75e73c LP |
232 | interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH |
233 | 0 141 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 234 | clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; |
546e5d3e GL |
235 | reg-io-width = <4>; |
236 | status = "disabled"; | |
237 | }; | |
238 | ||
33f6be3b | 239 | sdhi0: sd@ee100000 { |
e8a8b8a3 | 240 | compatible = "renesas,sdhi-sh73a0"; |
546e5d3e | 241 | reg = <0xee100000 0x100>; |
5f75e73c LP |
242 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH |
243 | 0 84 IRQ_TYPE_LEVEL_HIGH | |
244 | 0 85 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 245 | clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; |
a463f731 | 246 | cap-sd-highspeed; |
546e5d3e GL |
247 | status = "disabled"; |
248 | }; | |
249 | ||
250 | /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ | |
33f6be3b | 251 | sdhi1: sd@ee120000 { |
e8a8b8a3 | 252 | compatible = "renesas,sdhi-sh73a0"; |
546e5d3e | 253 | reg = <0xee120000 0x100>; |
5f75e73c LP |
254 | interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH |
255 | 0 89 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 256 | clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; |
546e5d3e | 257 | toshiba,mmc-wrprotect-disable; |
a463f731 | 258 | cap-sd-highspeed; |
546e5d3e GL |
259 | status = "disabled"; |
260 | }; | |
261 | ||
33f6be3b | 262 | sdhi2: sd@ee140000 { |
e8a8b8a3 | 263 | compatible = "renesas,sdhi-sh73a0"; |
546e5d3e | 264 | reg = <0xee140000 0x100>; |
5f75e73c LP |
265 | interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH |
266 | 0 105 IRQ_TYPE_LEVEL_HIGH>; | |
f73e1e28 | 267 | clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; |
546e5d3e | 268 | toshiba,mmc-wrprotect-disable; |
a463f731 | 269 | cap-sd-highspeed; |
546e5d3e GL |
270 | status = "disabled"; |
271 | }; | |
3f59007e | 272 | |
2131421b SH |
273 | scifa0: serial@e6c40000 { |
274 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
275 | reg = <0xe6c40000 0x100>; | |
2131421b | 276 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
277 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; |
278 | clock-names = "sci_ick"; | |
2131421b SH |
279 | status = "disabled"; |
280 | }; | |
281 | ||
282 | scifa1: serial@e6c50000 { | |
283 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
284 | reg = <0xe6c50000 0x100>; | |
2131421b | 285 | interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
286 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; |
287 | clock-names = "sci_ick"; | |
2131421b SH |
288 | status = "disabled"; |
289 | }; | |
290 | ||
291 | scifa2: serial@e6c60000 { | |
292 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
293 | reg = <0xe6c60000 0x100>; | |
2131421b | 294 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
295 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; |
296 | clock-names = "sci_ick"; | |
2131421b SH |
297 | status = "disabled"; |
298 | }; | |
299 | ||
300 | scifa3: serial@e6c70000 { | |
301 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
302 | reg = <0xe6c70000 0x100>; | |
2131421b | 303 | interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
304 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; |
305 | clock-names = "sci_ick"; | |
2131421b SH |
306 | status = "disabled"; |
307 | }; | |
308 | ||
309 | scifa4: serial@e6c80000 { | |
310 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
311 | reg = <0xe6c80000 0x100>; | |
2131421b | 312 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
313 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; |
314 | clock-names = "sci_ick"; | |
2131421b SH |
315 | status = "disabled"; |
316 | }; | |
317 | ||
318 | scifa5: serial@e6cb0000 { | |
319 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
320 | reg = <0xe6cb0000 0x100>; | |
2131421b | 321 | interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
322 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; |
323 | clock-names = "sci_ick"; | |
2131421b SH |
324 | status = "disabled"; |
325 | }; | |
326 | ||
327 | scifa6: serial@e6cc0000 { | |
328 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
329 | reg = <0xe6cc0000 0x100>; | |
2131421b | 330 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
331 | clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; |
332 | clock-names = "sci_ick"; | |
2131421b SH |
333 | status = "disabled"; |
334 | }; | |
335 | ||
336 | scifa7: serial@e6cd0000 { | |
337 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
338 | reg = <0xe6cd0000 0x100>; | |
2131421b | 339 | interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
340 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; |
341 | clock-names = "sci_ick"; | |
2131421b SH |
342 | status = "disabled"; |
343 | }; | |
344 | ||
345 | scifb8: serial@e6c30000 { | |
346 | compatible = "renesas,scifb-sh73a0", "renesas,scifb"; | |
347 | reg = <0xe6c30000 0x100>; | |
2131421b | 348 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
f73e1e28 UH |
349 | clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; |
350 | clock-names = "sci_ick"; | |
2131421b SH |
351 | status = "disabled"; |
352 | }; | |
353 | ||
3f59007e LP |
354 | pfc: pfc@e6050000 { |
355 | compatible = "renesas,pfc-sh73a0"; | |
356 | reg = <0xe6050000 0x8000>, | |
357 | <0xe605801c 0x1c>; | |
358 | gpio-controller; | |
359 | #gpio-cells = <2>; | |
aba76d28 LP |
360 | interrupts-extended = |
361 | <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, | |
362 | <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, | |
363 | <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, | |
364 | <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, | |
365 | <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, | |
366 | <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, | |
367 | <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, | |
368 | <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; | |
3f59007e | 369 | }; |
63b1303d KM |
370 | |
371 | sh_fsi2: sound@ec230000 { | |
372 | #sound-dai-cells = <1>; | |
f76452fd | 373 | compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; |
63b1303d | 374 | reg = <0xec230000 0x400>; |
63b1303d KM |
375 | interrupts = <0 146 0x4>; |
376 | status = "disabled"; | |
377 | }; | |
00df6113 | 378 | |
217b6e65 GU |
379 | bsc: bus@fec10000 { |
380 | compatible = "renesas,bsc-sh73a0", "renesas,bsc", | |
381 | "simple-pm-bus"; | |
382 | #address-cells = <1>; | |
383 | #size-cells = <1>; | |
384 | ranges = <0 0 0x20000000>; | |
385 | reg = <0xfec10000 0x400>; | |
386 | interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; | |
387 | clocks = <&zb_clk>; | |
388 | }; | |
389 | ||
00df6113 UH |
390 | clocks { |
391 | #address-cells = <1>; | |
392 | #size-cells = <1>; | |
393 | ranges; | |
394 | ||
395 | /* External root clocks */ | |
396 | extalr_clk: extalr_clk { | |
397 | compatible = "fixed-clock"; | |
398 | #clock-cells = <0>; | |
399 | clock-frequency = <32768>; | |
400 | clock-output-names = "extalr"; | |
401 | }; | |
402 | extal1_clk: extal1_clk { | |
403 | compatible = "fixed-clock"; | |
404 | #clock-cells = <0>; | |
405 | clock-frequency = <26000000>; | |
406 | clock-output-names = "extal1"; | |
407 | }; | |
408 | extal2_clk: extal2_clk { | |
409 | compatible = "fixed-clock"; | |
410 | #clock-cells = <0>; | |
411 | clock-output-names = "extal2"; | |
412 | }; | |
413 | extcki_clk: extcki_clk { | |
414 | compatible = "fixed-clock"; | |
415 | #clock-cells = <0>; | |
416 | clock-output-names = "extcki"; | |
417 | }; | |
418 | fsiack_clk: fsiack_clk { | |
419 | compatible = "fixed-clock"; | |
420 | #clock-cells = <0>; | |
421 | clock-frequency = <0>; | |
422 | clock-output-names = "fsiack"; | |
423 | }; | |
424 | fsibck_clk: fsibck_clk { | |
425 | compatible = "fixed-clock"; | |
426 | #clock-cells = <0>; | |
427 | clock-frequency = <0>; | |
428 | clock-output-names = "fsibck"; | |
429 | }; | |
430 | ||
431 | /* Special CPG clocks */ | |
432 | cpg_clocks: cpg_clocks@e6150000 { | |
433 | compatible = "renesas,sh73a0-cpg-clocks"; | |
434 | reg = <0xe6150000 0x10000>; | |
435 | clocks = <&extal1_clk>, <&extal2_clk>; | |
436 | #clock-cells = <1>; | |
437 | clock-output-names = "main", "pll0", "pll1", "pll2", | |
438 | "pll3", "dsi0phy", "dsi1phy", | |
439 | "zg", "m3", "b", "m1", "m2", | |
440 | "z", "zx", "hp"; | |
441 | }; | |
442 | ||
443 | /* Variable factor clocks (DIV6) */ | |
444 | vclk1_clk: vclk1_clk@e6150008 { | |
445 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
446 | reg = <0xe6150008 4>; | |
09940bf0 UH |
447 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
448 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, | |
449 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, | |
450 | <0>; | |
00df6113 UH |
451 | #clock-cells = <0>; |
452 | clock-output-names = "vclk1"; | |
453 | }; | |
454 | vclk2_clk: vclk2_clk@e615000c { | |
455 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
456 | reg = <0xe615000c 4>; | |
09940bf0 UH |
457 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
458 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, | |
459 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, | |
460 | <0>; | |
00df6113 UH |
461 | #clock-cells = <0>; |
462 | clock-output-names = "vclk2"; | |
463 | }; | |
464 | vclk3_clk: vclk3_clk@e615001c { | |
465 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
466 | reg = <0xe615001c 4>; | |
09940bf0 UH |
467 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
468 | <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>, | |
469 | <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>, | |
470 | <0>; | |
00df6113 UH |
471 | #clock-cells = <0>; |
472 | clock-output-names = "vclk3"; | |
473 | }; | |
474 | zb_clk: zb_clk@e6150010 { | |
475 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
476 | reg = <0xe6150010 4>; | |
09940bf0 UH |
477 | clocks = <&pll1_div2_clk>, <0>, |
478 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
479 | #clock-cells = <0>; |
480 | clock-output-names = "zb"; | |
481 | }; | |
482 | flctl_clk: flctl_clk@e6150014 { | |
483 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
484 | reg = <0xe6150014 4>; | |
09940bf0 UH |
485 | clocks = <&pll1_div2_clk>, <0>, |
486 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
487 | #clock-cells = <0>; |
488 | clock-output-names = "flctlck"; | |
489 | }; | |
490 | sdhi0_clk: sdhi0_clk@e6150074 { | |
491 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
492 | reg = <0xe6150074 4>; | |
09940bf0 UH |
493 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
494 | <&pll1_div13_clk>, <0>; | |
00df6113 UH |
495 | #clock-cells = <0>; |
496 | clock-output-names = "sdhi0ck"; | |
497 | }; | |
498 | sdhi1_clk: sdhi1_clk@e6150078 { | |
499 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
500 | reg = <0xe6150078 4>; | |
09940bf0 UH |
501 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
502 | <&pll1_div13_clk>, <0>; | |
00df6113 UH |
503 | #clock-cells = <0>; |
504 | clock-output-names = "sdhi1ck"; | |
505 | }; | |
506 | sdhi2_clk: sdhi2_clk@e615007c { | |
507 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
508 | reg = <0xe615007c 4>; | |
09940bf0 UH |
509 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
510 | <&pll1_div13_clk>, <0>; | |
00df6113 UH |
511 | #clock-cells = <0>; |
512 | clock-output-names = "sdhi2ck"; | |
513 | }; | |
514 | fsia_clk: fsia_clk@e6150018 { | |
515 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
516 | reg = <0xe6150018 4>; | |
09940bf0 UH |
517 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
518 | <&fsiack_clk>, <&fsiack_clk>; | |
00df6113 UH |
519 | #clock-cells = <0>; |
520 | clock-output-names = "fsia"; | |
521 | }; | |
522 | fsib_clk: fsib_clk@e6150090 { | |
523 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
524 | reg = <0xe6150090 4>; | |
09940bf0 UH |
525 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
526 | <&fsibck_clk>, <&fsibck_clk>; | |
00df6113 UH |
527 | #clock-cells = <0>; |
528 | clock-output-names = "fsib"; | |
529 | }; | |
530 | sub_clk: sub_clk@e6150080 { | |
531 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
532 | reg = <0xe6150080 4>; | |
09940bf0 UH |
533 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
534 | <&extal2_clk>, <&extal2_clk>; | |
00df6113 UH |
535 | #clock-cells = <0>; |
536 | clock-output-names = "sub"; | |
537 | }; | |
538 | spua_clk: spua_clk@e6150084 { | |
539 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
540 | reg = <0xe6150084 4>; | |
09940bf0 UH |
541 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
542 | <&extal2_clk>, <&extal2_clk>; | |
00df6113 UH |
543 | #clock-cells = <0>; |
544 | clock-output-names = "spua"; | |
545 | }; | |
546 | spuv_clk: spuv_clk@e6150094 { | |
547 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
548 | reg = <0xe6150094 4>; | |
09940bf0 UH |
549 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
550 | <&extal2_clk>, <&extal2_clk>; | |
00df6113 UH |
551 | #clock-cells = <0>; |
552 | clock-output-names = "spuv"; | |
553 | }; | |
554 | msu_clk: msu_clk@e6150088 { | |
555 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
556 | reg = <0xe6150088 4>; | |
09940bf0 UH |
557 | clocks = <&pll1_div2_clk>, <0>, |
558 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
559 | #clock-cells = <0>; |
560 | clock-output-names = "msu"; | |
561 | }; | |
562 | hsi_clk: hsi_clk@e615008c { | |
563 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
564 | reg = <0xe615008c 4>; | |
09940bf0 UH |
565 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
566 | <&pll1_div7_clk>, <0>; | |
00df6113 UH |
567 | #clock-cells = <0>; |
568 | clock-output-names = "hsi"; | |
569 | }; | |
570 | mfg1_clk: mfg1_clk@e6150098 { | |
571 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
572 | reg = <0xe6150098 4>; | |
09940bf0 UH |
573 | clocks = <&pll1_div2_clk>, <0>, |
574 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
575 | #clock-cells = <0>; |
576 | clock-output-names = "mfg1"; | |
577 | }; | |
578 | mfg2_clk: mfg2_clk@e615009c { | |
579 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
580 | reg = <0xe615009c 4>; | |
09940bf0 UH |
581 | clocks = <&pll1_div2_clk>, <0>, |
582 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
583 | #clock-cells = <0>; |
584 | clock-output-names = "mfg2"; | |
585 | }; | |
586 | dsit_clk: dsit_clk@e6150060 { | |
587 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
588 | reg = <0xe6150060 4>; | |
09940bf0 UH |
589 | clocks = <&pll1_div2_clk>, <0>, |
590 | <&cpg_clocks SH73A0_CLK_PLL2>, <0>; | |
00df6113 UH |
591 | #clock-cells = <0>; |
592 | clock-output-names = "dsit"; | |
593 | }; | |
594 | dsi0p_clk: dsi0p_clk@e6150064 { | |
595 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
596 | reg = <0xe6150064 4>; | |
09940bf0 UH |
597 | clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>, |
598 | <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>, | |
599 | <&extcki_clk>, <0>, <0>, <0>; | |
00df6113 UH |
600 | #clock-cells = <0>; |
601 | clock-output-names = "dsi0pck"; | |
602 | }; | |
603 | ||
604 | /* Fixed factor clocks */ | |
605 | main_div2_clk: main_div2_clk { | |
606 | compatible = "fixed-factor-clock"; | |
607 | clocks = <&cpg_clocks SH73A0_CLK_MAIN>; | |
608 | #clock-cells = <0>; | |
609 | clock-div = <2>; | |
610 | clock-mult = <1>; | |
611 | clock-output-names = "main_div2"; | |
612 | }; | |
613 | pll1_div2_clk: pll1_div2_clk { | |
614 | compatible = "fixed-factor-clock"; | |
615 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
616 | #clock-cells = <0>; | |
617 | clock-div = <2>; | |
618 | clock-mult = <1>; | |
619 | clock-output-names = "pll1_div2"; | |
620 | }; | |
621 | pll1_div7_clk: pll1_div7_clk { | |
622 | compatible = "fixed-factor-clock"; | |
623 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
624 | #clock-cells = <0>; | |
625 | clock-div = <7>; | |
626 | clock-mult = <1>; | |
627 | clock-output-names = "pll1_div7"; | |
628 | }; | |
629 | pll1_div13_clk: pll1_div13_clk { | |
630 | compatible = "fixed-factor-clock"; | |
631 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
632 | #clock-cells = <0>; | |
633 | clock-div = <13>; | |
634 | clock-mult = <1>; | |
635 | clock-output-names = "pll1_div13"; | |
636 | }; | |
637 | twd_clk: twd_clk { | |
638 | compatible = "fixed-factor-clock"; | |
639 | clocks = <&cpg_clocks SH73A0_CLK_Z>; | |
640 | #clock-cells = <0>; | |
641 | clock-div = <4>; | |
642 | clock-mult = <1>; | |
643 | clock-output-names = "twd"; | |
644 | }; | |
645 | ||
646 | /* Gate clocks */ | |
647 | mstp0_clks: mstp0_clks@e6150130 { | |
648 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
649 | reg = <0xe6150130 4>, <0xe6150030 4>; | |
650 | clocks = <&cpg_clocks SH73A0_CLK_HP>; | |
651 | #clock-cells = <1>; | |
652 | clock-indices = < | |
653 | SH73A0_CLK_IIC2 | |
654 | >; | |
655 | clock-output-names = | |
656 | "iic2"; | |
657 | }; | |
658 | mstp1_clks: mstp1_clks@e6150134 { | |
659 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
660 | reg = <0xe6150134 4>, <0xe6150038 4>; | |
661 | clocks = <&cpg_clocks SH73A0_CLK_B>, | |
662 | <&cpg_clocks SH73A0_CLK_B>, | |
663 | <&cpg_clocks SH73A0_CLK_B>, | |
664 | <&cpg_clocks SH73A0_CLK_B>, | |
665 | <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, | |
666 | <&cpg_clocks SH73A0_CLK_HP>, | |
667 | <&cpg_clocks SH73A0_CLK_ZG>, | |
668 | <&cpg_clocks SH73A0_CLK_B>; | |
669 | #clock-cells = <1>; | |
670 | clock-indices = < | |
671 | SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 | |
672 | SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 | |
673 | SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 | |
674 | SH73A0_CLK_IIC0 SH73A0_CLK_SGX | |
675 | SH73A0_CLK_LCDC0 | |
676 | >; | |
677 | clock-output-names = | |
678 | "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", | |
679 | "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; | |
680 | }; | |
681 | mstp2_clks: mstp2_clks@e6150138 { | |
682 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
683 | reg = <0xe6150138 4>, <0xe6150040 4>; | |
684 | clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, | |
685 | <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, | |
686 | <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
687 | <&sub_clk>, <&sub_clk>; | |
688 | #clock-cells = <1>; | |
689 | clock-indices = < | |
690 | SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC | |
691 | SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5 | |
692 | SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0 | |
693 | SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2 | |
694 | SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4 | |
695 | >; | |
696 | clock-output-names = | |
697 | "scifa7", "sy_dmac", "mp_dmac", "scifa5", | |
698 | "scifb", "scifa0", "scifa1", "scifa2", | |
699 | "scifa3", "scifa4"; | |
700 | }; | |
701 | mstp3_clks: mstp3_clks@e615013c { | |
702 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
703 | reg = <0xe615013c 4>, <0xe6150048 4>; | |
704 | clocks = <&sub_clk>, <&extalr_clk>, | |
705 | <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, | |
706 | <&cpg_clocks SH73A0_CLK_HP>, | |
707 | <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, | |
708 | <&sdhi0_clk>, <&sdhi1_clk>, | |
709 | <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, | |
710 | <&main_div2_clk>, <&main_div2_clk>, | |
711 | <&main_div2_clk>, <&main_div2_clk>, | |
712 | <&main_div2_clk>; | |
713 | #clock-cells = <1>; | |
714 | clock-indices = < | |
715 | SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 | |
716 | SH73A0_CLK_FSI SH73A0_CLK_IRDA | |
717 | SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL | |
718 | SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 | |
719 | SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 | |
720 | SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 | |
721 | SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 | |
722 | SH73A0_CLK_TPU4 | |
723 | >; | |
724 | clock-output-names = | |
725 | "scifa6", "cmt1", "fsi", "irda", "iic1", | |
726 | "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", | |
727 | "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; | |
728 | }; | |
729 | mstp4_clks: mstp4_clks@e6150140 { | |
730 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
731 | reg = <0xe6150140 4>, <0xe615004c 4>; | |
732 | clocks = <&cpg_clocks SH73A0_CLK_HP>, | |
733 | <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; | |
734 | #clock-cells = <1>; | |
735 | clock-indices = < | |
736 | SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 | |
737 | SH73A0_CLK_KEYSC | |
738 | >; | |
739 | clock-output-names = | |
740 | "iic3", "iic4", "keysc"; | |
741 | }; | |
56a215d6 GU |
742 | mstp5_clks: mstp5_clks@e6150144 { |
743 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
744 | reg = <0xe6150144 4>, <0xe615003c 4>; | |
745 | clocks = <&cpg_clocks SH73A0_CLK_HP>; | |
746 | #clock-cells = <1>; | |
747 | clock-indices = < | |
748 | SH73A0_CLK_INTCA0 | |
749 | >; | |
750 | clock-output-names = | |
751 | "intca0"; | |
752 | }; | |
00df6113 | 753 | }; |
a3f22db5 | 754 | }; |