projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| a3f22db5 SH |
1 | /* |
| 2 | * Device Tree Source for the SH73A0 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Renesas Solutions Corp. | |
| 5 | * | |
| 6 | * This file is licensed under the terms of the GNU General Public License | |
| 7 | * version 2. This program is licensed "as is" without any warranty of any | |
| 8 | * kind, whether express or implied. | |
| 9 | */ | |
| 10 | ||
| 11 | /include/ "skeleton.dtsi" | |
| 12 | ||
| 00df6113 | 13 | #include <dt-bindings/clock/sh73a0-clock.h> |
| 5f75e73c LP |
14 | #include <dt-bindings/interrupt-controller/irq.h> |
| 15 | ||
| a3f22db5 SH |
16 | / { |
| 17 | compatible = "renesas,sh73a0"; | |
| f170b97c | 18 | interrupt-parent = <&gic>; |
| a3f22db5 SH |
19 | |
| 20 | cpus { | |
| c5795aec SH |
21 | #address-cells = <1>; |
| 22 | #size-cells = <0>; | |
| 23 | ||
| a3f22db5 | 24 | cpu@0 { |
| c5795aec | 25 | device_type = "cpu"; |
| a3f22db5 | 26 | compatible = "arm,cortex-a9"; |
| c5795aec | 27 | reg = <0>; |
| 13bd825b | 28 | clock-frequency = <1196000000>; |
| a3f22db5 SH |
29 | }; |
| 30 | cpu@1 { | |
| c5795aec | 31 | device_type = "cpu"; |
| a3f22db5 | 32 | compatible = "arm,cortex-a9"; |
| c5795aec | 33 | reg = <1>; |
| 13bd825b | 34 | clock-frequency = <1196000000>; |
| a3f22db5 SH |
35 | }; |
| 36 | }; | |
| 37 | ||
| 38 | gic: interrupt-controller@f0001000 { | |
| 39 | compatible = "arm,cortex-a9-gic"; | |
| 40 | #interrupt-cells = <3>; | |
| a3f22db5 SH |
41 | interrupt-controller; |
| 42 | reg = <0xf0001000 0x1000>, | |
| 43 | <0xf0000100 0x100>; | |
| 44 | }; | |
| 48609533 | 45 | |
| 29828c87 GU |
46 | sbsc2: memory-controller@fb400000 { |
| 47 | compatible = "renesas,sbsc-sh73a0"; | |
| 48 | reg = <0xfb400000 0x400>; | |
| 49 | interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, | |
| 50 | <0 38 IRQ_TYPE_LEVEL_HIGH>; | |
| 51 | interrupt-names = "sec", "temp"; | |
| 52 | }; | |
| 53 | ||
| 54 | sbsc1: memory-controller@fe400000 { | |
| 55 | compatible = "renesas,sbsc-sh73a0"; | |
| 56 | reg = <0xfe400000 0x400>; | |
| 57 | interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, | |
| 58 | <0 36 IRQ_TYPE_LEVEL_HIGH>; | |
| 59 | interrupt-names = "sec", "temp"; | |
| 60 | }; | |
| 61 | ||
| 4c90483a MD |
62 | pmu { |
| 63 | compatible = "arm,cortex-a9-pmu"; | |
| 5f75e73c LP |
64 | interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>, |
| 65 | <0 56 IRQ_TYPE_LEVEL_HIGH>; | |
| 4c90483a MD |
66 | }; |
| 67 | ||
| 6a5336a7 UH |
68 | cmt1: timer@e6138000 { |
| 69 | compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; | |
| 70 | reg = <0xe6138000 0x200>; | |
| 71 | interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; | |
| 72 | ||
| 73 | renesas,channels-mask = <0x3f>; | |
| 74 | ||
| f73e1e28 UH |
75 | clocks = <&mstp3_clks SH73A0_CLK_CMT1>; |
| 76 | clock-names = "fck"; | |
| 6a5336a7 UH |
77 | status = "disabled"; |
| 78 | }; | |
| 79 | ||
| 558f8740 | 80 | irqpin0: irqpin@e6900000 { |
| 8bb44445 | 81 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
| 558f8740 GL |
82 | #interrupt-cells = <2>; |
| 83 | interrupt-controller; | |
| 84 | reg = <0xe6900000 4>, | |
| 85 | <0xe6900010 4>, | |
| 86 | <0xe6900020 1>, | |
| 87 | <0xe6900040 1>, | |
| 88 | <0xe6900060 1>; | |
| 5f75e73c LP |
89 | interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH |
| 90 | 0 2 IRQ_TYPE_LEVEL_HIGH | |
| 91 | 0 3 IRQ_TYPE_LEVEL_HIGH | |
| 92 | 0 4 IRQ_TYPE_LEVEL_HIGH | |
| 93 | 0 5 IRQ_TYPE_LEVEL_HIGH | |
| 94 | 0 6 IRQ_TYPE_LEVEL_HIGH | |
| 95 | 0 7 IRQ_TYPE_LEVEL_HIGH | |
| 96 | 0 8 IRQ_TYPE_LEVEL_HIGH>; | |
| 48bdf06d | 97 | control-parent; |
| 558f8740 GL |
98 | }; |
| 99 | ||
| 100 | irqpin1: irqpin@e6900004 { | |
| 8bb44445 | 101 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
| 558f8740 GL |
102 | #interrupt-cells = <2>; |
| 103 | interrupt-controller; | |
| 104 | reg = <0xe6900004 4>, | |
| 105 | <0xe6900014 4>, | |
| 106 | <0xe6900024 1>, | |
| 107 | <0xe6900044 1>, | |
| 108 | <0xe6900064 1>; | |
| 5f75e73c LP |
109 | interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH |
| 110 | 0 10 IRQ_TYPE_LEVEL_HIGH | |
| 111 | 0 11 IRQ_TYPE_LEVEL_HIGH | |
| 112 | 0 12 IRQ_TYPE_LEVEL_HIGH | |
| 113 | 0 13 IRQ_TYPE_LEVEL_HIGH | |
| 114 | 0 14 IRQ_TYPE_LEVEL_HIGH | |
| 115 | 0 15 IRQ_TYPE_LEVEL_HIGH | |
| 116 | 0 16 IRQ_TYPE_LEVEL_HIGH>; | |
| 558f8740 GL |
117 | control-parent; |
| 118 | }; | |
| 119 | ||
| 120 | irqpin2: irqpin@e6900008 { | |
| 8bb44445 | 121 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
| 558f8740 GL |
122 | #interrupt-cells = <2>; |
| 123 | interrupt-controller; | |
| 124 | reg = <0xe6900008 4>, | |
| 125 | <0xe6900018 4>, | |
| 126 | <0xe6900028 1>, | |
| 127 | <0xe6900048 1>, | |
| 128 | <0xe6900068 1>; | |
| 5f75e73c LP |
129 | interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH |
| 130 | 0 18 IRQ_TYPE_LEVEL_HIGH | |
| 131 | 0 19 IRQ_TYPE_LEVEL_HIGH | |
| 132 | 0 20 IRQ_TYPE_LEVEL_HIGH | |
| 133 | 0 21 IRQ_TYPE_LEVEL_HIGH | |
| 134 | 0 22 IRQ_TYPE_LEVEL_HIGH | |
| 135 | 0 23 IRQ_TYPE_LEVEL_HIGH | |
| 136 | 0 24 IRQ_TYPE_LEVEL_HIGH>; | |
| 48bdf06d | 137 | control-parent; |
| 558f8740 GL |
138 | }; |
| 139 | ||
| 140 | irqpin3: irqpin@e690000c { | |
| 8bb44445 | 141 | compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin"; |
| 558f8740 GL |
142 | #interrupt-cells = <2>; |
| 143 | interrupt-controller; | |
| 144 | reg = <0xe690000c 4>, | |
| 145 | <0xe690001c 4>, | |
| 146 | <0xe690002c 1>, | |
| 147 | <0xe690004c 1>, | |
| 148 | <0xe690006c 1>; | |
| 5f75e73c LP |
149 | interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH |
| 150 | 0 26 IRQ_TYPE_LEVEL_HIGH | |
| 151 | 0 27 IRQ_TYPE_LEVEL_HIGH | |
| 152 | 0 28 IRQ_TYPE_LEVEL_HIGH | |
| 153 | 0 29 IRQ_TYPE_LEVEL_HIGH | |
| 154 | 0 30 IRQ_TYPE_LEVEL_HIGH | |
| 155 | 0 31 IRQ_TYPE_LEVEL_HIGH | |
| 156 | 0 32 IRQ_TYPE_LEVEL_HIGH>; | |
| 48bdf06d | 157 | control-parent; |
| 558f8740 GL |
158 | }; |
| 159 | ||
| 561a1a31 | 160 | i2c0: i2c@e6820000 { |
| 48609533 SH |
161 | #address-cells = <1>; |
| 162 | #size-cells = <0>; | |
| dd4dc874 | 163 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
| 48609533 | 164 | reg = <0xe6820000 0x425>; |
| 5f75e73c LP |
165 | interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH |
| 166 | 0 168 IRQ_TYPE_LEVEL_HIGH | |
| 167 | 0 169 IRQ_TYPE_LEVEL_HIGH | |
| 168 | 0 170 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 169 | clocks = <&mstp1_clks SH73A0_CLK_IIC0>; |
| eda3a4fa | 170 | status = "disabled"; |
| 48609533 SH |
171 | }; |
| 172 | ||
| 561a1a31 | 173 | i2c1: i2c@e6822000 { |
| 48609533 SH |
174 | #address-cells = <1>; |
| 175 | #size-cells = <0>; | |
| dd4dc874 | 176 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
| 48609533 | 177 | reg = <0xe6822000 0x425>; |
| 5f75e73c LP |
178 | interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH |
| 179 | 0 52 IRQ_TYPE_LEVEL_HIGH | |
| 180 | 0 53 IRQ_TYPE_LEVEL_HIGH | |
| 181 | 0 54 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 182 | clocks = <&mstp3_clks SH73A0_CLK_IIC1>; |
| eda3a4fa | 183 | status = "disabled"; |
| 48609533 SH |
184 | }; |
| 185 | ||
| 561a1a31 | 186 | i2c2: i2c@e6824000 { |
| 48609533 SH |
187 | #address-cells = <1>; |
| 188 | #size-cells = <0>; | |
| dd4dc874 | 189 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
| 48609533 | 190 | reg = <0xe6824000 0x425>; |
| 5f75e73c LP |
191 | interrupts = <0 171 IRQ_TYPE_LEVEL_HIGH |
| 192 | 0 172 IRQ_TYPE_LEVEL_HIGH | |
| 193 | 0 173 IRQ_TYPE_LEVEL_HIGH | |
| 194 | 0 174 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 195 | clocks = <&mstp0_clks SH73A0_CLK_IIC2>; |
| eda3a4fa | 196 | status = "disabled"; |
| 48609533 SH |
197 | }; |
| 198 | ||
| 561a1a31 | 199 | i2c3: i2c@e6826000 { |
| 48609533 SH |
200 | #address-cells = <1>; |
| 201 | #size-cells = <0>; | |
| dd4dc874 | 202 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
| 48609533 | 203 | reg = <0xe6826000 0x425>; |
| 5f75e73c LP |
204 | interrupts = <0 183 IRQ_TYPE_LEVEL_HIGH |
| 205 | 0 184 IRQ_TYPE_LEVEL_HIGH | |
| 206 | 0 185 IRQ_TYPE_LEVEL_HIGH | |
| 207 | 0 186 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 208 | clocks = <&mstp4_clks SH73A0_CLK_IIC3>; |
| eda3a4fa | 209 | status = "disabled"; |
| 48609533 SH |
210 | }; |
| 211 | ||
| 561a1a31 | 212 | i2c4: i2c@e6828000 { |
| 48609533 SH |
213 | #address-cells = <1>; |
| 214 | #size-cells = <0>; | |
| dd4dc874 | 215 | compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic"; |
| 48609533 | 216 | reg = <0xe6828000 0x425>; |
| 5f75e73c LP |
217 | interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH |
| 218 | 0 188 IRQ_TYPE_LEVEL_HIGH | |
| 219 | 0 189 IRQ_TYPE_LEVEL_HIGH | |
| 220 | 0 190 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 221 | clocks = <&mstp4_clks SH73A0_CLK_IIC4>; |
| eda3a4fa | 222 | status = "disabled"; |
| 48609533 | 223 | }; |
| 546e5d3e | 224 | |
| 33f6be3b | 225 | mmcif: mmc@e6bd0000 { |
| 546e5d3e GL |
226 | compatible = "renesas,sh-mmcif"; |
| 227 | reg = <0xe6bd0000 0x100>; | |
| 5f75e73c LP |
228 | interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH |
| 229 | 0 141 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 230 | clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; |
| 546e5d3e GL |
231 | reg-io-width = <4>; |
| 232 | status = "disabled"; | |
| 233 | }; | |
| 234 | ||
| 33f6be3b | 235 | sdhi0: sd@ee100000 { |
| e8a8b8a3 | 236 | compatible = "renesas,sdhi-sh73a0"; |
| 546e5d3e | 237 | reg = <0xee100000 0x100>; |
| 5f75e73c LP |
238 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH |
| 239 | 0 84 IRQ_TYPE_LEVEL_HIGH | |
| 240 | 0 85 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 241 | clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; |
| a463f731 | 242 | cap-sd-highspeed; |
| 546e5d3e GL |
243 | status = "disabled"; |
| 244 | }; | |
| 245 | ||
| 246 | /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */ | |
| 33f6be3b | 247 | sdhi1: sd@ee120000 { |
| e8a8b8a3 | 248 | compatible = "renesas,sdhi-sh73a0"; |
| 546e5d3e | 249 | reg = <0xee120000 0x100>; |
| 5f75e73c LP |
250 | interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH |
| 251 | 0 89 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 252 | clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; |
| 546e5d3e | 253 | toshiba,mmc-wrprotect-disable; |
| a463f731 | 254 | cap-sd-highspeed; |
| 546e5d3e GL |
255 | status = "disabled"; |
| 256 | }; | |
| 257 | ||
| 33f6be3b | 258 | sdhi2: sd@ee140000 { |
| e8a8b8a3 | 259 | compatible = "renesas,sdhi-sh73a0"; |
| 546e5d3e | 260 | reg = <0xee140000 0x100>; |
| 5f75e73c LP |
261 | interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH |
| 262 | 0 105 IRQ_TYPE_LEVEL_HIGH>; | |
| f73e1e28 | 263 | clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; |
| 546e5d3e | 264 | toshiba,mmc-wrprotect-disable; |
| a463f731 | 265 | cap-sd-highspeed; |
| 546e5d3e GL |
266 | status = "disabled"; |
| 267 | }; | |
| 3f59007e | 268 | |
| 2131421b SH |
269 | scifa0: serial@e6c40000 { |
| 270 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
| 271 | reg = <0xe6c40000 0x100>; | |
| 2131421b | 272 | interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
273 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; |
| 274 | clock-names = "sci_ick"; | |
| 2131421b SH |
275 | status = "disabled"; |
| 276 | }; | |
| 277 | ||
| 278 | scifa1: serial@e6c50000 { | |
| 279 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
| 280 | reg = <0xe6c50000 0x100>; | |
| 2131421b | 281 | interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
282 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; |
| 283 | clock-names = "sci_ick"; | |
| 2131421b SH |
284 | status = "disabled"; |
| 285 | }; | |
| 286 | ||
| 287 | scifa2: serial@e6c60000 { | |
| 288 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
| 289 | reg = <0xe6c60000 0x100>; | |
| 2131421b | 290 | interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
291 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; |
| 292 | clock-names = "sci_ick"; | |
| 2131421b SH |
293 | status = "disabled"; |
| 294 | }; | |
| 295 | ||
| 296 | scifa3: serial@e6c70000 { | |
| 297 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
| 298 | reg = <0xe6c70000 0x100>; | |
| 2131421b | 299 | interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
300 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; |
| 301 | clock-names = "sci_ick"; | |
| 2131421b SH |
302 | status = "disabled"; |
| 303 | }; | |
| 304 | ||
| 305 | scifa4: serial@e6c80000 { | |
| 306 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
| 307 | reg = <0xe6c80000 0x100>; | |
| 2131421b | 308 | interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
309 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; |
| 310 | clock-names = "sci_ick"; | |
| 2131421b SH |
311 | status = "disabled"; |
| 312 | }; | |
| 313 | ||
| 314 | scifa5: serial@e6cb0000 { | |
| 315 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
| 316 | reg = <0xe6cb0000 0x100>; | |
| 2131421b | 317 | interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
318 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; |
| 319 | clock-names = "sci_ick"; | |
| 2131421b SH |
320 | status = "disabled"; |
| 321 | }; | |
| 322 | ||
| 323 | scifa6: serial@e6cc0000 { | |
| 324 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
| 325 | reg = <0xe6cc0000 0x100>; | |
| 2131421b | 326 | interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
327 | clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; |
| 328 | clock-names = "sci_ick"; | |
| 2131421b SH |
329 | status = "disabled"; |
| 330 | }; | |
| 331 | ||
| 332 | scifa7: serial@e6cd0000 { | |
| 333 | compatible = "renesas,scifa-sh73a0", "renesas,scifa"; | |
| 334 | reg = <0xe6cd0000 0x100>; | |
| 2131421b | 335 | interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
336 | clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; |
| 337 | clock-names = "sci_ick"; | |
| 2131421b SH |
338 | status = "disabled"; |
| 339 | }; | |
| 340 | ||
| 341 | scifb8: serial@e6c30000 { | |
| 342 | compatible = "renesas,scifb-sh73a0", "renesas,scifb"; | |
| 343 | reg = <0xe6c30000 0x100>; | |
| 2131421b | 344 | interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; |
| f73e1e28 UH |
345 | clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; |
| 346 | clock-names = "sci_ick"; | |
| 2131421b SH |
347 | status = "disabled"; |
| 348 | }; | |
| 349 | ||
| 3f59007e LP |
350 | pfc: pfc@e6050000 { |
| 351 | compatible = "renesas,pfc-sh73a0"; | |
| 352 | reg = <0xe6050000 0x8000>, | |
| 353 | <0xe605801c 0x1c>; | |
| 354 | gpio-controller; | |
| 355 | #gpio-cells = <2>; | |
| aba76d28 LP |
356 | interrupts-extended = |
| 357 | <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>, | |
| 358 | <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>, | |
| 359 | <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>, | |
| 360 | <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>, | |
| 361 | <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>, | |
| 362 | <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, | |
| 363 | <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, | |
| 364 | <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; | |
| 3f59007e | 365 | }; |
| 63b1303d KM |
366 | |
| 367 | sh_fsi2: sound@ec230000 { | |
| 368 | #sound-dai-cells = <1>; | |
| f76452fd | 369 | compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; |
| 63b1303d | 370 | reg = <0xec230000 0x400>; |
| 63b1303d KM |
371 | interrupts = <0 146 0x4>; |
| 372 | status = "disabled"; | |
| 373 | }; | |
| 00df6113 UH |
374 | |
| 375 | clocks { | |
| 376 | #address-cells = <1>; | |
| 377 | #size-cells = <1>; | |
| 378 | ranges; | |
| 379 | ||
| 380 | /* External root clocks */ | |
| 381 | extalr_clk: extalr_clk { | |
| 382 | compatible = "fixed-clock"; | |
| 383 | #clock-cells = <0>; | |
| 384 | clock-frequency = <32768>; | |
| 385 | clock-output-names = "extalr"; | |
| 386 | }; | |
| 387 | extal1_clk: extal1_clk { | |
| 388 | compatible = "fixed-clock"; | |
| 389 | #clock-cells = <0>; | |
| 390 | clock-frequency = <26000000>; | |
| 391 | clock-output-names = "extal1"; | |
| 392 | }; | |
| 393 | extal2_clk: extal2_clk { | |
| 394 | compatible = "fixed-clock"; | |
| 395 | #clock-cells = <0>; | |
| 396 | clock-output-names = "extal2"; | |
| 397 | }; | |
| 398 | extcki_clk: extcki_clk { | |
| 399 | compatible = "fixed-clock"; | |
| 400 | #clock-cells = <0>; | |
| 401 | clock-output-names = "extcki"; | |
| 402 | }; | |
| 403 | fsiack_clk: fsiack_clk { | |
| 404 | compatible = "fixed-clock"; | |
| 405 | #clock-cells = <0>; | |
| 406 | clock-frequency = <0>; | |
| 407 | clock-output-names = "fsiack"; | |
| 408 | }; | |
| 409 | fsibck_clk: fsibck_clk { | |
| 410 | compatible = "fixed-clock"; | |
| 411 | #clock-cells = <0>; | |
| 412 | clock-frequency = <0>; | |
| 413 | clock-output-names = "fsibck"; | |
| 414 | }; | |
| 415 | ||
| 416 | /* Special CPG clocks */ | |
| 417 | cpg_clocks: cpg_clocks@e6150000 { | |
| 418 | compatible = "renesas,sh73a0-cpg-clocks"; | |
| 419 | reg = <0xe6150000 0x10000>; | |
| 420 | clocks = <&extal1_clk>, <&extal2_clk>; | |
| 421 | #clock-cells = <1>; | |
| 422 | clock-output-names = "main", "pll0", "pll1", "pll2", | |
| 423 | "pll3", "dsi0phy", "dsi1phy", | |
| 424 | "zg", "m3", "b", "m1", "m2", | |
| 425 | "z", "zx", "hp"; | |
| 426 | }; | |
| 427 | ||
| 428 | /* Variable factor clocks (DIV6) */ | |
| 429 | vclk1_clk: vclk1_clk@e6150008 { | |
| 430 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 431 | reg = <0xe6150008 4>; | |
| 432 | clocks = <&pll1_div2_clk>; | |
| 433 | #clock-cells = <0>; | |
| 434 | clock-output-names = "vclk1"; | |
| 435 | }; | |
| 436 | vclk2_clk: vclk2_clk@e615000c { | |
| 437 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 438 | reg = <0xe615000c 4>; | |
| 439 | clocks = <&pll1_div2_clk>; | |
| 440 | #clock-cells = <0>; | |
| 441 | clock-output-names = "vclk2"; | |
| 442 | }; | |
| 443 | vclk3_clk: vclk3_clk@e615001c { | |
| 444 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 445 | reg = <0xe615001c 4>; | |
| 446 | clocks = <&pll1_div2_clk>; | |
| 447 | #clock-cells = <0>; | |
| 448 | clock-output-names = "vclk3"; | |
| 449 | }; | |
| 450 | zb_clk: zb_clk@e6150010 { | |
| 451 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 452 | reg = <0xe6150010 4>; | |
| 453 | clocks = <&pll1_div2_clk>; | |
| 454 | #clock-cells = <0>; | |
| 455 | clock-output-names = "zb"; | |
| 456 | }; | |
| 457 | flctl_clk: flctl_clk@e6150014 { | |
| 458 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 459 | reg = <0xe6150014 4>; | |
| 460 | clocks = <&pll1_div2_clk>; | |
| 461 | #clock-cells = <0>; | |
| 462 | clock-output-names = "flctlck"; | |
| 463 | }; | |
| 464 | sdhi0_clk: sdhi0_clk@e6150074 { | |
| 465 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 466 | reg = <0xe6150074 4>; | |
| 467 | clocks = <&pll1_div2_clk>; | |
| 468 | #clock-cells = <0>; | |
| 469 | clock-output-names = "sdhi0ck"; | |
| 470 | }; | |
| 471 | sdhi1_clk: sdhi1_clk@e6150078 { | |
| 472 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 473 | reg = <0xe6150078 4>; | |
| 474 | clocks = <&pll1_div2_clk>; | |
| 475 | #clock-cells = <0>; | |
| 476 | clock-output-names = "sdhi1ck"; | |
| 477 | }; | |
| 478 | sdhi2_clk: sdhi2_clk@e615007c { | |
| 479 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 480 | reg = <0xe615007c 4>; | |
| 481 | clocks = <&pll1_div2_clk>; | |
| 482 | #clock-cells = <0>; | |
| 483 | clock-output-names = "sdhi2ck"; | |
| 484 | }; | |
| 485 | fsia_clk: fsia_clk@e6150018 { | |
| 486 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 487 | reg = <0xe6150018 4>; | |
| 488 | clocks = <&pll1_div2_clk>; | |
| 489 | #clock-cells = <0>; | |
| 490 | clock-output-names = "fsia"; | |
| 491 | }; | |
| 492 | fsib_clk: fsib_clk@e6150090 { | |
| 493 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 494 | reg = <0xe6150090 4>; | |
| 495 | clocks = <&pll1_div2_clk>; | |
| 496 | #clock-cells = <0>; | |
| 497 | clock-output-names = "fsib"; | |
| 498 | }; | |
| 499 | sub_clk: sub_clk@e6150080 { | |
| 500 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 501 | reg = <0xe6150080 4>; | |
| 502 | clocks = <&extal2_clk>; | |
| 503 | #clock-cells = <0>; | |
| 504 | clock-output-names = "sub"; | |
| 505 | }; | |
| 506 | spua_clk: spua_clk@e6150084 { | |
| 507 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 508 | reg = <0xe6150084 4>; | |
| 509 | clocks = <&pll1_div2_clk>; | |
| 510 | #clock-cells = <0>; | |
| 511 | clock-output-names = "spua"; | |
| 512 | }; | |
| 513 | spuv_clk: spuv_clk@e6150094 { | |
| 514 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 515 | reg = <0xe6150094 4>; | |
| 516 | clocks = <&pll1_div2_clk>; | |
| 517 | #clock-cells = <0>; | |
| 518 | clock-output-names = "spuv"; | |
| 519 | }; | |
| 520 | msu_clk: msu_clk@e6150088 { | |
| 521 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 522 | reg = <0xe6150088 4>; | |
| 523 | clocks = <&pll1_div2_clk>; | |
| 524 | #clock-cells = <0>; | |
| 525 | clock-output-names = "msu"; | |
| 526 | }; | |
| 527 | hsi_clk: hsi_clk@e615008c { | |
| 528 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 529 | reg = <0xe615008c 4>; | |
| 530 | clocks = <&pll1_div2_clk>; | |
| 531 | #clock-cells = <0>; | |
| 532 | clock-output-names = "hsi"; | |
| 533 | }; | |
| 534 | mfg1_clk: mfg1_clk@e6150098 { | |
| 535 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 536 | reg = <0xe6150098 4>; | |
| 537 | clocks = <&pll1_div2_clk>; | |
| 538 | #clock-cells = <0>; | |
| 539 | clock-output-names = "mfg1"; | |
| 540 | }; | |
| 541 | mfg2_clk: mfg2_clk@e615009c { | |
| 542 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 543 | reg = <0xe615009c 4>; | |
| 544 | clocks = <&pll1_div2_clk>; | |
| 545 | #clock-cells = <0>; | |
| 546 | clock-output-names = "mfg2"; | |
| 547 | }; | |
| 548 | dsit_clk: dsit_clk@e6150060 { | |
| 549 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 550 | reg = <0xe6150060 4>; | |
| 551 | clocks = <&pll1_div2_clk>; | |
| 552 | #clock-cells = <0>; | |
| 553 | clock-output-names = "dsit"; | |
| 554 | }; | |
| 555 | dsi0p_clk: dsi0p_clk@e6150064 { | |
| 556 | compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; | |
| 557 | reg = <0xe6150064 4>; | |
| 558 | clocks = <&pll1_div2_clk>; | |
| 559 | #clock-cells = <0>; | |
| 560 | clock-output-names = "dsi0pck"; | |
| 561 | }; | |
| 562 | ||
| 563 | /* Fixed factor clocks */ | |
| 564 | main_div2_clk: main_div2_clk { | |
| 565 | compatible = "fixed-factor-clock"; | |
| 566 | clocks = <&cpg_clocks SH73A0_CLK_MAIN>; | |
| 567 | #clock-cells = <0>; | |
| 568 | clock-div = <2>; | |
| 569 | clock-mult = <1>; | |
| 570 | clock-output-names = "main_div2"; | |
| 571 | }; | |
| 572 | pll1_div2_clk: pll1_div2_clk { | |
| 573 | compatible = "fixed-factor-clock"; | |
| 574 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
| 575 | #clock-cells = <0>; | |
| 576 | clock-div = <2>; | |
| 577 | clock-mult = <1>; | |
| 578 | clock-output-names = "pll1_div2"; | |
| 579 | }; | |
| 580 | pll1_div7_clk: pll1_div7_clk { | |
| 581 | compatible = "fixed-factor-clock"; | |
| 582 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
| 583 | #clock-cells = <0>; | |
| 584 | clock-div = <7>; | |
| 585 | clock-mult = <1>; | |
| 586 | clock-output-names = "pll1_div7"; | |
| 587 | }; | |
| 588 | pll1_div13_clk: pll1_div13_clk { | |
| 589 | compatible = "fixed-factor-clock"; | |
| 590 | clocks = <&cpg_clocks SH73A0_CLK_PLL1>; | |
| 591 | #clock-cells = <0>; | |
| 592 | clock-div = <13>; | |
| 593 | clock-mult = <1>; | |
| 594 | clock-output-names = "pll1_div13"; | |
| 595 | }; | |
| 596 | twd_clk: twd_clk { | |
| 597 | compatible = "fixed-factor-clock"; | |
| 598 | clocks = <&cpg_clocks SH73A0_CLK_Z>; | |
| 599 | #clock-cells = <0>; | |
| 600 | clock-div = <4>; | |
| 601 | clock-mult = <1>; | |
| 602 | clock-output-names = "twd"; | |
| 603 | }; | |
| 604 | ||
| 605 | /* Gate clocks */ | |
| 606 | mstp0_clks: mstp0_clks@e6150130 { | |
| 607 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 608 | reg = <0xe6150130 4>, <0xe6150030 4>; | |
| 609 | clocks = <&cpg_clocks SH73A0_CLK_HP>; | |
| 610 | #clock-cells = <1>; | |
| 611 | clock-indices = < | |
| 612 | SH73A0_CLK_IIC2 | |
| 613 | >; | |
| 614 | clock-output-names = | |
| 615 | "iic2"; | |
| 616 | }; | |
| 617 | mstp1_clks: mstp1_clks@e6150134 { | |
| 618 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 619 | reg = <0xe6150134 4>, <0xe6150038 4>; | |
| 620 | clocks = <&cpg_clocks SH73A0_CLK_B>, | |
| 621 | <&cpg_clocks SH73A0_CLK_B>, | |
| 622 | <&cpg_clocks SH73A0_CLK_B>, | |
| 623 | <&cpg_clocks SH73A0_CLK_B>, | |
| 624 | <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>, | |
| 625 | <&cpg_clocks SH73A0_CLK_HP>, | |
| 626 | <&cpg_clocks SH73A0_CLK_ZG>, | |
| 627 | <&cpg_clocks SH73A0_CLK_B>; | |
| 628 | #clock-cells = <1>; | |
| 629 | clock-indices = < | |
| 630 | SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1 | |
| 631 | SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0 | |
| 632 | SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0 | |
| 633 | SH73A0_CLK_IIC0 SH73A0_CLK_SGX | |
| 634 | SH73A0_CLK_LCDC0 | |
| 635 | >; | |
| 636 | clock-output-names = | |
| 637 | "ceu1", "csi2_rx1", "ceu0", "csi2_rx0", | |
| 638 | "tmu0", "dsitx0", "iic0", "sgx", "lcdc0"; | |
| 639 | }; | |
| 640 | mstp2_clks: mstp2_clks@e6150138 { | |
| 641 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 642 | reg = <0xe6150138 4>, <0xe6150040 4>; | |
| 643 | clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>, | |
| 644 | <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, | |
| 645 | <&sub_clk>, <&sub_clk>, <&sub_clk>, <&sub_clk>, | |
| 646 | <&sub_clk>, <&sub_clk>; | |
| 647 | #clock-cells = <1>; | |
| 648 | clock-indices = < | |
| 649 | SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC | |
| 650 | SH73A0_CLK_MP_DMAC SH73A0_CLK_SCIFA5 | |
| 651 | SH73A0_CLK_SCIFB SH73A0_CLK_SCIFA0 | |
| 652 | SH73A0_CLK_SCIFA1 SH73A0_CLK_SCIFA2 | |
| 653 | SH73A0_CLK_SCIFA3 SH73A0_CLK_SCIFA4 | |
| 654 | >; | |
| 655 | clock-output-names = | |
| 656 | "scifa7", "sy_dmac", "mp_dmac", "scifa5", | |
| 657 | "scifb", "scifa0", "scifa1", "scifa2", | |
| 658 | "scifa3", "scifa4"; | |
| 659 | }; | |
| 660 | mstp3_clks: mstp3_clks@e615013c { | |
| 661 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 662 | reg = <0xe615013c 4>, <0xe6150048 4>; | |
| 663 | clocks = <&sub_clk>, <&extalr_clk>, | |
| 664 | <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>, | |
| 665 | <&cpg_clocks SH73A0_CLK_HP>, | |
| 666 | <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>, | |
| 667 | <&sdhi0_clk>, <&sdhi1_clk>, | |
| 668 | <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>, | |
| 669 | <&main_div2_clk>, <&main_div2_clk>, | |
| 670 | <&main_div2_clk>, <&main_div2_clk>, | |
| 671 | <&main_div2_clk>; | |
| 672 | #clock-cells = <1>; | |
| 673 | clock-indices = < | |
| 674 | SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1 | |
| 675 | SH73A0_CLK_FSI SH73A0_CLK_IRDA | |
| 676 | SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL | |
| 677 | SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1 | |
| 678 | SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2 | |
| 679 | SH73A0_CLK_TPU0 SH73A0_CLK_TPU1 | |
| 680 | SH73A0_CLK_TPU2 SH73A0_CLK_TPU3 | |
| 681 | SH73A0_CLK_TPU4 | |
| 682 | >; | |
| 683 | clock-output-names = | |
| 684 | "scifa6", "cmt1", "fsi", "irda", "iic1", | |
| 685 | "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2", | |
| 686 | "tpu0", "tpu1", "tpu2", "tpu3", "tpu4"; | |
| 687 | }; | |
| 688 | mstp4_clks: mstp4_clks@e6150140 { | |
| 689 | compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks"; | |
| 690 | reg = <0xe6150140 4>, <0xe615004c 4>; | |
| 691 | clocks = <&cpg_clocks SH73A0_CLK_HP>, | |
| 692 | <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>; | |
| 693 | #clock-cells = <1>; | |
| 694 | clock-indices = < | |
| 695 | SH73A0_CLK_IIC3 SH73A0_CLK_IIC4 | |
| 696 | SH73A0_CLK_KEYSC | |
| 697 | >; | |
| 698 | clock-output-names = | |
| 699 | "iic3", "iic4", "keysc"; | |
| 700 | }; | |
| 701 | }; | |
| a3f22db5 | 702 | }; |