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66314223 DN |
1 | /* |
2 | * Copyright (C) 2012 Altera <www.altera.com> | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License as published by | |
6 | * the Free Software Foundation; either version 2 of the License, or | |
7 | * (at your option) any later version. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
12 | * GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
16 | */ | |
17 | ||
18 | /include/ "skeleton.dtsi" | |
19 | ||
20 | / { | |
21 | #address-cells = <1>; | |
22 | #size-cells = <1>; | |
23 | ||
24 | aliases { | |
25 | ethernet0 = &gmac0; | |
3d954cf1 | 26 | ethernet1 = &gmac1; |
66314223 DN |
27 | serial0 = &uart0; |
28 | serial1 = &uart1; | |
c2ad2844 DN |
29 | timer0 = &timer0; |
30 | timer1 = &timer1; | |
31 | timer2 = &timer2; | |
32 | timer3 = &timer3; | |
66314223 DN |
33 | }; |
34 | ||
35 | cpus { | |
36 | #address-cells = <1>; | |
37 | #size-cells = <0>; | |
38 | ||
39 | cpu@0 { | |
40 | compatible = "arm,cortex-a9"; | |
41 | device_type = "cpu"; | |
42 | reg = <0>; | |
43 | next-level-cache = <&L2>; | |
44 | }; | |
45 | cpu@1 { | |
46 | compatible = "arm,cortex-a9"; | |
47 | device_type = "cpu"; | |
48 | reg = <1>; | |
49 | next-level-cache = <&L2>; | |
50 | }; | |
51 | }; | |
52 | ||
53 | intc: intc@fffed000 { | |
54 | compatible = "arm,cortex-a9-gic"; | |
55 | #interrupt-cells = <3>; | |
56 | interrupt-controller; | |
57 | reg = <0xfffed000 0x1000>, | |
58 | <0xfffec100 0x100>; | |
59 | }; | |
60 | ||
61 | soc { | |
62 | #address-cells = <1>; | |
63 | #size-cells = <1>; | |
64 | compatible = "simple-bus"; | |
65 | device_type = "soc"; | |
66 | interrupt-parent = <&intc>; | |
67 | ranges; | |
68 | ||
69 | amba { | |
70 | compatible = "arm,amba-bus"; | |
71 | #address-cells = <1>; | |
72 | #size-cells = <1>; | |
73 | ranges; | |
74 | ||
75 | pdma: pdma@ffe01000 { | |
76 | compatible = "arm,pl330", "arm,primecell"; | |
77 | reg = <0xffe01000 0x1000>; | |
78 | interrupts = <0 180 4>; | |
0d8abbfd PV |
79 | #dma-cells = <1>; |
80 | #dma-channels = <8>; | |
81 | #dma-requests = <32>; | |
672ef909 ST |
82 | clocks = <&l4_main_clk>; |
83 | clock-names = "apb_pclk"; | |
66314223 DN |
84 | }; |
85 | }; | |
86 | ||
042000b0 DN |
87 | clkmgr@ffd04000 { |
88 | compatible = "altr,clk-mgr"; | |
89 | reg = <0xffd04000 0x1000>; | |
90 | ||
91 | clocks { | |
92 | #address-cells = <1>; | |
93 | #size-cells = <0>; | |
94 | ||
95 | osc: osc1 { | |
96 | #clock-cells = <0>; | |
97 | compatible = "fixed-clock"; | |
98 | }; | |
99 | ||
a92b83af DN |
100 | f2s_periph_ref_clk: f2s_periph_ref_clk { |
101 | #clock-cells = <0>; | |
102 | compatible = "fixed-clock"; | |
103 | clock-frequency = <10000000>; | |
104 | }; | |
105 | ||
042000b0 DN |
106 | main_pll: main_pll { |
107 | #address-cells = <1>; | |
108 | #size-cells = <0>; | |
109 | #clock-cells = <0>; | |
110 | compatible = "altr,socfpga-pll-clock"; | |
111 | clocks = <&osc>; | |
112 | reg = <0x40>; | |
113 | ||
114 | mpuclk: mpuclk { | |
115 | #clock-cells = <0>; | |
116 | compatible = "altr,socfpga-perip-clk"; | |
117 | clocks = <&main_pll>; | |
118 | fixed-divider = <2>; | |
119 | reg = <0x48>; | |
120 | }; | |
121 | ||
122 | mainclk: mainclk { | |
123 | #clock-cells = <0>; | |
124 | compatible = "altr,socfpga-perip-clk"; | |
125 | clocks = <&main_pll>; | |
126 | fixed-divider = <4>; | |
127 | reg = <0x4C>; | |
128 | }; | |
129 | ||
130 | dbg_base_clk: dbg_base_clk { | |
131 | #clock-cells = <0>; | |
132 | compatible = "altr,socfpga-perip-clk"; | |
133 | clocks = <&main_pll>; | |
134 | fixed-divider = <4>; | |
135 | reg = <0x50>; | |
136 | }; | |
137 | ||
138 | main_qspi_clk: main_qspi_clk { | |
139 | #clock-cells = <0>; | |
140 | compatible = "altr,socfpga-perip-clk"; | |
141 | clocks = <&main_pll>; | |
142 | reg = <0x54>; | |
143 | }; | |
144 | ||
145 | main_nand_sdmmc_clk: main_nand_sdmmc_clk { | |
146 | #clock-cells = <0>; | |
147 | compatible = "altr,socfpga-perip-clk"; | |
148 | clocks = <&main_pll>; | |
149 | reg = <0x58>; | |
150 | }; | |
151 | ||
01ed80b0 | 152 | cfg_h2f_usr0_clk: cfg_h2f_usr0_clk { |
042000b0 DN |
153 | #clock-cells = <0>; |
154 | compatible = "altr,socfpga-perip-clk"; | |
155 | clocks = <&main_pll>; | |
156 | reg = <0x5C>; | |
157 | }; | |
158 | }; | |
159 | ||
160 | periph_pll: periph_pll { | |
161 | #address-cells = <1>; | |
162 | #size-cells = <0>; | |
163 | #clock-cells = <0>; | |
164 | compatible = "altr,socfpga-pll-clock"; | |
165 | clocks = <&osc>; | |
166 | reg = <0x80>; | |
167 | ||
168 | emac0_clk: emac0_clk { | |
169 | #clock-cells = <0>; | |
170 | compatible = "altr,socfpga-perip-clk"; | |
171 | clocks = <&periph_pll>; | |
172 | reg = <0x88>; | |
173 | }; | |
174 | ||
175 | emac1_clk: emac1_clk { | |
176 | #clock-cells = <0>; | |
177 | compatible = "altr,socfpga-perip-clk"; | |
178 | clocks = <&periph_pll>; | |
179 | reg = <0x8C>; | |
180 | }; | |
181 | ||
182 | per_qspi_clk: per_qsi_clk { | |
183 | #clock-cells = <0>; | |
184 | compatible = "altr,socfpga-perip-clk"; | |
185 | clocks = <&periph_pll>; | |
186 | reg = <0x90>; | |
187 | }; | |
188 | ||
189 | per_nand_mmc_clk: per_nand_mmc_clk { | |
190 | #clock-cells = <0>; | |
191 | compatible = "altr,socfpga-perip-clk"; | |
192 | clocks = <&periph_pll>; | |
193 | reg = <0x94>; | |
194 | }; | |
195 | ||
196 | per_base_clk: per_base_clk { | |
197 | #clock-cells = <0>; | |
198 | compatible = "altr,socfpga-perip-clk"; | |
199 | clocks = <&periph_pll>; | |
200 | reg = <0x98>; | |
201 | }; | |
202 | ||
01ed80b0 | 203 | h2f_usr1_clk: h2f_usr1_clk { |
042000b0 DN |
204 | #clock-cells = <0>; |
205 | compatible = "altr,socfpga-perip-clk"; | |
206 | clocks = <&periph_pll>; | |
207 | reg = <0x9C>; | |
208 | }; | |
209 | }; | |
210 | ||
211 | sdram_pll: sdram_pll { | |
212 | #address-cells = <1>; | |
213 | #size-cells = <0>; | |
214 | #clock-cells = <0>; | |
215 | compatible = "altr,socfpga-pll-clock"; | |
216 | clocks = <&osc>; | |
217 | reg = <0xC0>; | |
218 | ||
219 | ddr_dqs_clk: ddr_dqs_clk { | |
220 | #clock-cells = <0>; | |
221 | compatible = "altr,socfpga-perip-clk"; | |
222 | clocks = <&sdram_pll>; | |
223 | reg = <0xC8>; | |
224 | }; | |
225 | ||
226 | ddr_2x_dqs_clk: ddr_2x_dqs_clk { | |
227 | #clock-cells = <0>; | |
228 | compatible = "altr,socfpga-perip-clk"; | |
229 | clocks = <&sdram_pll>; | |
230 | reg = <0xCC>; | |
231 | }; | |
232 | ||
233 | ddr_dq_clk: ddr_dq_clk { | |
234 | #clock-cells = <0>; | |
235 | compatible = "altr,socfpga-perip-clk"; | |
236 | clocks = <&sdram_pll>; | |
237 | reg = <0xD0>; | |
238 | }; | |
239 | ||
01ed80b0 | 240 | h2f_usr2_clk: h2f_usr2_clk { |
042000b0 DN |
241 | #clock-cells = <0>; |
242 | compatible = "altr,socfpga-perip-clk"; | |
243 | clocks = <&sdram_pll>; | |
244 | reg = <0xD4>; | |
245 | }; | |
246 | }; | |
a92b83af | 247 | |
7857d560 ST |
248 | mpu_periph_clk: mpu_periph_clk { |
249 | #clock-cells = <0>; | |
a5c6e87a | 250 | compatible = "altr,socfpga-perip-clk"; |
7857d560 ST |
251 | clocks = <&mpuclk>; |
252 | fixed-divider = <4>; | |
a92b83af DN |
253 | }; |
254 | ||
7857d560 ST |
255 | mpu_l2_ram_clk: mpu_l2_ram_clk { |
256 | #clock-cells = <0>; | |
a5c6e87a | 257 | compatible = "altr,socfpga-perip-clk"; |
7857d560 ST |
258 | clocks = <&mpuclk>; |
259 | fixed-divider = <2>; | |
a92b83af DN |
260 | }; |
261 | ||
7857d560 ST |
262 | l4_main_clk: l4_main_clk { |
263 | #clock-cells = <0>; | |
264 | compatible = "altr,socfpga-gate-clk"; | |
265 | clocks = <&mainclk>; | |
266 | clk-gate = <0x60 0>; | |
a92b83af DN |
267 | }; |
268 | ||
7857d560 ST |
269 | l3_main_clk: l3_main_clk { |
270 | #clock-cells = <0>; | |
a5c6e87a | 271 | compatible = "altr,socfpga-perip-clk"; |
7857d560 | 272 | clocks = <&mainclk>; |
a5c6e87a | 273 | fixed-divider = <1>; |
a92b83af DN |
274 | }; |
275 | ||
7857d560 ST |
276 | l3_mp_clk: l3_mp_clk { |
277 | #clock-cells = <0>; | |
278 | compatible = "altr,socfpga-gate-clk"; | |
279 | clocks = <&mainclk>; | |
280 | div-reg = <0x64 0 2>; | |
281 | clk-gate = <0x60 1>; | |
a92b83af DN |
282 | }; |
283 | ||
7857d560 ST |
284 | l3_sp_clk: l3_sp_clk { |
285 | #clock-cells = <0>; | |
286 | compatible = "altr,socfpga-gate-clk"; | |
287 | clocks = <&mainclk>; | |
288 | div-reg = <0x64 2 2>; | |
289 | }; | |
a92b83af | 290 | |
7857d560 ST |
291 | l4_mp_clk: l4_mp_clk { |
292 | #clock-cells = <0>; | |
293 | compatible = "altr,socfpga-gate-clk"; | |
294 | clocks = <&mainclk>, <&per_base_clk>; | |
295 | div-reg = <0x64 4 3>; | |
296 | clk-gate = <0x60 2>; | |
a92b83af DN |
297 | }; |
298 | ||
7857d560 ST |
299 | l4_sp_clk: l4_sp_clk { |
300 | #clock-cells = <0>; | |
301 | compatible = "altr,socfpga-gate-clk"; | |
302 | clocks = <&mainclk>, <&per_base_clk>; | |
303 | div-reg = <0x64 7 3>; | |
304 | clk-gate = <0x60 3>; | |
a92b83af DN |
305 | }; |
306 | ||
7857d560 ST |
307 | dbg_at_clk: dbg_at_clk { |
308 | #clock-cells = <0>; | |
309 | compatible = "altr,socfpga-gate-clk"; | |
310 | clocks = <&dbg_base_clk>; | |
311 | div-reg = <0x68 0 2>; | |
312 | clk-gate = <0x60 4>; | |
a92b83af DN |
313 | }; |
314 | ||
7857d560 ST |
315 | dbg_clk: dbg_clk { |
316 | #clock-cells = <0>; | |
317 | compatible = "altr,socfpga-gate-clk"; | |
318 | clocks = <&dbg_base_clk>; | |
319 | div-reg = <0x68 2 2>; | |
320 | clk-gate = <0x60 5>; | |
a92b83af DN |
321 | }; |
322 | ||
7857d560 ST |
323 | dbg_trace_clk: dbg_trace_clk { |
324 | #clock-cells = <0>; | |
325 | compatible = "altr,socfpga-gate-clk"; | |
326 | clocks = <&dbg_base_clk>; | |
327 | div-reg = <0x6C 0 3>; | |
328 | clk-gate = <0x60 6>; | |
a92b83af DN |
329 | }; |
330 | ||
7857d560 ST |
331 | dbg_timer_clk: dbg_timer_clk { |
332 | #clock-cells = <0>; | |
333 | compatible = "altr,socfpga-gate-clk"; | |
334 | clocks = <&dbg_base_clk>; | |
335 | clk-gate = <0x60 7>; | |
a92b83af DN |
336 | }; |
337 | ||
7857d560 ST |
338 | cfg_clk: cfg_clk { |
339 | #clock-cells = <0>; | |
340 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 341 | clocks = <&cfg_h2f_usr0_clk>; |
7857d560 | 342 | clk-gate = <0x60 8>; |
a92b83af DN |
343 | }; |
344 | ||
01ed80b0 | 345 | h2f_user0_clk: h2f_user0_clk { |
7857d560 ST |
346 | #clock-cells = <0>; |
347 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 348 | clocks = <&cfg_h2f_usr0_clk>; |
7857d560 | 349 | clk-gate = <0x60 9>; |
a92b83af DN |
350 | }; |
351 | ||
7857d560 ST |
352 | emac_0_clk: emac_0_clk { |
353 | #clock-cells = <0>; | |
354 | compatible = "altr,socfpga-gate-clk"; | |
355 | clocks = <&emac0_clk>; | |
356 | clk-gate = <0xa0 0>; | |
a92b83af DN |
357 | }; |
358 | ||
7857d560 ST |
359 | emac_1_clk: emac_1_clk { |
360 | #clock-cells = <0>; | |
361 | compatible = "altr,socfpga-gate-clk"; | |
362 | clocks = <&emac1_clk>; | |
363 | clk-gate = <0xa0 1>; | |
a92b83af DN |
364 | }; |
365 | ||
7857d560 ST |
366 | usb_mp_clk: usb_mp_clk { |
367 | #clock-cells = <0>; | |
368 | compatible = "altr,socfpga-gate-clk"; | |
369 | clocks = <&per_base_clk>; | |
370 | clk-gate = <0xa0 2>; | |
371 | div-reg = <0xa4 0 3>; | |
a92b83af DN |
372 | }; |
373 | ||
7857d560 ST |
374 | spi_m_clk: spi_m_clk { |
375 | #clock-cells = <0>; | |
376 | compatible = "altr,socfpga-gate-clk"; | |
377 | clocks = <&per_base_clk>; | |
378 | clk-gate = <0xa0 3>; | |
379 | div-reg = <0xa4 3 3>; | |
a92b83af DN |
380 | }; |
381 | ||
7857d560 ST |
382 | can0_clk: can0_clk { |
383 | #clock-cells = <0>; | |
384 | compatible = "altr,socfpga-gate-clk"; | |
385 | clocks = <&per_base_clk>; | |
386 | clk-gate = <0xa0 4>; | |
387 | div-reg = <0xa4 6 3>; | |
a92b83af DN |
388 | }; |
389 | ||
7857d560 ST |
390 | can1_clk: can1_clk { |
391 | #clock-cells = <0>; | |
392 | compatible = "altr,socfpga-gate-clk"; | |
393 | clocks = <&per_base_clk>; | |
394 | clk-gate = <0xa0 5>; | |
395 | div-reg = <0xa4 9 3>; | |
a92b83af DN |
396 | }; |
397 | ||
7857d560 ST |
398 | gpio_db_clk: gpio_db_clk { |
399 | #clock-cells = <0>; | |
400 | compatible = "altr,socfpga-gate-clk"; | |
401 | clocks = <&per_base_clk>; | |
402 | clk-gate = <0xa0 6>; | |
403 | div-reg = <0xa8 0 24>; | |
a92b83af DN |
404 | }; |
405 | ||
01ed80b0 | 406 | h2f_user1_clk: h2f_user1_clk { |
7857d560 ST |
407 | #clock-cells = <0>; |
408 | compatible = "altr,socfpga-gate-clk"; | |
01ed80b0 | 409 | clocks = <&h2f_usr1_clk>; |
7857d560 | 410 | clk-gate = <0xa0 7>; |
a92b83af DN |
411 | }; |
412 | ||
7857d560 ST |
413 | sdmmc_clk: sdmmc_clk { |
414 | #clock-cells = <0>; | |
415 | compatible = "altr,socfpga-gate-clk"; | |
416 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
417 | clk-gate = <0xa0 8>; | |
a92b83af DN |
418 | }; |
419 | ||
7857d560 ST |
420 | nand_x_clk: nand_x_clk { |
421 | #clock-cells = <0>; | |
422 | compatible = "altr,socfpga-gate-clk"; | |
423 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
424 | clk-gate = <0xa0 9>; | |
a92b83af DN |
425 | }; |
426 | ||
7857d560 ST |
427 | nand_clk: nand_clk { |
428 | #clock-cells = <0>; | |
429 | compatible = "altr,socfpga-gate-clk"; | |
430 | clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; | |
431 | clk-gate = <0xa0 10>; | |
432 | fixed-divider = <4>; | |
a92b83af DN |
433 | }; |
434 | ||
7857d560 ST |
435 | qspi_clk: qspi_clk { |
436 | #clock-cells = <0>; | |
437 | compatible = "altr,socfpga-gate-clk"; | |
438 | clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>; | |
439 | clk-gate = <0xa0 11>; | |
a92b83af | 440 | }; |
042000b0 DN |
441 | }; |
442 | }; | |
443 | ||
3d954cf1 | 444 | gmac0: ethernet@ff700000 { |
66314223 DN |
445 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; |
446 | reg = <0xff700000 0x2000>; | |
447 | interrupts = <0 115 4>; | |
448 | interrupt-names = "macirq"; | |
449 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | |
3d954cf1 DN |
450 | clocks = <&emac0_clk>; |
451 | clock-names = "stmmaceth"; | |
452 | status = "disabled"; | |
453 | }; | |
454 | ||
455 | gmac1: ethernet@ff702000 { | |
456 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac"; | |
457 | reg = <0xff702000 0x2000>; | |
458 | interrupts = <0 120 4>; | |
459 | interrupt-names = "macirq"; | |
460 | mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */ | |
461 | clocks = <&emac1_clk>; | |
462 | clock-names = "stmmaceth"; | |
463 | status = "disabled"; | |
66314223 DN |
464 | }; |
465 | ||
466 | L2: l2-cache@fffef000 { | |
467 | compatible = "arm,pl310-cache"; | |
468 | reg = <0xfffef000 0x1000>; | |
469 | interrupts = <0 38 0x04>; | |
470 | cache-unified; | |
471 | cache-level = <2>; | |
9a21e55d DN |
472 | arm,tag-latency = <1 1 1>; |
473 | arm,data-latency = <2 1 1>; | |
66314223 DN |
474 | }; |
475 | ||
476 | /* Local timer */ | |
477 | timer@fffec600 { | |
478 | compatible = "arm,cortex-a9-twd-timer"; | |
479 | reg = <0xfffec600 0x100>; | |
480 | interrupts = <1 13 0xf04>; | |
159c7f89 | 481 | clocks = <&mpu_periph_clk>; |
66314223 DN |
482 | }; |
483 | ||
c2ad2844 | 484 | timer0: timer0@ffc08000 { |
620f5e1c | 485 | compatible = "snps,dw-apb-timer"; |
66314223 | 486 | interrupts = <0 167 4>; |
66314223 DN |
487 | reg = <0xffc08000 0x1000>; |
488 | }; | |
489 | ||
c2ad2844 | 490 | timer1: timer1@ffc09000 { |
620f5e1c | 491 | compatible = "snps,dw-apb-timer"; |
66314223 | 492 | interrupts = <0 168 4>; |
66314223 DN |
493 | reg = <0xffc09000 0x1000>; |
494 | }; | |
495 | ||
c2ad2844 | 496 | timer2: timer2@ffd00000 { |
620f5e1c | 497 | compatible = "snps,dw-apb-timer"; |
66314223 | 498 | interrupts = <0 169 4>; |
66314223 DN |
499 | reg = <0xffd00000 0x1000>; |
500 | }; | |
501 | ||
c2ad2844 | 502 | timer3: timer3@ffd01000 { |
620f5e1c | 503 | compatible = "snps,dw-apb-timer"; |
66314223 | 504 | interrupts = <0 170 4>; |
66314223 DN |
505 | reg = <0xffd01000 0x1000>; |
506 | }; | |
507 | ||
c2ad2844 | 508 | uart0: serial0@ffc02000 { |
66314223 DN |
509 | compatible = "snps,dw-apb-uart"; |
510 | reg = <0xffc02000 0x1000>; | |
66314223 DN |
511 | interrupts = <0 162 4>; |
512 | reg-shift = <2>; | |
513 | reg-io-width = <4>; | |
514 | }; | |
515 | ||
c2ad2844 | 516 | uart1: serial1@ffc03000 { |
66314223 DN |
517 | compatible = "snps,dw-apb-uart"; |
518 | reg = <0xffc03000 0x1000>; | |
66314223 DN |
519 | interrupts = <0 163 4>; |
520 | reg-shift = <2>; | |
521 | reg-io-width = <4>; | |
522 | }; | |
9c4566a1 DN |
523 | |
524 | rstmgr@ffd05000 { | |
7857d560 ST |
525 | compatible = "altr,rst-mgr"; |
526 | reg = <0xffd05000 0x1000>; | |
527 | }; | |
9c4566a1 DN |
528 | |
529 | sysmgr@ffd08000 { | |
530 | compatible = "altr,sys-mgr"; | |
531 | reg = <0xffd08000 0x4000>; | |
532 | }; | |
66314223 DN |
533 | }; |
534 | }; |