[deliverable/linux.git] / arch / arm / boot / dts / socfpga.dtsi

/*
 *  Copyright (C) 2012 Altera <www.altera.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include "skeleton.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		ethernet0 = &gmac0;
		ethernet1 = &gmac1;
		serial0 = &uart0;
		serial1 = &uart1;
		timer0 = &timer0;
		timer1 = &timer1;
		timer2 = &timer2;
		timer3 = &timer3;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
		};
		cpu@1 {
			compatible = "arm,cortex-a9";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
		};
	};

	intc: intc@fffed000 {
		compatible = "arm,cortex-a9-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xfffed000 0x1000>,
		      <0xfffec100 0x100>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges;

		amba {
			compatible = "arm,amba-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			pdma: pdma@ffe01000 {
				compatible = "arm,pl330", "arm,primecell";
				reg = <0xffe01000 0x1000>;
				interrupts = <0 104 4>,
					     <0 105 4>,
					     <0 106 4>,
					     <0 107 4>,
					     <0 108 4>,
					     <0 109 4>,
					     <0 110 4>,
					     <0 111 4>;
				#dma-cells = <1>;
				#dma-channels = <8>;
				#dma-requests = <32>;
				clocks = <&l4_main_clk>;
				clock-names = "apb_pclk";
			};
		};

		can0: can@ffc00000 {
			compatible = "bosch,d_can";
			reg = <0xffc00000 0x1000>;
			interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
			clocks = <&can0_clk>;
			status = "disabled";
		};

		can1: can@ffc01000 {
			compatible = "bosch,d_can";
			reg = <0xffc01000 0x1000>;
			interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
			clocks = <&can1_clk>;
			status = "disabled";
		};

		clkmgr@ffd04000 {
				compatible = "altr,clk-mgr";
				reg = <0xffd04000 0x1000>;

				clocks {
					#address-cells = <1>;
					#size-cells = <0>;

					osc1: osc1 {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					osc2: osc2 {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					f2s_periph_ref_clk: f2s_periph_ref_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					f2s_sdram_ref_clk: f2s_sdram_ref_clk {
						#clock-cells = <0>;
						compatible = "fixed-clock";
					};

					main_pll: main_pll {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc1>;
						reg = <0x40>;

						mpuclk: mpuclk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							fixed-divider = <2>;
							reg = <0x48>;
						};

						mainclk: mainclk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							fixed-divider = <4>;
							reg = <0x4C>;
						};

						dbg_base_clk: dbg_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							fixed-divider = <4>;
							reg = <0x50>;
						};

						main_qspi_clk: main_qspi_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x54>;
						};

						main_nand_sdmmc_clk: main_nand_sdmmc_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x58>;
						};

						cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&main_pll>;
							reg = <0x5C>;
						};
					};

					periph_pll: periph_pll {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
						reg = <0x80>;

						emac0_clk: emac0_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x88>;
						};

						emac1_clk: emac1_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x8C>;
						};

						per_qspi_clk: per_qsi_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x90>;
						};

						per_nand_mmc_clk: per_nand_mmc_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x94>;
						};

						per_base_clk: per_base_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x98>;
						};

						h2f_usr1_clk: h2f_usr1_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&periph_pll>;
							reg = <0x9C>;
						};
					};

					sdram_pll: sdram_pll {
						#address-cells = <1>;
						#size-cells = <0>;
						#clock-cells = <0>;
						compatible = "altr,socfpga-pll-clock";
						clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
						reg = <0xC0>;

						ddr_dqs_clk: ddr_dqs_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xC8>;
						};

						ddr_2x_dqs_clk: ddr_2x_dqs_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xCC>;
						};

						ddr_dq_clk: ddr_dq_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xD0>;
						};

						h2f_usr2_clk: h2f_usr2_clk {
							#clock-cells = <0>;
							compatible = "altr,socfpga-perip-clk";
							clocks = <&sdram_pll>;
							reg = <0xD4>;
						};
					};

					mpu_periph_clk: mpu_periph_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-perip-clk";
						clocks = <&mpuclk>;
						fixed-divider = <4>;
					};

					mpu_l2_ram_clk: mpu_l2_ram_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-perip-clk";
						clocks = <&mpuclk>;
						fixed-divider = <2>;
					};

					l4_main_clk: l4_main_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>;
						clk-gate = <0x60 0>;
					};

					l3_main_clk: l3_main_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-perip-clk";
						clocks = <&mainclk>;
						fixed-divider = <1>;
					};

					l3_mp_clk: l3_mp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>;
						div-reg = <0x64 0 2>;
						clk-gate = <0x60 1>;
					};

					l3_sp_clk: l3_sp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>;
						div-reg = <0x64 2 2>;
					};

					l4_mp_clk: l4_mp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>, <&per_base_clk>;
						div-reg = <0x64 4 3>;
						clk-gate = <0x60 2>;
					};

					l4_sp_clk: l4_sp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&mainclk>, <&per_base_clk>;
						div-reg = <0x64 7 3>;
						clk-gate = <0x60 3>;
					};

					dbg_at_clk: dbg_at_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&dbg_base_clk>;
						div-reg = <0x68 0 2>;
						clk-gate = <0x60 4>;
					};

					dbg_clk: dbg_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&dbg_base_clk>;
						div-reg = <0x68 2 2>;
						clk-gate = <0x60 5>;
					};

					dbg_trace_clk: dbg_trace_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&dbg_base_clk>;
						div-reg = <0x6C 0 3>;
						clk-gate = <0x60 6>;
					};

					dbg_timer_clk: dbg_timer_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&dbg_base_clk>;
						clk-gate = <0x60 7>;
					};

					cfg_clk: cfg_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&cfg_h2f_usr0_clk>;
						clk-gate = <0x60 8>;
					};

					h2f_user0_clk: h2f_user0_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&cfg_h2f_usr0_clk>;
						clk-gate = <0x60 9>;
					};

					emac_0_clk: emac_0_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&emac0_clk>;
						clk-gate = <0xa0 0>;
					};

					emac_1_clk: emac_1_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&emac1_clk>;
						clk-gate = <0xa0 1>;
					};

					usb_mp_clk: usb_mp_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 2>;
						div-reg = <0xa4 0 3>;
					};

					spi_m_clk: spi_m_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 3>;
						div-reg = <0xa4 3 3>;
					};

					can0_clk: can0_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 4>;
						div-reg = <0xa4 6 3>;
					};

					can1_clk: can1_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 5>;
						div-reg = <0xa4 9 3>;
					};

					gpio_db_clk: gpio_db_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&per_base_clk>;
						clk-gate = <0xa0 6>;
						div-reg = <0xa8 0 24>;
					};

					h2f_user1_clk: h2f_user1_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&h2f_usr1_clk>;
						clk-gate = <0xa0 7>;
					};

					sdmmc_clk: sdmmc_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
						clk-gate = <0xa0 8>;
						clk-phase = <0 135>;
					};

					nand_x_clk: nand_x_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
						clk-gate = <0xa0 9>;
					};

					nand_clk: nand_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
						clk-gate = <0xa0 10>;
						fixed-divider = <4>;
					};

					qspi_clk: qspi_clk {
						#clock-cells = <0>;
						compatible = "altr,socfpga-gate-clk";
						clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
						clk-gate = <0xa0 11>;
					};
				};
			};

		gmac0: ethernet@ff700000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x60 0>;
			reg = <0xff700000 0x2000>;
			interrupts = <0 115 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
			clocks = <&emac0_clk>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		gmac1: ethernet@ff702000 {
			compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
			altr,sysmgr-syscon = <&sysmgr 0x60 2>;
			reg = <0xff702000 0x2000>;
			interrupts = <0 120 4>;
			interrupt-names = "macirq";
			mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
			clocks = <&emac1_clk>;
			clock-names = "stmmaceth";
			status = "disabled";
		};

		i2c0: i2c@ffc04000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc04000 0x1000>;
			clocks = <&l4_sp_clk>;
			interrupts = <0 158 0x4>;
			status = "disabled";
		};

		i2c1: i2c@ffc05000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc05000 0x1000>;
			clocks = <&l4_sp_clk>;
			interrupts = <0 159 0x4>;
			status = "disabled";
		};

		i2c2: i2c@ffc06000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc06000 0x1000>;
			clocks = <&l4_sp_clk>;
			interrupts = <0 160 0x4>;
			status = "disabled";
		};

		i2c3: i2c@ffc07000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "snps,designware-i2c";
			reg = <0xffc07000 0x1000>;
			clocks = <&l4_sp_clk>;
			interrupts = <0 161 0x4>;
			status = "disabled";
		};

		L2: l2-cache@fffef000 {
			compatible = "arm,pl310-cache";
			reg = <0xfffef000 0x1000>;
			interrupts = <0 38 0x04>;
			cache-unified;
			cache-level = <2>;
			arm,tag-latency = <1 1 1>;
			arm,data-latency = <2 1 1>;
		};

		mmc: dwmmc0@ff704000 {
			compatible = "altr,socfpga-dw-mshc";
			reg = <0xff704000 0x1000>;
			interrupts = <0 139 4>;
			fifo-depth = <0x400>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&l4_mp_clk>, <&sdmmc_clk>;
			clock-names = "biu", "ciu";
		};

		/* Local timer */
		timer@fffec600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xfffec600 0x100>;
			interrupts = <1 13 0xf04>;
			clocks = <&mpu_periph_clk>;
		};

		timer0: timer0@ffc08000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 167 4>;
			reg = <0xffc08000 0x1000>;
			clocks = <&l4_sp_clk>;
			clock-names = "timer";
		};

		timer1: timer1@ffc09000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 168 4>;
			reg = <0xffc09000 0x1000>;
			clocks = <&l4_sp_clk>;
			clock-names = "timer";
		};

		timer2: timer2@ffd00000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 169 4>;
			reg = <0xffd00000 0x1000>;
			clocks = <&osc1>;
			clock-names = "timer";
		};

		timer3: timer3@ffd01000 {
			compatible = "snps,dw-apb-timer";
			interrupts = <0 170 4>;
			reg = <0xffd01000 0x1000>;
			clocks = <&osc1>;
			clock-names = "timer";
		};

		uart0: serial0@ffc02000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc02000 0x1000>;
			interrupts = <0 162 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&l4_sp_clk>;
		};

		uart1: serial1@ffc03000 {
			compatible = "snps,dw-apb-uart";
			reg = <0xffc03000 0x1000>;
			interrupts = <0 163 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&l4_sp_clk>;
		};

		rstmgr@ffd05000 {
			compatible = "altr,rst-mgr";
			reg = <0xffd05000 0x1000>;
		};

		sysmgr: sysmgr@ffd08000 {
			compatible = "altr,sys-mgr", "syscon";
			reg = <0xffd08000 0x4000>;
		};
	};
};
Commit	Line	Data
66314223 DN	1	/*
	2	* Copyright (C) 2012 Altera <www.altera.com>
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	16	*/
	17
7da9b436	18	#include "skeleton.dtsi"
66314223 DN	19
	20	/ {
	21	#address-cells = <1>;
	22	#size-cells = <1>;
	23
	24	aliases {
	25	ethernet0 = &gmac0;
3d954cf1	26	ethernet1 = &gmac1;
66314223 DN	27	serial0 = &uart0;
66314223 DN	28	serial1 = &uart1;
c2ad2844 DN	29	timer0 = &timer0;
	30	timer1 = &timer1;
	31	timer2 = &timer2;
	32	timer3 = &timer3;
66314223 DN	33	};
	34
	35	cpus {
	36	#address-cells = <1>;
	37	#size-cells = <0>;
	38
	39	cpu@0 {
	40	compatible = "arm,cortex-a9";
	41	device_type = "cpu";
	42	reg = <0>;
	43	next-level-cache = <&L2>;
	44	};
	45	cpu@1 {
	46	compatible = "arm,cortex-a9";
	47	device_type = "cpu";
	48	reg = <1>;
	49	next-level-cache = <&L2>;
	50	};
	51	};
	52
	53	intc: intc@fffed000 {
	54	compatible = "arm,cortex-a9-gic";
	55	#interrupt-cells = <3>;
	56	interrupt-controller;
	57	reg = <0xfffed000 0x1000>,
	58	<0xfffec100 0x100>;
	59	};
	60
	61	soc {
	62	#address-cells = <1>;
	63	#size-cells = <1>;
	64	compatible = "simple-bus";
	65	device_type = "soc";
	66	interrupt-parent = <&intc>;
	67	ranges;
	68
	69	amba {
	70	compatible = "arm,amba-bus";
	71	#address-cells = <1>;
	72	#size-cells = <1>;
	73	ranges;
	74
	75	pdma: pdma@ffe01000 {
	76	compatible = "arm,pl330", "arm,primecell";
	77	reg = <0xffe01000 0x1000>;
18d56199 ST	78	interrupts = <0 104 4>,
	79	<0 105 4>,
	80	<0 106 4>,
	81	<0 107 4>,
	82	<0 108 4>,
	83	<0 109 4>,
	84	<0 110 4>,
	85	<0 111 4>;
0d8abbfd PV	86	#dma-cells = <1>;
	87	#dma-channels = <8>;
	88	#dma-requests = <32>;
672ef909 ST	89	clocks = <&l4_main_clk>;
672ef909 ST	90	clock-names = "apb_pclk";
66314223 DN	91	};
	92	};
	93
36fe3f54 ST	94	can0: can@ffc00000 {
	95	compatible = "bosch,d_can";
	96	reg = <0xffc00000 0x1000>;
	97	interrupts = <0 131 4>, <0 132 4>, <0 133 4>, <0 134 4>;
	98	clocks = <&can0_clk>;
	99	status = "disabled";
	100	};
	101
	102	can1: can@ffc01000 {
	103	compatible = "bosch,d_can";
	104	reg = <0xffc01000 0x1000>;
	105	interrupts = <0 135 4>, <0 136 4>, <0 137 4>, <0 138 4>;
	106	clocks = <&can1_clk>;
	107	status = "disabled";
	108	};
	109
042000b0 DN	110	clkmgr@ffd04000 {
	111	compatible = "altr,clk-mgr";
	112	reg = <0xffd04000 0x1000>;
	113
	114	clocks {
	115	#address-cells = <1>;
	116	#size-cells = <0>;
	117
f1ce1a99 DN	118	osc1: osc1 {
	119	#clock-cells = <0>;
	120	compatible = "fixed-clock";
	121	};
	122
	123	osc2: osc2 {
042000b0 DN	124	#clock-cells = <0>;
	125	compatible = "fixed-clock";
	126	};
	127
a92b83af DN	128	f2s_periph_ref_clk: f2s_periph_ref_clk {
	129	#clock-cells = <0>;
	130	compatible = "fixed-clock";
f1ce1a99 DN	131	};
	132
	133	f2s_sdram_ref_clk: f2s_sdram_ref_clk {
	134	#clock-cells = <0>;
	135	compatible = "fixed-clock";
a92b83af DN	136	};
a92b83af DN	137
042000b0 DN	138	main_pll: main_pll {
	139	#address-cells = <1>;
	140	#size-cells = <0>;
	141	#clock-cells = <0>;
	142	compatible = "altr,socfpga-pll-clock";
f1ce1a99	143	clocks = <&osc1>;
042000b0 DN	144	reg = <0x40>;
	145
	146	mpuclk: mpuclk {
	147	#clock-cells = <0>;
	148	compatible = "altr,socfpga-perip-clk";
	149	clocks = <&main_pll>;
	150	fixed-divider = <2>;
	151	reg = <0x48>;
	152	};
	153
	154	mainclk: mainclk {
	155	#clock-cells = <0>;
	156	compatible = "altr,socfpga-perip-clk";
	157	clocks = <&main_pll>;
	158	fixed-divider = <4>;
	159	reg = <0x4C>;
	160	};
	161
	162	dbg_base_clk: dbg_base_clk {
	163	#clock-cells = <0>;
	164	compatible = "altr,socfpga-perip-clk";
	165	clocks = <&main_pll>;
	166	fixed-divider = <4>;
	167	reg = <0x50>;
	168	};
	169
	170	main_qspi_clk: main_qspi_clk {
	171	#clock-cells = <0>;
	172	compatible = "altr,socfpga-perip-clk";
	173	clocks = <&main_pll>;
	174	reg = <0x54>;
	175	};
	176
	177	main_nand_sdmmc_clk: main_nand_sdmmc_clk {
	178	#clock-cells = <0>;
	179	compatible = "altr,socfpga-perip-clk";
	180	clocks = <&main_pll>;
	181	reg = <0x58>;
	182	};
	183
01ed80b0	184	cfg_h2f_usr0_clk: cfg_h2f_usr0_clk {
042000b0 DN	185	#clock-cells = <0>;
	186	compatible = "altr,socfpga-perip-clk";
	187	clocks = <&main_pll>;
	188	reg = <0x5C>;
	189	};
	190	};
	191
	192	periph_pll: periph_pll {
	193	#address-cells = <1>;
	194	#size-cells = <0>;
	195	#clock-cells = <0>;
	196	compatible = "altr,socfpga-pll-clock";
f1ce1a99	197	clocks = <&osc1>, <&osc2>, <&f2s_periph_ref_clk>;
042000b0 DN	198	reg = <0x80>;
	199
	200	emac0_clk: emac0_clk {
	201	#clock-cells = <0>;
	202	compatible = "altr,socfpga-perip-clk";
	203	clocks = <&periph_pll>;
	204	reg = <0x88>;
	205	};
	206
	207	emac1_clk: emac1_clk {
	208	#clock-cells = <0>;
	209	compatible = "altr,socfpga-perip-clk";
	210	clocks = <&periph_pll>;
	211	reg = <0x8C>;
	212	};
	213
	214	per_qspi_clk: per_qsi_clk {
	215	#clock-cells = <0>;
	216	compatible = "altr,socfpga-perip-clk";
	217	clocks = <&periph_pll>;
	218	reg = <0x90>;
	219	};
	220
	221	per_nand_mmc_clk: per_nand_mmc_clk {
	222	#clock-cells = <0>;
	223	compatible = "altr,socfpga-perip-clk";
	224	clocks = <&periph_pll>;
	225	reg = <0x94>;
	226	};
	227
	228	per_base_clk: per_base_clk {
	229	#clock-cells = <0>;
	230	compatible = "altr,socfpga-perip-clk";
	231	clocks = <&periph_pll>;
	232	reg = <0x98>;
	233	};
	234
01ed80b0	235	h2f_usr1_clk: h2f_usr1_clk {
042000b0 DN	236	#clock-cells = <0>;
	237	compatible = "altr,socfpga-perip-clk";
	238	clocks = <&periph_pll>;
	239	reg = <0x9C>;
	240	};
	241	};
	242
	243	sdram_pll: sdram_pll {
	244	#address-cells = <1>;
	245	#size-cells = <0>;
	246	#clock-cells = <0>;
	247	compatible = "altr,socfpga-pll-clock";
f1ce1a99	248	clocks = <&osc1>, <&osc2>, <&f2s_sdram_ref_clk>;
042000b0 DN	249	reg = <0xC0>;
	250
	251	ddr_dqs_clk: ddr_dqs_clk {
	252	#clock-cells = <0>;
	253	compatible = "altr,socfpga-perip-clk";
	254	clocks = <&sdram_pll>;
	255	reg = <0xC8>;
	256	};
	257
	258	ddr_2x_dqs_clk: ddr_2x_dqs_clk {
	259	#clock-cells = <0>;
	260	compatible = "altr,socfpga-perip-clk";
	261	clocks = <&sdram_pll>;
	262	reg = <0xCC>;
	263	};
	264
	265	ddr_dq_clk: ddr_dq_clk {
	266	#clock-cells = <0>;
	267	compatible = "altr,socfpga-perip-clk";
	268	clocks = <&sdram_pll>;
	269	reg = <0xD0>;
	270	};
	271
01ed80b0	272	h2f_usr2_clk: h2f_usr2_clk {
042000b0 DN	273	#clock-cells = <0>;
	274	compatible = "altr,socfpga-perip-clk";
	275	clocks = <&sdram_pll>;
	276	reg = <0xD4>;
	277	};
	278	};
a92b83af	279
7857d560 ST	280	mpu_periph_clk: mpu_periph_clk {
7857d560 ST	281	#clock-cells = <0>;
a5c6e87a	282	compatible = "altr,socfpga-perip-clk";
7857d560 ST	283	clocks = <&mpuclk>;
7857d560 ST	284	fixed-divider = <4>;
a92b83af DN	285	};
a92b83af DN	286
7857d560 ST	287	mpu_l2_ram_clk: mpu_l2_ram_clk {
7857d560 ST	288	#clock-cells = <0>;
a5c6e87a	289	compatible = "altr,socfpga-perip-clk";
7857d560 ST	290	clocks = <&mpuclk>;
7857d560 ST	291	fixed-divider = <2>;
a92b83af DN	292	};
a92b83af DN	293
7857d560 ST	294	l4_main_clk: l4_main_clk {
	295	#clock-cells = <0>;
	296	compatible = "altr,socfpga-gate-clk";
	297	clocks = <&mainclk>;
	298	clk-gate = <0x60 0>;
a92b83af DN	299	};
a92b83af DN	300
7857d560 ST	301	l3_main_clk: l3_main_clk {
7857d560 ST	302	#clock-cells = <0>;
a5c6e87a	303	compatible = "altr,socfpga-perip-clk";
7857d560	304	clocks = <&mainclk>;
a5c6e87a	305	fixed-divider = <1>;
a92b83af DN	306	};
a92b83af DN	307
7857d560 ST	308	l3_mp_clk: l3_mp_clk {
	309	#clock-cells = <0>;
	310	compatible = "altr,socfpga-gate-clk";
	311	clocks = <&mainclk>;
	312	div-reg = <0x64 0 2>;
	313	clk-gate = <0x60 1>;
a92b83af DN	314	};
a92b83af DN	315
7857d560 ST	316	l3_sp_clk: l3_sp_clk {
	317	#clock-cells = <0>;
	318	compatible = "altr,socfpga-gate-clk";
	319	clocks = <&mainclk>;
	320	div-reg = <0x64 2 2>;
	321	};
a92b83af	322
7857d560 ST	323	l4_mp_clk: l4_mp_clk {
	324	#clock-cells = <0>;
	325	compatible = "altr,socfpga-gate-clk";
	326	clocks = <&mainclk>, <&per_base_clk>;
	327	div-reg = <0x64 4 3>;
	328	clk-gate = <0x60 2>;
a92b83af DN	329	};
a92b83af DN	330
7857d560 ST	331	l4_sp_clk: l4_sp_clk {
	332	#clock-cells = <0>;
	333	compatible = "altr,socfpga-gate-clk";
	334	clocks = <&mainclk>, <&per_base_clk>;
	335	div-reg = <0x64 7 3>;
	336	clk-gate = <0x60 3>;
a92b83af DN	337	};
a92b83af DN	338
7857d560 ST	339	dbg_at_clk: dbg_at_clk {
	340	#clock-cells = <0>;
	341	compatible = "altr,socfpga-gate-clk";
	342	clocks = <&dbg_base_clk>;
	343	div-reg = <0x68 0 2>;
	344	clk-gate = <0x60 4>;
a92b83af DN	345	};
a92b83af DN	346
7857d560 ST	347	dbg_clk: dbg_clk {
	348	#clock-cells = <0>;
	349	compatible = "altr,socfpga-gate-clk";
	350	clocks = <&dbg_base_clk>;
	351	div-reg = <0x68 2 2>;
	352	clk-gate = <0x60 5>;
a92b83af DN	353	};
a92b83af DN	354
7857d560 ST	355	dbg_trace_clk: dbg_trace_clk {
	356	#clock-cells = <0>;
	357	compatible = "altr,socfpga-gate-clk";
	358	clocks = <&dbg_base_clk>;
	359	div-reg = <0x6C 0 3>;
	360	clk-gate = <0x60 6>;
a92b83af DN	361	};
a92b83af DN	362
7857d560 ST	363	dbg_timer_clk: dbg_timer_clk {
	364	#clock-cells = <0>;
	365	compatible = "altr,socfpga-gate-clk";
	366	clocks = <&dbg_base_clk>;
	367	clk-gate = <0x60 7>;
a92b83af DN	368	};
a92b83af DN	369
7857d560 ST	370	cfg_clk: cfg_clk {
	371	#clock-cells = <0>;
	372	compatible = "altr,socfpga-gate-clk";
01ed80b0	373	clocks = <&cfg_h2f_usr0_clk>;
7857d560	374	clk-gate = <0x60 8>;
a92b83af DN	375	};
a92b83af DN	376
01ed80b0	377	h2f_user0_clk: h2f_user0_clk {
7857d560 ST	378	#clock-cells = <0>;
7857d560 ST	379	compatible = "altr,socfpga-gate-clk";
01ed80b0	380	clocks = <&cfg_h2f_usr0_clk>;
7857d560	381	clk-gate = <0x60 9>;
a92b83af DN	382	};
a92b83af DN	383
7857d560 ST	384	emac_0_clk: emac_0_clk {
	385	#clock-cells = <0>;
	386	compatible = "altr,socfpga-gate-clk";
	387	clocks = <&emac0_clk>;
	388	clk-gate = <0xa0 0>;
a92b83af DN	389	};
a92b83af DN	390
7857d560 ST	391	emac_1_clk: emac_1_clk {
	392	#clock-cells = <0>;
	393	compatible = "altr,socfpga-gate-clk";
	394	clocks = <&emac1_clk>;
	395	clk-gate = <0xa0 1>;
a92b83af DN	396	};
a92b83af DN	397
7857d560 ST	398	usb_mp_clk: usb_mp_clk {
	399	#clock-cells = <0>;
	400	compatible = "altr,socfpga-gate-clk";
	401	clocks = <&per_base_clk>;
	402	clk-gate = <0xa0 2>;
	403	div-reg = <0xa4 0 3>;
a92b83af DN	404	};
a92b83af DN	405
7857d560 ST	406	spi_m_clk: spi_m_clk {
	407	#clock-cells = <0>;
	408	compatible = "altr,socfpga-gate-clk";
	409	clocks = <&per_base_clk>;
	410	clk-gate = <0xa0 3>;
	411	div-reg = <0xa4 3 3>;
a92b83af DN	412	};
a92b83af DN	413
7857d560 ST	414	can0_clk: can0_clk {
	415	#clock-cells = <0>;
	416	compatible = "altr,socfpga-gate-clk";
	417	clocks = <&per_base_clk>;
	418	clk-gate = <0xa0 4>;
	419	div-reg = <0xa4 6 3>;
a92b83af DN	420	};
a92b83af DN	421
7857d560 ST	422	can1_clk: can1_clk {
	423	#clock-cells = <0>;
	424	compatible = "altr,socfpga-gate-clk";
	425	clocks = <&per_base_clk>;
	426	clk-gate = <0xa0 5>;
	427	div-reg = <0xa4 9 3>;
a92b83af DN	428	};
a92b83af DN	429
7857d560 ST	430	gpio_db_clk: gpio_db_clk {
	431	#clock-cells = <0>;
	432	compatible = "altr,socfpga-gate-clk";
	433	clocks = <&per_base_clk>;
	434	clk-gate = <0xa0 6>;
	435	div-reg = <0xa8 0 24>;
a92b83af DN	436	};
a92b83af DN	437
01ed80b0	438	h2f_user1_clk: h2f_user1_clk {
7857d560 ST	439	#clock-cells = <0>;
7857d560 ST	440	compatible = "altr,socfpga-gate-clk";
01ed80b0	441	clocks = <&h2f_usr1_clk>;
7857d560	442	clk-gate = <0xa0 7>;
a92b83af DN	443	};
a92b83af DN	444
7857d560 ST	445	sdmmc_clk: sdmmc_clk {
	446	#clock-cells = <0>;
	447	compatible = "altr,socfpga-gate-clk";
	448	clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
	449	clk-gate = <0xa0 8>;
044abbde	450	clk-phase = <0 135>;
a92b83af DN	451	};
a92b83af DN	452
7857d560 ST	453	nand_x_clk: nand_x_clk {
	454	#clock-cells = <0>;
	455	compatible = "altr,socfpga-gate-clk";
	456	clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
	457	clk-gate = <0xa0 9>;
a92b83af DN	458	};
a92b83af DN	459
7857d560 ST	460	nand_clk: nand_clk {
	461	#clock-cells = <0>;
	462	compatible = "altr,socfpga-gate-clk";
	463	clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>;
	464	clk-gate = <0xa0 10>;
	465	fixed-divider = <4>;
a92b83af DN	466	};
a92b83af DN	467
7857d560 ST	468	qspi_clk: qspi_clk {
	469	#clock-cells = <0>;
	470	compatible = "altr,socfpga-gate-clk";
	471	clocks = <&f2s_periph_ref_clk>, <&main_qspi_clk>, <&per_qspi_clk>;
	472	clk-gate = <0xa0 11>;
a92b83af	473	};
042000b0 DN	474	};
	475	};
	476
3d954cf1	477	gmac0: ethernet@ff700000 {
66314223	478	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
2755e187	479	altr,sysmgr-syscon = <&sysmgr 0x60 0>;
66314223 DN	480	reg = <0xff700000 0x2000>;
	481	interrupts = <0 115 4>;
	482	interrupt-names = "macirq";
	483	mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
3d954cf1 DN	484	clocks = <&emac0_clk>;
	485	clock-names = "stmmaceth";
	486	status = "disabled";
	487	};
	488
	489	gmac1: ethernet@ff702000 {
	490	compatible = "altr,socfpga-stmmac", "snps,dwmac-3.70a", "snps,dwmac";
2755e187	491	altr,sysmgr-syscon = <&sysmgr 0x60 2>;
3d954cf1 DN	492	reg = <0xff702000 0x2000>;
	493	interrupts = <0 120 4>;
	494	interrupt-names = "macirq";
	495	mac-address = [00 00 00 00 00 00];/* Filled in by U-Boot */
	496	clocks = <&emac1_clk>;
	497	clock-names = "stmmaceth";
	498	status = "disabled";
66314223 DN	499	};
66314223 DN	500
fdeda156 ST	501	i2c0: i2c@ffc04000 {
	502	#address-cells = <1>;
	503	#size-cells = <0>;
	504	compatible = "snps,designware-i2c";
	505	reg = <0xffc04000 0x1000>;
	506	clocks = <&l4_sp_clk>;
	507	interrupts = <0 158 0x4>;
	508	status = "disabled";
	509	};
	510
	511	i2c1: i2c@ffc05000 {
	512	#address-cells = <1>;
	513	#size-cells = <0>;
	514	compatible = "snps,designware-i2c";
	515	reg = <0xffc05000 0x1000>;
	516	clocks = <&l4_sp_clk>;
	517	interrupts = <0 159 0x4>;
	518	status = "disabled";
	519	};
	520
	521	i2c2: i2c@ffc06000 {
	522	#address-cells = <1>;
	523	#size-cells = <0>;
	524	compatible = "snps,designware-i2c";
	525	reg = <0xffc06000 0x1000>;
	526	clocks = <&l4_sp_clk>;
	527	interrupts = <0 160 0x4>;
	528	status = "disabled";
	529	};
	530
	531	i2c3: i2c@ffc07000 {
	532	#address-cells = <1>;
	533	#size-cells = <0>;
	534	compatible = "snps,designware-i2c";
	535	reg = <0xffc07000 0x1000>;
	536	clocks = <&l4_sp_clk>;
	537	interrupts = <0 161 0x4>;
	538	status = "disabled";
	539	};
	540
66314223 DN	541	L2: l2-cache@fffef000 {
	542	compatible = "arm,pl310-cache";
	543	reg = <0xfffef000 0x1000>;
	544	interrupts = <0 38 0x04>;
	545	cache-unified;
	546	cache-level = <2>;
9a21e55d DN	547	arm,tag-latency = <1 1 1>;
9a21e55d DN	548	arm,data-latency = <2 1 1>;
66314223 DN	549	};
66314223 DN	550
9b931361 DN	551	mmc: dwmmc0@ff704000 {
	552	compatible = "altr,socfpga-dw-mshc";
	553	reg = <0xff704000 0x1000>;
	554	interrupts = <0 139 4>;
	555	fifo-depth = <0x400>;
	556	#address-cells = <1>;
	557	#size-cells = <0>;
	558	clocks = <&l4_mp_clk>, <&sdmmc_clk>;
	559	clock-names = "biu", "ciu";
	560	};
	561
66314223 DN	562	/* Local timer */
	563	timer@fffec600 {
	564	compatible = "arm,cortex-a9-twd-timer";
	565	reg = <0xfffec600 0x100>;
	566	interrupts = <1 13 0xf04>;
159c7f89	567	clocks = <&mpu_periph_clk>;
66314223 DN	568	};
66314223 DN	569
c2ad2844	570	timer0: timer0@ffc08000 {
620f5e1c	571	compatible = "snps,dw-apb-timer";
66314223	572	interrupts = <0 167 4>;
66314223	573	reg = <0xffc08000 0x1000>;
bd785efd DN	574	clocks = <&l4_sp_clk>;
bd785efd DN	575	clock-names = "timer";
66314223 DN	576	};
66314223 DN	577
c2ad2844	578	timer1: timer1@ffc09000 {
620f5e1c	579	compatible = "snps,dw-apb-timer";
66314223	580	interrupts = <0 168 4>;
66314223	581	reg = <0xffc09000 0x1000>;
bd785efd DN	582	clocks = <&l4_sp_clk>;
bd785efd DN	583	clock-names = "timer";
66314223 DN	584	};
66314223 DN	585
c2ad2844	586	timer2: timer2@ffd00000 {
620f5e1c	587	compatible = "snps,dw-apb-timer";
66314223	588	interrupts = <0 169 4>;
66314223	589	reg = <0xffd00000 0x1000>;
bd785efd DN	590	clocks = <&osc1>;
bd785efd DN	591	clock-names = "timer";
66314223 DN	592	};
66314223 DN	593
c2ad2844	594	timer3: timer3@ffd01000 {
620f5e1c	595	compatible = "snps,dw-apb-timer";
66314223	596	interrupts = <0 170 4>;
66314223	597	reg = <0xffd01000 0x1000>;
bd785efd DN	598	clocks = <&osc1>;
bd785efd DN	599	clock-names = "timer";
66314223 DN	600	};
66314223 DN	601
c2ad2844	602	uart0: serial0@ffc02000 {
66314223 DN	603	compatible = "snps,dw-apb-uart";
66314223 DN	604	reg = <0xffc02000 0x1000>;
66314223 DN	605	interrupts = <0 162 4>;
	606	reg-shift = <2>;
	607	reg-io-width = <4>;
bd785efd	608	clocks = <&l4_sp_clk>;
66314223 DN	609	};
66314223 DN	610
c2ad2844	611	uart1: serial1@ffc03000 {
66314223 DN	612	compatible = "snps,dw-apb-uart";
66314223 DN	613	reg = <0xffc03000 0x1000>;
66314223 DN	614	interrupts = <0 163 4>;
	615	reg-shift = <2>;
	616	reg-io-width = <4>;
bd785efd	617	clocks = <&l4_sp_clk>;
66314223	618	};
9c4566a1 DN	619
9c4566a1 DN	620	rstmgr@ffd05000 {
7857d560 ST	621	compatible = "altr,rst-mgr";
	622	reg = <0xffd05000 0x1000>;
	623	};
9c4566a1	624
a5d6ac2a	625	sysmgr: sysmgr@ffd08000 {
9b931361 DN	626	compatible = "altr,sys-mgr", "syscon";
	627	reg = <0xffd08000 0x4000>;
	628	};
66314223 DN	629	};
66314223 DN	630	};