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475dc86d DN |
1 | /* |
2 | * Copyright Altera Corporation (C) 2014. All rights reserved. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms and conditions of the GNU General Public License, | |
6 | * version 2, as published by the Free Software Foundation. | |
7 | * | |
8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
11 | * more details. | |
12 | * | |
13 | * You should have received a copy of the GNU General Public License along with | |
14 | * this program. If not, see <http://www.gnu.org/licenses/>. | |
15 | */ | |
16 | ||
17 | #include "skeleton.dtsi" | |
18 | #include <dt-bindings/interrupt-controller/arm-gic.h> | |
19 | ||
20 | / { | |
21 | #address-cells = <1>; | |
22 | #size-cells = <1>; | |
23 | ||
475dc86d DN |
24 | cpus { |
25 | #address-cells = <1>; | |
26 | #size-cells = <0>; | |
ebbce1bb | 27 | enable-method = "altr,socfpga-a10-smp"; |
475dc86d DN |
28 | |
29 | cpu@0 { | |
30 | compatible = "arm,cortex-a9"; | |
31 | device_type = "cpu"; | |
32 | reg = <0>; | |
33 | next-level-cache = <&L2>; | |
34 | }; | |
35 | cpu@1 { | |
36 | compatible = "arm,cortex-a9"; | |
37 | device_type = "cpu"; | |
38 | reg = <1>; | |
39 | next-level-cache = <&L2>; | |
40 | }; | |
41 | }; | |
42 | ||
43 | intc: intc@ffffd000 { | |
44 | compatible = "arm,cortex-a9-gic"; | |
45 | #interrupt-cells = <3>; | |
46 | interrupt-controller; | |
47 | reg = <0xffffd000 0x1000>, | |
48 | <0xffffc100 0x100>; | |
49 | }; | |
50 | ||
51 | soc { | |
52 | #address-cells = <1>; | |
53 | #size-cells = <1>; | |
54 | compatible = "simple-bus"; | |
55 | device_type = "soc"; | |
56 | interrupt-parent = <&intc>; | |
57 | ranges; | |
58 | ||
59 | amba { | |
60 | compatible = "arm,amba-bus"; | |
61 | #address-cells = <1>; | |
62 | #size-cells = <1>; | |
63 | ranges; | |
64 | ||
65 | pdma: pdma@ffda1000 { | |
66 | compatible = "arm,pl330", "arm,primecell"; | |
67 | reg = <0xffda1000 0x1000>; | |
68 | interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>, | |
69 | <0 84 IRQ_TYPE_LEVEL_HIGH>, | |
70 | <0 85 IRQ_TYPE_LEVEL_HIGH>, | |
71 | <0 86 IRQ_TYPE_LEVEL_HIGH>, | |
72 | <0 87 IRQ_TYPE_LEVEL_HIGH>, | |
73 | <0 88 IRQ_TYPE_LEVEL_HIGH>, | |
74 | <0 89 IRQ_TYPE_LEVEL_HIGH>, | |
75 | <0 90 IRQ_TYPE_LEVEL_HIGH>; | |
76 | #dma-cells = <1>; | |
77 | #dma-channels = <8>; | |
78 | #dma-requests = <32>; | |
79 | }; | |
80 | }; | |
81 | ||
82 | clkmgr@ffd04000 { | |
83 | compatible = "altr,clk-mgr"; | |
84 | reg = <0xffd04000 0x1000>; | |
85 | ||
86 | clocks { | |
87 | #address-cells = <1>; | |
88 | #size-cells = <0>; | |
89 | ||
da29d824 DN |
90 | cb_intosc_hs_div2_clk: cb_intosc_hs_div2_clk { |
91 | #clock-cells = <0>; | |
92 | compatible = "fixed-clock"; | |
93 | }; | |
94 | ||
95 | cb_intosc_ls_clk: cb_intosc_ls_clk { | |
96 | #clock-cells = <0>; | |
97 | compatible = "fixed-clock"; | |
98 | }; | |
99 | ||
100 | f2s_free_clk: f2s_free_clk { | |
101 | #clock-cells = <0>; | |
102 | compatible = "fixed-clock"; | |
103 | }; | |
104 | ||
475dc86d DN |
105 | osc1: osc1 { |
106 | #clock-cells = <0>; | |
107 | compatible = "fixed-clock"; | |
108 | }; | |
109 | ||
110 | main_pll: main_pll { | |
111 | #address-cells = <1>; | |
112 | #size-cells = <0>; | |
113 | #clock-cells = <0>; | |
da29d824 DN |
114 | compatible = "altr,socfpga-a10-pll-clock"; |
115 | clocks = <&osc1>, <&cb_intosc_ls_clk>, | |
116 | <&f2s_free_clk>; | |
117 | reg = <0x40>; | |
118 | ||
119 | main_mpu_base_clk: main_mpu_base_clk { | |
120 | #clock-cells = <0>; | |
121 | compatible = "altr,socfpga-a10-perip-clk"; | |
122 | clocks = <&main_pll>; | |
123 | div-reg = <0x140 0 11>; | |
124 | }; | |
125 | ||
126 | main_noc_base_clk: main_noc_base_clk { | |
127 | #clock-cells = <0>; | |
128 | compatible = "altr,socfpga-a10-perip-clk"; | |
129 | clocks = <&main_pll>; | |
130 | div-reg = <0x144 0 11>; | |
131 | }; | |
132 | ||
133 | main_emaca_clk: main_emaca_clk { | |
134 | #clock-cells = <0>; | |
135 | compatible = "altr,socfpga-a10-perip-clk"; | |
136 | clocks = <&main_pll>; | |
137 | reg = <0x68>; | |
138 | }; | |
139 | ||
140 | main_emacb_clk: main_emacb_clk { | |
141 | #clock-cells = <0>; | |
142 | compatible = "altr,socfpga-a10-perip-clk"; | |
143 | clocks = <&main_pll>; | |
144 | reg = <0x6C>; | |
145 | }; | |
146 | ||
147 | main_emac_ptp_clk: main_emac_ptp_clk { | |
148 | #clock-cells = <0>; | |
149 | compatible = "altr,socfpga-a10-perip-clk"; | |
150 | clocks = <&main_pll>; | |
151 | reg = <0x70>; | |
152 | }; | |
153 | ||
154 | main_gpio_db_clk: main_gpio_db_clk { | |
155 | #clock-cells = <0>; | |
156 | compatible = "altr,socfpga-a10-perip-clk"; | |
157 | clocks = <&main_pll>; | |
158 | reg = <0x74>; | |
159 | }; | |
160 | ||
161 | main_sdmmc_clk: main_sdmmc_clk { | |
162 | #clock-cells = <0>; | |
163 | compatible = "altr,socfpga-a10-perip-clk" | |
164 | ; | |
165 | clocks = <&main_pll>; | |
166 | reg = <0x78>; | |
167 | }; | |
168 | ||
169 | main_s2f_usr0_clk: main_s2f_usr0_clk { | |
170 | #clock-cells = <0>; | |
171 | compatible = "altr,socfpga-a10-perip-clk"; | |
172 | clocks = <&main_pll>; | |
173 | reg = <0x7C>; | |
174 | }; | |
175 | ||
176 | main_s2f_usr1_clk: main_s2f_usr1_clk { | |
177 | #clock-cells = <0>; | |
178 | compatible = "altr,socfpga-a10-perip-clk"; | |
179 | clocks = <&main_pll>; | |
180 | reg = <0x80>; | |
181 | }; | |
182 | ||
183 | main_hmc_pll_ref_clk: main_hmc_pll_ref_clk { | |
184 | #clock-cells = <0>; | |
185 | compatible = "altr,socfpga-a10-perip-clk"; | |
186 | clocks = <&main_pll>; | |
187 | reg = <0x84>; | |
188 | }; | |
189 | ||
190 | main_periph_ref_clk: main_periph_ref_clk { | |
191 | #clock-cells = <0>; | |
192 | compatible = "altr,socfpga-a10-perip-clk"; | |
193 | clocks = <&main_pll>; | |
194 | reg = <0x9C>; | |
195 | }; | |
475dc86d DN |
196 | }; |
197 | ||
198 | periph_pll: periph_pll { | |
199 | #address-cells = <1>; | |
200 | #size-cells = <0>; | |
201 | #clock-cells = <0>; | |
da29d824 DN |
202 | compatible = "altr,socfpga-a10-pll-clock"; |
203 | clocks = <&osc1>, <&cb_intosc_ls_clk>, | |
204 | <&f2s_free_clk>, <&main_periph_ref_clk>; | |
205 | reg = <0xC0>; | |
206 | ||
207 | peri_mpu_base_clk: peri_mpu_base_clk { | |
208 | #clock-cells = <0>; | |
209 | compatible = "altr,socfpga-a10-perip-clk"; | |
210 | clocks = <&periph_pll>; | |
211 | div-reg = <0x140 16 11>; | |
212 | }; | |
213 | ||
214 | peri_noc_base_clk: peri_noc_base_clk { | |
215 | #clock-cells = <0>; | |
216 | compatible = "altr,socfpga-a10-perip-clk"; | |
217 | clocks = <&periph_pll>; | |
218 | div-reg = <0x144 16 11>; | |
219 | }; | |
220 | ||
221 | peri_emaca_clk: peri_emaca_clk { | |
222 | #clock-cells = <0>; | |
223 | compatible = "altr,socfpga-a10-perip-clk"; | |
224 | clocks = <&periph_pll>; | |
225 | reg = <0xE8>; | |
226 | }; | |
227 | ||
228 | peri_emacb_clk: peri_emacb_clk { | |
229 | #clock-cells = <0>; | |
230 | compatible = "altr,socfpga-a10-perip-clk"; | |
231 | clocks = <&periph_pll>; | |
232 | reg = <0xEC>; | |
233 | }; | |
234 | ||
235 | peri_emac_ptp_clk: peri_emac_ptp_clk { | |
236 | #clock-cells = <0>; | |
237 | compatible = "altr,socfpga-a10-perip-clk"; | |
238 | clocks = <&periph_pll>; | |
239 | reg = <0xF0>; | |
240 | }; | |
241 | ||
242 | peri_gpio_db_clk: peri_gpio_db_clk { | |
243 | #clock-cells = <0>; | |
244 | compatible = "altr,socfpga-a10-perip-clk"; | |
245 | clocks = <&periph_pll>; | |
246 | reg = <0xF4>; | |
247 | }; | |
248 | ||
249 | peri_sdmmc_clk: peri_sdmmc_clk { | |
250 | #clock-cells = <0>; | |
251 | compatible = "altr,socfpga-a10-perip-clk"; | |
252 | clocks = <&periph_pll>; | |
253 | reg = <0xF8>; | |
254 | }; | |
255 | ||
256 | peri_s2f_usr0_clk: peri_s2f_usr0_clk { | |
257 | #clock-cells = <0>; | |
258 | compatible = "altr,socfpga-a10-perip-clk"; | |
259 | clocks = <&periph_pll>; | |
260 | reg = <0xFC>; | |
261 | }; | |
262 | ||
263 | peri_s2f_usr1_clk: peri_s2f_usr1_clk { | |
264 | #clock-cells = <0>; | |
265 | compatible = "altr,socfpga-a10-perip-clk"; | |
266 | clocks = <&periph_pll>; | |
267 | reg = <0x100>; | |
268 | }; | |
269 | ||
270 | peri_hmc_pll_ref_clk: peri_hmc_pll_ref_clk { | |
271 | #clock-cells = <0>; | |
272 | compatible = "altr,socfpga-a10-perip-clk"; | |
273 | clocks = <&periph_pll>; | |
274 | reg = <0x104>; | |
275 | }; | |
276 | }; | |
277 | ||
278 | mpu_free_clk: mpu_free_clk { | |
279 | #clock-cells = <0>; | |
280 | compatible = "altr,socfpga-a10-perip-clk"; | |
281 | clocks = <&main_mpu_base_clk>, <&peri_mpu_base_clk>, | |
282 | <&osc1>, <&cb_intosc_hs_div2_clk>, | |
283 | <&f2s_free_clk>; | |
284 | reg = <0x60>; | |
285 | }; | |
286 | ||
287 | noc_free_clk: noc_free_clk { | |
288 | #clock-cells = <0>; | |
289 | compatible = "altr,socfpga-a10-perip-clk"; | |
290 | clocks = <&main_noc_base_clk>, <&peri_noc_base_clk>, | |
291 | <&osc1>, <&cb_intosc_hs_div2_clk>, | |
292 | <&f2s_free_clk>; | |
293 | reg = <0x64>; | |
294 | }; | |
295 | ||
296 | s2f_user1_free_clk: s2f_user1_free_clk { | |
297 | #clock-cells = <0>; | |
298 | compatible = "altr,socfpga-a10-perip-clk"; | |
299 | clocks = <&main_s2f_usr1_clk>, <&peri_s2f_usr1_clk>, | |
300 | <&osc1>, <&cb_intosc_hs_div2_clk>, | |
301 | <&f2s_free_clk>; | |
302 | reg = <0x104>; | |
303 | }; | |
304 | ||
305 | sdmmc_free_clk: sdmmc_free_clk { | |
306 | #clock-cells = <0>; | |
307 | compatible = "altr,socfpga-a10-perip-clk"; | |
308 | clocks = <&main_sdmmc_clk>, <&peri_sdmmc_clk>, | |
309 | <&osc1>, <&cb_intosc_hs_div2_clk>, | |
310 | <&f2s_free_clk>; | |
311 | fixed-divider = <4>; | |
312 | reg = <0xF8>; | |
313 | }; | |
314 | ||
315 | l4_sys_free_clk: l4_sys_free_clk { | |
316 | #clock-cells = <0>; | |
317 | compatible = "altr,socfpga-a10-perip-clk"; | |
318 | clocks = <&noc_free_clk>; | |
319 | fixed-divider = <4>; | |
320 | }; | |
321 | ||
322 | l4_main_clk: l4_main_clk { | |
323 | #clock-cells = <0>; | |
324 | compatible = "altr,socfpga-a10-gate-clk"; | |
325 | clocks = <&noc_free_clk>; | |
326 | div-reg = <0xA8 0 2>; | |
327 | clk-gate = <0x48 1>; | |
328 | }; | |
329 | ||
330 | l4_mp_clk: l4_mp_clk { | |
331 | #clock-cells = <0>; | |
332 | compatible = "altr,socfpga-a10-gate-clk"; | |
333 | clocks = <&noc_free_clk>; | |
334 | div-reg = <0xA8 8 2>; | |
335 | clk-gate = <0x48 2>; | |
336 | }; | |
337 | ||
338 | l4_sp_clk: l4_sp_clk { | |
339 | #clock-cells = <0>; | |
340 | compatible = "altr,socfpga-a10-gate-clk"; | |
341 | clocks = <&noc_free_clk>; | |
342 | div-reg = <0xA8 16 2>; | |
343 | clk-gate = <0x48 3>; | |
344 | }; | |
345 | ||
346 | mpu_periph_clk: mpu_periph_clk { | |
347 | #clock-cells = <0>; | |
348 | compatible = "altr,socfpga-a10-gate-clk"; | |
349 | clocks = <&mpu_free_clk>; | |
350 | fixed-divider = <4>; | |
351 | clk-gate = <0x48 0>; | |
352 | }; | |
353 | ||
354 | sdmmc_clk: sdmmc_clk { | |
355 | #clock-cells = <0>; | |
356 | compatible = "altr,socfpga-a10-gate-clk"; | |
357 | clocks = <&sdmmc_free_clk>; | |
358 | clk-gate = <0xC8 5>; | |
359 | }; | |
360 | ||
361 | qspi_clk: qspi_clk { | |
362 | #clock-cells = <0>; | |
363 | compatible = "altr,socfpga-a10-gate-clk"; | |
364 | clocks = <&l4_main_clk>; | |
365 | clk-gate = <0xC8 11>; | |
366 | }; | |
367 | ||
368 | nand_clk: nand_clk { | |
369 | #clock-cells = <0>; | |
370 | compatible = "altr,socfpga-a10-gate-clk"; | |
371 | clocks = <&l4_mp_clk>; | |
372 | clk-gate = <0xC8 10>; | |
373 | }; | |
374 | ||
375 | spi_m_clk: spi_m_clk { | |
376 | #clock-cells = <0>; | |
377 | compatible = "altr,socfpga-a10-gate-clk"; | |
378 | clocks = <&l4_main_clk>; | |
379 | clk-gate = <0xC8 9>; | |
380 | }; | |
381 | ||
382 | usb_clk: usb_clk { | |
383 | #clock-cells = <0>; | |
384 | compatible = "altr,socfpga-a10-gate-clk"; | |
385 | clocks = <&l4_mp_clk>; | |
386 | clk-gate = <0xC8 8>; | |
387 | }; | |
388 | ||
389 | s2f_usr1_clk: s2f_usr1_clk { | |
390 | #clock-cells = <0>; | |
391 | compatible = "altr,socfpga-a10-gate-clk"; | |
392 | clocks = <&peri_s2f_usr1_clk>; | |
393 | clk-gate = <0xC8 6>; | |
475dc86d DN |
394 | }; |
395 | }; | |
396 | }; | |
397 | ||
398 | gmac0: ethernet@ff800000 { | |
399 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
112cadfd | 400 | altr,sysmgr-syscon = <&sysmgr 0x44 0>; |
475dc86d DN |
401 | reg = <0xff800000 0x2000>; |
402 | interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; | |
403 | interrupt-names = "macirq"; | |
404 | /* Filled in by bootloader */ | |
405 | mac-address = [00 00 00 00 00 00]; | |
be9863ca VB |
406 | snps,multicast-filter-bins = <256>; |
407 | snps,perfect-filter-entries = <128>; | |
112cadfd DN |
408 | tx-fifo-depth = <4096>; |
409 | rx-fifo-depth = <16384>; | |
410 | clocks = <&l4_mp_clk>; | |
411 | clock-names = "stmmaceth"; | |
475dc86d DN |
412 | status = "disabled"; |
413 | }; | |
414 | ||
415 | gmac1: ethernet@ff802000 { | |
416 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
112cadfd | 417 | altr,sysmgr-syscon = <&sysmgr 0x48 0>; |
475dc86d DN |
418 | reg = <0xff802000 0x2000>; |
419 | interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; | |
420 | interrupt-names = "macirq"; | |
421 | /* Filled in by bootloader */ | |
422 | mac-address = [00 00 00 00 00 00]; | |
be9863ca VB |
423 | snps,multicast-filter-bins = <256>; |
424 | snps,perfect-filter-entries = <128>; | |
c01e8cdb VB |
425 | tx-fifo-depth = <4096>; |
426 | rx-fifo-depth = <16384>; | |
112cadfd DN |
427 | clocks = <&l4_mp_clk>; |
428 | clock-names = "stmmaceth"; | |
475dc86d DN |
429 | status = "disabled"; |
430 | }; | |
431 | ||
432 | gmac2: ethernet@ff804000 { | |
433 | compatible = "altr,socfpga-stmmac", "snps,dwmac-3.72a", "snps,dwmac"; | |
112cadfd | 434 | altr,sysmgr-syscon = <&sysmgr 0x4C 0>; |
475dc86d DN |
435 | reg = <0xff804000 0x2000>; |
436 | interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; | |
437 | interrupt-names = "macirq"; | |
438 | /* Filled in by bootloader */ | |
439 | mac-address = [00 00 00 00 00 00]; | |
be9863ca VB |
440 | snps,multicast-filter-bins = <256>; |
441 | snps,perfect-filter-entries = <128>; | |
c01e8cdb VB |
442 | tx-fifo-depth = <4096>; |
443 | rx-fifo-depth = <16384>; | |
112cadfd DN |
444 | clocks = <&l4_mp_clk>; |
445 | clock-names = "stmmaceth"; | |
475dc86d DN |
446 | status = "disabled"; |
447 | }; | |
448 | ||
449 | gpio0: gpio@ffc02900 { | |
450 | #address-cells = <1>; | |
451 | #size-cells = <0>; | |
452 | compatible = "snps,dw-apb-gpio"; | |
453 | reg = <0xffc02900 0x100>; | |
454 | status = "disabled"; | |
455 | ||
456 | porta: gpio-controller@0 { | |
457 | compatible = "snps,dw-apb-gpio-port"; | |
458 | gpio-controller; | |
459 | #gpio-cells = <2>; | |
460 | snps,nr-gpios = <29>; | |
461 | reg = <0>; | |
462 | interrupt-controller; | |
463 | #interrupt-cells = <2>; | |
464 | interrupts = <0 112 IRQ_TYPE_LEVEL_HIGH>; | |
465 | }; | |
466 | }; | |
467 | ||
468 | gpio1: gpio@ffc02a00 { | |
469 | #address-cells = <1>; | |
470 | #size-cells = <0>; | |
471 | compatible = "snps,dw-apb-gpio"; | |
472 | reg = <0xffc02a00 0x100>; | |
473 | status = "disabled"; | |
474 | ||
475 | portb: gpio-controller@0 { | |
476 | compatible = "snps,dw-apb-gpio-port"; | |
477 | gpio-controller; | |
478 | #gpio-cells = <2>; | |
479 | snps,nr-gpios = <29>; | |
480 | reg = <0>; | |
481 | interrupt-controller; | |
482 | #interrupt-cells = <2>; | |
483 | interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; | |
484 | }; | |
485 | }; | |
486 | ||
487 | gpio2: gpio@ffc02b00 { | |
488 | #address-cells = <1>; | |
489 | #size-cells = <0>; | |
490 | compatible = "snps,dw-apb-gpio"; | |
491 | reg = <0xffc02b00 0x100>; | |
492 | status = "disabled"; | |
493 | ||
494 | portc: gpio-controller@0 { | |
495 | compatible = "snps,dw-apb-gpio-port"; | |
496 | gpio-controller; | |
497 | #gpio-cells = <2>; | |
498 | snps,nr-gpios = <27>; | |
499 | reg = <0>; | |
500 | interrupt-controller; | |
501 | #interrupt-cells = <2>; | |
502 | interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; | |
503 | }; | |
504 | }; | |
505 | ||
506 | i2c0: i2c@ffc02200 { | |
507 | #address-cells = <1>; | |
508 | #size-cells = <0>; | |
509 | compatible = "snps,designware-i2c"; | |
510 | reg = <0xffc02200 0x100>; | |
511 | interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>; | |
512 | status = "disabled"; | |
513 | }; | |
514 | ||
515 | i2c1: i2c@ffc02300 { | |
516 | #address-cells = <1>; | |
517 | #size-cells = <0>; | |
518 | compatible = "snps,designware-i2c"; | |
519 | reg = <0xffc02300 0x100>; | |
520 | interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; | |
521 | status = "disabled"; | |
522 | }; | |
523 | ||
524 | i2c2: i2c@ffc02400 { | |
525 | #address-cells = <1>; | |
526 | #size-cells = <0>; | |
527 | compatible = "snps,designware-i2c"; | |
528 | reg = <0xffc02400 0x100>; | |
529 | interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>; | |
530 | status = "disabled"; | |
531 | }; | |
532 | ||
533 | i2c3: i2c@ffc02500 { | |
534 | #address-cells = <1>; | |
535 | #size-cells = <0>; | |
536 | compatible = "snps,designware-i2c"; | |
537 | reg = <0xffc02500 0x100>; | |
538 | interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; | |
539 | status = "disabled"; | |
540 | }; | |
541 | ||
542 | i2c4: i2c@ffc02600 { | |
543 | #address-cells = <1>; | |
544 | #size-cells = <0>; | |
545 | compatible = "snps,designware-i2c"; | |
546 | reg = <0xffc02600 0x100>; | |
547 | interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>; | |
548 | status = "disabled"; | |
549 | }; | |
550 | ||
54b4a8f5 TT |
551 | sdr: sdr@ffc25000 { |
552 | compatible = "syscon"; | |
553 | reg = <0xffcfb100 0x80>; | |
554 | }; | |
555 | ||
556 | sdramedac { | |
557 | compatible = "altr,sdram-edac-a10"; | |
558 | altr,sdr-syscon = <&sdr>; | |
559 | interrupts = <0 2 4>, <0 0 4>; | |
560 | }; | |
561 | ||
475dc86d DN |
562 | L2: l2-cache@fffff000 { |
563 | compatible = "arm,pl310-cache"; | |
564 | reg = <0xfffff000 0x1000>; | |
565 | interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>; | |
566 | cache-unified; | |
567 | cache-level = <2>; | |
568 | }; | |
569 | ||
570 | mmc: dwmmc0@ff808000 { | |
571 | #address-cells = <1>; | |
572 | #size-cells = <0>; | |
573 | compatible = "altr,socfpga-dw-mshc"; | |
574 | reg = <0xff808000 0x1000>; | |
575 | interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; | |
576 | fifo-depth = <0x400>; | |
da29d824 DN |
577 | clocks = <&l4_mp_clk>, <&sdmmc_free_clk>; |
578 | clock-names = "biu", "ciu"; | |
1dfb7d2f | 579 | status = "disabled"; |
475dc86d DN |
580 | }; |
581 | ||
582 | ocram: sram@ffe00000 { | |
583 | compatible = "mmio-sram"; | |
584 | reg = <0xffe00000 0x40000>; | |
585 | }; | |
586 | ||
587 | rst: rstmgr@ffd05000 { | |
588 | #reset-cells = <1>; | |
589 | compatible = "altr,rst-mgr"; | |
590 | reg = <0xffd05000 0x100>; | |
591 | }; | |
592 | ||
479f8df0 DN |
593 | scu: snoop-control-unit@ffffc000 { |
594 | compatible = "arm,cortex-a9-scu"; | |
595 | reg = <0xffffc000 0x100>; | |
596 | }; | |
597 | ||
475dc86d DN |
598 | sysmgr: sysmgr@ffd06000 { |
599 | compatible = "altr,sys-mgr", "syscon"; | |
600 | reg = <0xffd06000 0x300>; | |
08d6638f | 601 | cpu1-start-addr = <0xffd06230>; |
475dc86d DN |
602 | }; |
603 | ||
604 | /* Local timer */ | |
605 | timer@ffffc600 { | |
606 | compatible = "arm,cortex-a9-twd-timer"; | |
607 | reg = <0xffffc600 0x100>; | |
608 | interrupts = <1 13 0xf04>; | |
da29d824 | 609 | clocks = <&mpu_periph_clk>; |
475dc86d DN |
610 | }; |
611 | ||
612 | timer0: timer0@ffc02700 { | |
613 | compatible = "snps,dw-apb-timer"; | |
614 | interrupts = <0 115 IRQ_TYPE_LEVEL_HIGH>; | |
615 | reg = <0xffc02700 0x100>; | |
da29d824 DN |
616 | clocks = <&l4_sp_clk>; |
617 | clock-names = "timer"; | |
475dc86d DN |
618 | }; |
619 | ||
620 | timer1: timer1@ffc02800 { | |
621 | compatible = "snps,dw-apb-timer"; | |
622 | interrupts = <0 116 IRQ_TYPE_LEVEL_HIGH>; | |
623 | reg = <0xffc02800 0x100>; | |
da29d824 DN |
624 | clocks = <&l4_sp_clk>; |
625 | clock-names = "timer"; | |
475dc86d DN |
626 | }; |
627 | ||
628 | timer2: timer2@ffd00000 { | |
629 | compatible = "snps,dw-apb-timer"; | |
630 | interrupts = <0 117 IRQ_TYPE_LEVEL_HIGH>; | |
631 | reg = <0xffd00000 0x100>; | |
da29d824 DN |
632 | clocks = <&l4_sys_free_clk>; |
633 | clock-names = "timer"; | |
475dc86d DN |
634 | }; |
635 | ||
636 | timer3: timer3@ffd00100 { | |
637 | compatible = "snps,dw-apb-timer"; | |
638 | interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; | |
639 | reg = <0xffd01000 0x100>; | |
da29d824 DN |
640 | clocks = <&l4_sys_free_clk>; |
641 | clock-names = "timer"; | |
475dc86d DN |
642 | }; |
643 | ||
644 | uart0: serial0@ffc02000 { | |
645 | compatible = "snps,dw-apb-uart"; | |
646 | reg = <0xffc02000 0x100>; | |
647 | interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; | |
648 | reg-shift = <2>; | |
649 | reg-io-width = <4>; | |
1dfb7d2f | 650 | status = "disabled"; |
475dc86d DN |
651 | }; |
652 | ||
653 | uart1: serial1@ffc02100 { | |
654 | compatible = "snps,dw-apb-uart"; | |
655 | reg = <0xffc02100 0x100>; | |
656 | interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; | |
657 | reg-shift = <2>; | |
658 | reg-io-width = <4>; | |
da29d824 | 659 | clocks = <&l4_sp_clk>; |
1dfb7d2f | 660 | status = "disabled"; |
475dc86d DN |
661 | }; |
662 | ||
663 | usbphy0: usbphy@0 { | |
664 | #phy-cells = <0>; | |
665 | compatible = "usb-nop-xceiv"; | |
666 | status = "okay"; | |
667 | }; | |
668 | ||
669 | usb0: usb@ffb00000 { | |
670 | compatible = "snps,dwc2"; | |
671 | reg = <0xffb00000 0xffff>; | |
672 | interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; | |
da29d824 DN |
673 | clocks = <&usb_clk>; |
674 | clock-names = "otg"; | |
475dc86d DN |
675 | phys = <&usbphy0>; |
676 | phy-names = "usb2-phy"; | |
677 | status = "disabled"; | |
678 | }; | |
679 | ||
680 | usb1: usb@ffb40000 { | |
681 | compatible = "snps,dwc2"; | |
682 | reg = <0xffb40000 0xffff>; | |
683 | interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; | |
684 | phys = <&usbphy0>; | |
685 | phy-names = "usb2-phy"; | |
686 | status = "disabled"; | |
687 | }; | |
688 | ||
689 | watchdog0: watchdog@ffd00200 { | |
690 | compatible = "snps,dw-wdt"; | |
691 | reg = <0xffd00200 0x100>; | |
692 | interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>; | |
da29d824 | 693 | clocks = <&l4_sys_free_clk>; |
475dc86d DN |
694 | status = "disabled"; |
695 | }; | |
696 | ||
697 | watchdog1: watchdog@ffd00300 { | |
698 | compatible = "snps,dw-wdt"; | |
699 | reg = <0xffd00300 0x100>; | |
700 | interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>; | |
da29d824 | 701 | clocks = <&l4_sys_free_clk>; |
475dc86d DN |
702 | status = "disabled"; |
703 | }; | |
704 | }; | |
705 | }; |