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9652e8bd SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese <sr@denx.de> | |
3 | * | |
4 | * The code contained herein is licensed under the GNU General Public | |
5 | * License. You may obtain a copy of the GNU General Public License | |
6 | * Version 2 or later at the following locations: | |
7 | * | |
8 | * http://www.opensource.org/licenses/gpl-license.html | |
9 | * http://www.gnu.org/copyleft/gpl.html | |
10 | */ | |
11 | ||
12 | /include/ "skeleton.dtsi" | |
13 | ||
14 | / { | |
15 | compatible = "st,spear600"; | |
16 | ||
17 | cpus { | |
18 | cpu@0 { | |
19 | compatible = "arm,arm926ejs"; | |
20 | }; | |
21 | }; | |
22 | ||
23 | memory { | |
24 | device_type = "memory"; | |
25 | reg = <0 0x40000000>; | |
26 | }; | |
27 | ||
28 | ahb { | |
29 | #address-cells = <1>; | |
30 | #size-cells = <1>; | |
31 | compatible = "simple-bus"; | |
32 | ranges = <0xd0000000 0xd0000000 0x30000000>; | |
33 | ||
34 | vic0: interrupt-controller@f1100000 { | |
35 | compatible = "arm,pl190-vic"; | |
36 | interrupt-controller; | |
37 | reg = <0xf1100000 0x1000>; | |
38 | #interrupt-cells = <1>; | |
39 | }; | |
40 | ||
41 | vic1: interrupt-controller@f1000000 { | |
42 | compatible = "arm,pl190-vic"; | |
43 | interrupt-controller; | |
44 | reg = <0xf1000000 0x1000>; | |
45 | #interrupt-cells = <1>; | |
46 | }; | |
47 | ||
0b7ee717 VK |
48 | dma@fc400000 { |
49 | compatible = "arm,pl080", "arm,primecell"; | |
50 | reg = <0xfc400000 0x1000>; | |
51 | interrupt-parent = <&vic1>; | |
52 | interrupts = <10>; | |
53 | status = "disabled"; | |
54 | }; | |
55 | ||
9652e8bd SR |
56 | gmac: ethernet@e0800000 { |
57 | compatible = "st,spear600-gmac"; | |
58 | reg = <0xe0800000 0x8000>; | |
59 | interrupt-parent = <&vic1>; | |
60 | interrupts = <24 23>; | |
61 | interrupt-names = "macirq", "eth_wake_irq"; | |
62 | status = "disabled"; | |
63 | }; | |
64 | ||
65 | fsmc: flash@d1800000 { | |
66 | compatible = "st,spear600-fsmc-nand"; | |
67 | #address-cells = <1>; | |
68 | #size-cells = <1>; | |
69 | reg = <0xd1800000 0x1000 /* FSMC Register */ | |
70 | 0xd2000000 0x4000>; /* NAND Base */ | |
71 | reg-names = "fsmc_regs", "nand_data"; | |
72 | st,ale-off = <0x20000>; | |
73 | st,cle-off = <0x10000>; | |
74 | status = "disabled"; | |
75 | }; | |
76 | ||
77 | smi: flash@fc000000 { | |
78 | compatible = "st,spear600-smi"; | |
79 | #address-cells = <1>; | |
80 | #size-cells = <1>; | |
81 | reg = <0xfc000000 0x1000>; | |
82 | interrupt-parent = <&vic1>; | |
83 | interrupts = <12>; | |
84 | status = "disabled"; | |
85 | }; | |
86 | ||
87 | ehci@e1800000 { | |
88 | compatible = "st,spear600-ehci", "usb-ehci"; | |
89 | reg = <0xe1800000 0x1000>; | |
90 | interrupt-parent = <&vic1>; | |
91 | interrupts = <27>; | |
92 | status = "disabled"; | |
93 | }; | |
94 | ||
95 | ehci@e2000000 { | |
96 | compatible = "st,spear600-ehci", "usb-ehci"; | |
97 | reg = <0xe2000000 0x1000>; | |
98 | interrupt-parent = <&vic1>; | |
99 | interrupts = <29>; | |
100 | status = "disabled"; | |
101 | }; | |
102 | ||
103 | ohci@e1900000 { | |
104 | compatible = "st,spear600-ohci", "usb-ohci"; | |
105 | reg = <0xe1900000 0x1000>; | |
106 | interrupt-parent = <&vic1>; | |
107 | interrupts = <26>; | |
108 | status = "disabled"; | |
109 | }; | |
110 | ||
111 | ohci@e2100000 { | |
112 | compatible = "st,spear600-ohci", "usb-ohci"; | |
113 | reg = <0xe2100000 0x1000>; | |
114 | interrupt-parent = <&vic1>; | |
115 | interrupts = <28>; | |
116 | status = "disabled"; | |
117 | }; | |
118 | ||
119 | apb { | |
120 | #address-cells = <1>; | |
121 | #size-cells = <1>; | |
122 | compatible = "simple-bus"; | |
123 | ranges = <0xd0000000 0xd0000000 0x30000000>; | |
124 | ||
125 | serial@d0000000 { | |
126 | compatible = "arm,pl011", "arm,primecell"; | |
127 | reg = <0xd0000000 0x1000>; | |
128 | interrupt-parent = <&vic0>; | |
129 | interrupts = <24>; | |
130 | status = "disabled"; | |
131 | }; | |
132 | ||
133 | serial@d0080000 { | |
134 | compatible = "arm,pl011", "arm,primecell"; | |
135 | reg = <0xd0080000 0x1000>; | |
136 | interrupt-parent = <&vic0>; | |
137 | interrupts = <25>; | |
138 | status = "disabled"; | |
139 | }; | |
140 | ||
141 | /* local/cpu GPIO */ | |
142 | gpio0: gpio@f0100000 { | |
143 | #gpio-cells = <2>; | |
144 | compatible = "arm,pl061", "arm,primecell"; | |
145 | gpio-controller; | |
146 | reg = <0xf0100000 0x1000>; | |
147 | interrupt-parent = <&vic0>; | |
148 | interrupts = <18>; | |
149 | }; | |
150 | ||
151 | /* basic GPIO */ | |
152 | gpio1: gpio@fc980000 { | |
153 | #gpio-cells = <2>; | |
154 | compatible = "arm,pl061", "arm,primecell"; | |
155 | gpio-controller; | |
156 | reg = <0xfc980000 0x1000>; | |
157 | interrupt-parent = <&vic1>; | |
158 | interrupts = <19>; | |
159 | }; | |
160 | ||
161 | /* appl GPIO */ | |
162 | gpio2: gpio@d8100000 { | |
163 | #gpio-cells = <2>; | |
164 | compatible = "arm,pl061", "arm,primecell"; | |
165 | gpio-controller; | |
166 | reg = <0xd8100000 0x1000>; | |
167 | interrupt-parent = <&vic1>; | |
168 | interrupts = <4>; | |
169 | }; | |
170 | ||
171 | i2c@d0200000 { | |
172 | #address-cells = <1>; | |
173 | #size-cells = <0>; | |
174 | compatible = "snps,designware-i2c"; | |
175 | reg = <0xd0200000 0x1000>; | |
176 | interrupt-parent = <&vic0>; | |
177 | interrupts = <28>; | |
178 | status = "disabled"; | |
179 | }; | |
30551c01 VK |
180 | |
181 | timer@f0000000 { | |
182 | compatible = "st,spear-timer"; | |
183 | reg = <0xf0000000 0x400>; | |
184 | interrupts = <16>; | |
185 | }; | |
9652e8bd SR |
186 | }; |
187 | }; | |
188 | }; |