Commit | Line | Data |
---|---|---|
f8635abd LW |
1 | /* |
2 | * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC | |
3 | */ | |
3181788c LW |
4 | |
5 | #include <dt-bindings/gpio/gpio.h> | |
6 | #include "skeleton.dtsi" | |
f8635abd LW |
7 | |
8 | / { | |
9 | #address-cells = <1>; | |
10 | #size-cells = <1>; | |
11 | ||
12 | memory { | |
13 | reg = <0x00000000 0x04000000>, | |
14 | <0x08000000 0x04000000>; | |
15 | }; | |
16 | ||
17 | L2: l2-cache { | |
18 | compatible = "arm,l210-cache"; | |
19 | reg = <0x10210000 0x1000>; | |
20 | interrupt-parent = <&vica>; | |
21 | interrupts = <30>; | |
22 | cache-unified; | |
23 | cache-level = <2>; | |
98badfd3 LW |
24 | cache-size = <131072>; |
25 | cache-sets = <512>; | |
26 | cache-line-size = <32>; | |
27 | /* At full speed latency must be >=2 */ | |
a461a3ec LW |
28 | arm,tag-latency = <8>; |
29 | arm,data-latency = <8 8>; | |
30 | arm,dirty-latency = <8>; | |
f8635abd LW |
31 | }; |
32 | ||
7690fbb2 | 33 | mtu0: mtu@101e2000 { |
f8635abd | 34 | /* Nomadik system timer */ |
7690fbb2 | 35 | compatible = "st,nomadik-mtu"; |
f8635abd LW |
36 | reg = <0x101e2000 0x1000>; |
37 | interrupt-parent = <&vica>; | |
38 | interrupts = <4>; | |
7690fbb2 LW |
39 | clocks = <&timclk>, <&pclk>; |
40 | clock-names = "timclk", "apb_pclk"; | |
f8635abd LW |
41 | }; |
42 | ||
7690fbb2 | 43 | mtu1: mtu@101e3000 { |
f8635abd LW |
44 | /* Secondary timer */ |
45 | reg = <0x101e3000 0x1000>; | |
46 | interrupt-parent = <&vica>; | |
47 | interrupts = <5>; | |
7690fbb2 LW |
48 | clocks = <&timclk>, <&pclk>; |
49 | clock-names = "timclk", "apb_pclk"; | |
f8635abd LW |
50 | }; |
51 | ||
6010d403 LW |
52 | gpio0: gpio@101e4000 { |
53 | compatible = "st,nomadik-gpio"; | |
54 | reg = <0x101e4000 0x80>; | |
55 | interrupt-parent = <&vica>; | |
56 | interrupts = <6>; | |
57 | interrupt-controller; | |
58 | #interrupt-cells = <2>; | |
59 | gpio-controller; | |
60 | #gpio-cells = <2>; | |
61 | gpio-bank = <0>; | |
ee04139d | 62 | gpio-ranges = <&pinctrl 0 0 32>; |
6e2b07a1 | 63 | clocks = <&pclk>; |
6010d403 LW |
64 | }; |
65 | ||
66 | gpio1: gpio@101e5000 { | |
67 | compatible = "st,nomadik-gpio"; | |
68 | reg = <0x101e5000 0x80>; | |
69 | interrupt-parent = <&vica>; | |
70 | interrupts = <7>; | |
71 | interrupt-controller; | |
72 | #interrupt-cells = <2>; | |
73 | gpio-controller; | |
74 | #gpio-cells = <2>; | |
75 | gpio-bank = <1>; | |
ee04139d | 76 | gpio-ranges = <&pinctrl 0 32 32>; |
6e2b07a1 | 77 | clocks = <&pclk>; |
6010d403 LW |
78 | }; |
79 | ||
80 | gpio2: gpio@101e6000 { | |
81 | compatible = "st,nomadik-gpio"; | |
82 | reg = <0x101e6000 0x80>; | |
83 | interrupt-parent = <&vica>; | |
84 | interrupts = <8>; | |
85 | interrupt-controller; | |
86 | #interrupt-cells = <2>; | |
87 | gpio-controller; | |
88 | #gpio-cells = <2>; | |
89 | gpio-bank = <2>; | |
ee04139d | 90 | gpio-ranges = <&pinctrl 0 64 32>; |
6e2b07a1 | 91 | clocks = <&pclk>; |
6010d403 LW |
92 | }; |
93 | ||
94 | gpio3: gpio@101e7000 { | |
95 | compatible = "st,nomadik-gpio"; | |
96 | reg = <0x101e7000 0x80>; | |
ee04139d | 97 | ngpio = <28>; |
6010d403 LW |
98 | interrupt-parent = <&vica>; |
99 | interrupts = <9>; | |
100 | interrupt-controller; | |
101 | #interrupt-cells = <2>; | |
102 | gpio-controller; | |
103 | #gpio-cells = <2>; | |
104 | gpio-bank = <3>; | |
ee04139d | 105 | gpio-ranges = <&pinctrl 0 96 28>; |
6e2b07a1 | 106 | clocks = <&pclk>; |
6010d403 LW |
107 | }; |
108 | ||
ee04139d | 109 | pinctrl: pinctrl { |
cdfa9273 | 110 | compatible = "stericsson,stn8815-pinctrl"; |
ee04139d | 111 | nomadik-gpio-chips = <&gpio0>, <&gpio1>, <&gpio2>, <&gpio3>; |
49932f5e | 112 | /* Pin configurations */ |
49932f5e LW |
113 | uart1 { |
114 | uart1_default_mux: uart1_mux { | |
115 | u1_default_mux { | |
68d41f23 LW |
116 | function = "u1"; |
117 | groups = "u1_a_1"; | |
49932f5e LW |
118 | }; |
119 | }; | |
120 | }; | |
121 | mmcsd { | |
122 | mmcsd_default_mux: mmcsd_mux { | |
123 | mmcsd_default_mux { | |
68d41f23 | 124 | function = "mmcsd"; |
c1b30e4d | 125 | groups = "mmcsd_a_1", "mmcsd_b_1"; |
49932f5e LW |
126 | }; |
127 | }; | |
128 | mmcsd_default_mode: mmcsd_default { | |
129 | mmcsd_default_cfg1 { | |
418d5516 LW |
130 | /* |
131 | * MCCLK, MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 | |
132 | * MCCMD, MCDAT3-0, MCMSFBCLK | |
133 | */ | |
134 | pins = "GPIO8_B10", "GPIO9_A10", "GPIO10_C11", "GPIO11_B11", | |
135 | "GPIO12_A11", "GPIO13_C12", "GPIO14_B12", "GPIO15_A12", | |
136 | "GPIO16_C13", "GPIO23_D15", "GPIO24_C15"; | |
137 | ste,output = <2>; | |
49932f5e LW |
138 | }; |
139 | }; | |
140 | }; | |
141 | i2c0 { | |
66e0c12f LW |
142 | i2c0_default_mux: i2c0_mux { |
143 | i2c0_default_mux { | |
68d41f23 LW |
144 | function = "i2c0"; |
145 | groups = "i2c0_a_1"; | |
66e0c12f LW |
146 | }; |
147 | }; | |
49932f5e LW |
148 | i2c0_default_mode: i2c0_default { |
149 | i2c0_default_cfg { | |
1637d480 | 150 | pins = "GPIO62_D3", "GPIO63_D2"; |
66e0c12f | 151 | ste,input = <0>; |
49932f5e LW |
152 | }; |
153 | }; | |
154 | }; | |
155 | i2c1 { | |
66e0c12f LW |
156 | i2c1_default_mux: i2c1_mux { |
157 | i2c1_default_mux { | |
68d41f23 LW |
158 | function = "i2c1"; |
159 | groups = "i2c1_a_1"; | |
66e0c12f LW |
160 | }; |
161 | }; | |
49932f5e LW |
162 | i2c1_default_mode: i2c1_default { |
163 | i2c1_default_cfg { | |
1637d480 | 164 | pins = "GPIO53_L4", "GPIO54_L3"; |
66e0c12f | 165 | ste,input = <0>; |
49932f5e LW |
166 | }; |
167 | }; | |
168 | }; | |
6010d403 LW |
169 | }; |
170 | ||
6e2b07a1 LW |
171 | src: src@101e0000 { |
172 | compatible = "stericsson,nomadik-src"; | |
173 | reg = <0x101e0000 0x1000>; | |
c641d4df LW |
174 | |
175 | /* | |
176 | * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz | |
177 | * that is parent of TIMCLK, PLL1 and PLL2 | |
178 | */ | |
179 | mxtal: mxtal@19.2M { | |
180 | #clock-cells = <0>; | |
181 | compatible = "fixed-clock"; | |
182 | clock-frequency = <19200000>; | |
183 | }; | |
184 | ||
185 | /* | |
186 | * The 2.4 MHz TIMCLK reference clock is active at | |
187 | * boot time, this is actually the MXTALCLK @19.2 MHz | |
188 | * divided by 8. This clock is used by the timers and | |
189 | * watchdog. See page 105 ff. | |
190 | */ | |
191 | timclk: timclk@2.4M { | |
192 | #clock-cells = <0>; | |
193 | compatible = "fixed-factor-clock"; | |
194 | clock-div = <8>; | |
195 | clock-mult = <1>; | |
196 | clocks = <&mxtal>; | |
197 | }; | |
198 | ||
199 | /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ | |
200 | pll1: pll1@0 { | |
201 | #clock-cells = <0>; | |
202 | compatible = "st,nomadik-pll-clock"; | |
203 | pll-id = <1>; | |
204 | clocks = <&mxtal>; | |
205 | }; | |
206 | ||
207 | /* HCLK divides the PLL1 with 1,2,3 or 4 */ | |
208 | hclk: hclk@0 { | |
209 | #clock-cells = <0>; | |
210 | compatible = "st,nomadik-hclk-clock"; | |
211 | clocks = <&pll1>; | |
212 | }; | |
213 | /* The PCLK domain uses HCLK right off */ | |
214 | pclk: pclk@0 { | |
215 | #clock-cells = <0>; | |
216 | compatible = "fixed-factor-clock"; | |
217 | clock-div = <1>; | |
218 | clock-mult = <1>; | |
219 | clocks = <&hclk>; | |
220 | }; | |
221 | ||
222 | /* PLL2 is usually 864 MHz and divided into a few fixed rates */ | |
223 | pll2: pll2@0 { | |
224 | #clock-cells = <0>; | |
225 | compatible = "st,nomadik-pll-clock"; | |
226 | pll-id = <2>; | |
227 | clocks = <&mxtal>; | |
228 | }; | |
229 | clk216: clk216@216M { | |
230 | #clock-cells = <0>; | |
231 | compatible = "fixed-factor-clock"; | |
232 | clock-div = <4>; | |
233 | clock-mult = <1>; | |
234 | clocks = <&pll2>; | |
235 | }; | |
236 | clk108: clk108@108M { | |
237 | #clock-cells = <0>; | |
238 | compatible = "fixed-factor-clock"; | |
239 | clock-div = <2>; | |
240 | clock-mult = <1>; | |
241 | clocks = <&clk216>; | |
242 | }; | |
243 | clk72: clk72@72M { | |
244 | #clock-cells = <0>; | |
245 | compatible = "fixed-factor-clock"; | |
246 | /* The data sheet does not say how this is derived */ | |
247 | clock-div = <12>; | |
248 | clock-mult = <1>; | |
249 | clocks = <&pll2>; | |
250 | }; | |
251 | clk48: clk48@48M { | |
252 | #clock-cells = <0>; | |
253 | compatible = "fixed-factor-clock"; | |
254 | /* The data sheet does not say how this is derived */ | |
255 | clock-div = <18>; | |
256 | clock-mult = <1>; | |
257 | clocks = <&pll2>; | |
258 | }; | |
259 | clk27: clk27@27M { | |
260 | #clock-cells = <0>; | |
261 | compatible = "fixed-factor-clock"; | |
262 | clock-div = <4>; | |
263 | clock-mult = <1>; | |
264 | clocks = <&clk108>; | |
265 | }; | |
266 | ||
267 | /* This apparently exists as well */ | |
268 | ulpiclk: ulpiclk@60M { | |
269 | #clock-cells = <0>; | |
270 | compatible = "fixed-clock"; | |
271 | clock-frequency = <60000000>; | |
272 | }; | |
273 | ||
274 | /* | |
275 | * IP AMBA bus clocks, driving the bus side of the | |
276 | * peripheral clocking, clock gates. | |
277 | */ | |
278 | ||
279 | hclkdma0: hclkdma0@48M { | |
280 | #clock-cells = <0>; | |
281 | compatible = "st,nomadik-src-clock"; | |
282 | clock-id = <0>; | |
283 | clocks = <&hclk>; | |
284 | }; | |
285 | hclksmc: hclksmc@48M { | |
286 | #clock-cells = <0>; | |
287 | compatible = "st,nomadik-src-clock"; | |
288 | clock-id = <1>; | |
289 | clocks = <&hclk>; | |
290 | }; | |
291 | hclksdram: hclksdram@48M { | |
292 | #clock-cells = <0>; | |
293 | compatible = "st,nomadik-src-clock"; | |
294 | clock-id = <2>; | |
295 | clocks = <&hclk>; | |
296 | }; | |
297 | hclkdma1: hclkdma1@48M { | |
298 | #clock-cells = <0>; | |
299 | compatible = "st,nomadik-src-clock"; | |
300 | clock-id = <3>; | |
301 | clocks = <&hclk>; | |
302 | }; | |
303 | hclkclcd: hclkclcd@48M { | |
304 | #clock-cells = <0>; | |
305 | compatible = "st,nomadik-src-clock"; | |
306 | clock-id = <4>; | |
307 | clocks = <&hclk>; | |
308 | }; | |
309 | pclkirda: pclkirda@48M { | |
310 | #clock-cells = <0>; | |
311 | compatible = "st,nomadik-src-clock"; | |
312 | clock-id = <5>; | |
313 | clocks = <&pclk>; | |
314 | }; | |
315 | pclkssp: pclkssp@48M { | |
316 | #clock-cells = <0>; | |
317 | compatible = "st,nomadik-src-clock"; | |
318 | clock-id = <6>; | |
319 | clocks = <&pclk>; | |
320 | }; | |
321 | pclkuart0: pclkuart0@48M { | |
322 | #clock-cells = <0>; | |
323 | compatible = "st,nomadik-src-clock"; | |
324 | clock-id = <7>; | |
325 | clocks = <&pclk>; | |
326 | }; | |
327 | pclksdi: pclksdi@48M { | |
328 | #clock-cells = <0>; | |
329 | compatible = "st,nomadik-src-clock"; | |
330 | clock-id = <8>; | |
331 | clocks = <&pclk>; | |
332 | }; | |
333 | pclki2c0: pclki2c0@48M { | |
334 | #clock-cells = <0>; | |
335 | compatible = "st,nomadik-src-clock"; | |
336 | clock-id = <9>; | |
337 | clocks = <&pclk>; | |
338 | }; | |
339 | pclki2c1: pclki2c1@48M { | |
340 | #clock-cells = <0>; | |
341 | compatible = "st,nomadik-src-clock"; | |
342 | clock-id = <10>; | |
343 | clocks = <&pclk>; | |
344 | }; | |
345 | pclkuart1: pclkuart1@48M { | |
346 | #clock-cells = <0>; | |
347 | compatible = "st,nomadik-src-clock"; | |
348 | clock-id = <11>; | |
349 | clocks = <&pclk>; | |
350 | }; | |
351 | pclkmsp0: pclkmsp0@48M { | |
352 | #clock-cells = <0>; | |
353 | compatible = "st,nomadik-src-clock"; | |
354 | clock-id = <12>; | |
355 | clocks = <&pclk>; | |
356 | }; | |
357 | hclkusb: hclkusb@48M { | |
358 | #clock-cells = <0>; | |
359 | compatible = "st,nomadik-src-clock"; | |
360 | clock-id = <13>; | |
361 | clocks = <&hclk>; | |
362 | }; | |
363 | hclkdif: hclkdif@48M { | |
364 | #clock-cells = <0>; | |
365 | compatible = "st,nomadik-src-clock"; | |
366 | clock-id = <14>; | |
367 | clocks = <&hclk>; | |
368 | }; | |
369 | hclksaa: hclksaa@48M { | |
370 | #clock-cells = <0>; | |
371 | compatible = "st,nomadik-src-clock"; | |
372 | clock-id = <15>; | |
373 | clocks = <&hclk>; | |
374 | }; | |
375 | hclksva: hclksva@48M { | |
376 | #clock-cells = <0>; | |
377 | compatible = "st,nomadik-src-clock"; | |
378 | clock-id = <16>; | |
379 | clocks = <&hclk>; | |
380 | }; | |
381 | pclkhsi: pclkhsi@48M { | |
382 | #clock-cells = <0>; | |
383 | compatible = "st,nomadik-src-clock"; | |
384 | clock-id = <17>; | |
385 | clocks = <&pclk>; | |
386 | }; | |
387 | pclkxti: pclkxti@48M { | |
388 | #clock-cells = <0>; | |
389 | compatible = "st,nomadik-src-clock"; | |
390 | clock-id = <18>; | |
391 | clocks = <&pclk>; | |
392 | }; | |
393 | pclkuart2: pclkuart2@48M { | |
394 | #clock-cells = <0>; | |
395 | compatible = "st,nomadik-src-clock"; | |
396 | clock-id = <19>; | |
397 | clocks = <&pclk>; | |
398 | }; | |
399 | pclkmsp1: pclkmsp1@48M { | |
400 | #clock-cells = <0>; | |
401 | compatible = "st,nomadik-src-clock"; | |
402 | clock-id = <20>; | |
403 | clocks = <&pclk>; | |
404 | }; | |
405 | pclkmsp2: pclkmsp2@48M { | |
406 | #clock-cells = <0>; | |
407 | compatible = "st,nomadik-src-clock"; | |
408 | clock-id = <21>; | |
409 | clocks = <&pclk>; | |
410 | }; | |
411 | pclkowm: pclkowm@48M { | |
412 | #clock-cells = <0>; | |
413 | compatible = "st,nomadik-src-clock"; | |
414 | clock-id = <22>; | |
415 | clocks = <&pclk>; | |
416 | }; | |
417 | hclkhpi: hclkhpi@48M { | |
418 | #clock-cells = <0>; | |
419 | compatible = "st,nomadik-src-clock"; | |
420 | clock-id = <23>; | |
421 | clocks = <&hclk>; | |
422 | }; | |
423 | pclkske: pclkske@48M { | |
424 | #clock-cells = <0>; | |
425 | compatible = "st,nomadik-src-clock"; | |
426 | clock-id = <24>; | |
427 | clocks = <&pclk>; | |
428 | }; | |
429 | pclkhsem: pclkhsem@48M { | |
430 | #clock-cells = <0>; | |
431 | compatible = "st,nomadik-src-clock"; | |
432 | clock-id = <25>; | |
433 | clocks = <&pclk>; | |
434 | }; | |
435 | hclk3d: hclk3d@48M { | |
436 | #clock-cells = <0>; | |
437 | compatible = "st,nomadik-src-clock"; | |
438 | clock-id = <26>; | |
439 | clocks = <&hclk>; | |
440 | }; | |
441 | hclkhash: hclkhash@48M { | |
442 | #clock-cells = <0>; | |
443 | compatible = "st,nomadik-src-clock"; | |
444 | clock-id = <27>; | |
445 | clocks = <&hclk>; | |
446 | }; | |
447 | hclkcryp: hclkcryp@48M { | |
448 | #clock-cells = <0>; | |
449 | compatible = "st,nomadik-src-clock"; | |
450 | clock-id = <28>; | |
451 | clocks = <&hclk>; | |
452 | }; | |
453 | pclkmshc: pclkmshc@48M { | |
454 | #clock-cells = <0>; | |
455 | compatible = "st,nomadik-src-clock"; | |
456 | clock-id = <29>; | |
457 | clocks = <&pclk>; | |
458 | }; | |
459 | hclkusbm: hclkusbm@48M { | |
460 | #clock-cells = <0>; | |
461 | compatible = "st,nomadik-src-clock"; | |
462 | clock-id = <30>; | |
463 | clocks = <&hclk>; | |
464 | }; | |
465 | hclkrng: hclkrng@48M { | |
466 | #clock-cells = <0>; | |
467 | compatible = "st,nomadik-src-clock"; | |
468 | clock-id = <31>; | |
469 | clocks = <&hclk>; | |
470 | }; | |
471 | ||
472 | /* IP kernel clocks */ | |
473 | clcdclk: clcdclk@0 { | |
474 | #clock-cells = <0>; | |
475 | compatible = "st,nomadik-src-clock"; | |
476 | clock-id = <36>; | |
477 | clocks = <&clk72 &clk48>; | |
478 | }; | |
479 | irdaclk: irdaclk@48M { | |
480 | #clock-cells = <0>; | |
481 | compatible = "st,nomadik-src-clock"; | |
482 | clock-id = <37>; | |
483 | clocks = <&clk48>; | |
484 | }; | |
485 | sspiclk: sspiclk@48M { | |
486 | #clock-cells = <0>; | |
487 | compatible = "st,nomadik-src-clock"; | |
488 | clock-id = <38>; | |
489 | clocks = <&clk48>; | |
490 | }; | |
491 | uart0clk: uart0clk@48M { | |
492 | #clock-cells = <0>; | |
493 | compatible = "st,nomadik-src-clock"; | |
494 | clock-id = <39>; | |
495 | clocks = <&clk48>; | |
496 | }; | |
497 | sdiclk: sdiclk@48M { | |
498 | /* Also called MCCLK in some documents */ | |
499 | #clock-cells = <0>; | |
500 | compatible = "st,nomadik-src-clock"; | |
501 | clock-id = <40>; | |
502 | clocks = <&clk48>; | |
503 | }; | |
504 | i2c0clk: i2c0clk@48M { | |
505 | #clock-cells = <0>; | |
506 | compatible = "st,nomadik-src-clock"; | |
507 | clock-id = <41>; | |
508 | clocks = <&clk48>; | |
509 | }; | |
510 | i2c1clk: i2c1clk@48M { | |
511 | #clock-cells = <0>; | |
512 | compatible = "st,nomadik-src-clock"; | |
513 | clock-id = <42>; | |
514 | clocks = <&clk48>; | |
515 | }; | |
516 | uart1clk: uart1clk@48M { | |
517 | #clock-cells = <0>; | |
518 | compatible = "st,nomadik-src-clock"; | |
519 | clock-id = <43>; | |
520 | clocks = <&clk48>; | |
521 | }; | |
522 | mspclk0: mspclk0@48M { | |
523 | #clock-cells = <0>; | |
524 | compatible = "st,nomadik-src-clock"; | |
525 | clock-id = <44>; | |
526 | clocks = <&clk48>; | |
527 | }; | |
528 | usbclk: usbclk@48M { | |
529 | #clock-cells = <0>; | |
530 | compatible = "st,nomadik-src-clock"; | |
531 | clock-id = <45>; | |
532 | clocks = <&clk48>; /* 48 MHz not ULPI */ | |
533 | }; | |
534 | difclk: difclk@72M { | |
535 | #clock-cells = <0>; | |
536 | compatible = "st,nomadik-src-clock"; | |
537 | clock-id = <46>; | |
538 | clocks = <&clk72>; | |
539 | }; | |
540 | ipi2cclk: ipi2cclk@48M { | |
541 | #clock-cells = <0>; | |
542 | compatible = "st,nomadik-src-clock"; | |
543 | clock-id = <47>; | |
544 | clocks = <&clk48>; /* Guess */ | |
545 | }; | |
546 | ipbmcclk: ipbmcclk@48M { | |
547 | #clock-cells = <0>; | |
548 | compatible = "st,nomadik-src-clock"; | |
549 | clock-id = <48>; | |
550 | clocks = <&clk48>; /* Guess */ | |
551 | }; | |
552 | hsiclkrx: hsiclkrx@216M { | |
553 | #clock-cells = <0>; | |
554 | compatible = "st,nomadik-src-clock"; | |
555 | clock-id = <49>; | |
556 | clocks = <&clk216>; | |
557 | }; | |
558 | hsiclktx: hsiclktx@108M { | |
559 | #clock-cells = <0>; | |
560 | compatible = "st,nomadik-src-clock"; | |
561 | clock-id = <50>; | |
562 | clocks = <&clk108>; | |
563 | }; | |
564 | uart2clk: uart2clk@48M { | |
565 | #clock-cells = <0>; | |
566 | compatible = "st,nomadik-src-clock"; | |
567 | clock-id = <51>; | |
568 | clocks = <&clk48>; | |
569 | }; | |
570 | mspclk1: mspclk1@48M { | |
571 | #clock-cells = <0>; | |
572 | compatible = "st,nomadik-src-clock"; | |
573 | clock-id = <52>; | |
574 | clocks = <&clk48>; | |
575 | }; | |
576 | mspclk2: mspclk2@48M { | |
577 | #clock-cells = <0>; | |
578 | compatible = "st,nomadik-src-clock"; | |
579 | clock-id = <53>; | |
580 | clocks = <&clk48>; | |
581 | }; | |
582 | owmclk: owmclk@48M { | |
583 | #clock-cells = <0>; | |
584 | compatible = "st,nomadik-src-clock"; | |
585 | clock-id = <54>; | |
586 | clocks = <&clk48>; /* Guess */ | |
587 | }; | |
588 | skeclk: skeclk@48M { | |
589 | #clock-cells = <0>; | |
590 | compatible = "st,nomadik-src-clock"; | |
591 | clock-id = <56>; | |
592 | clocks = <&clk48>; /* Guess */ | |
593 | }; | |
594 | x3dclk: x3dclk@48M { | |
595 | #clock-cells = <0>; | |
596 | compatible = "st,nomadik-src-clock"; | |
597 | clock-id = <58>; | |
598 | clocks = <&clk48>; /* Guess */ | |
599 | }; | |
600 | pclkmsp3: pclkmsp3@48M { | |
601 | #clock-cells = <0>; | |
602 | compatible = "st,nomadik-src-clock"; | |
603 | clock-id = <59>; | |
604 | clocks = <&pclk>; | |
605 | }; | |
606 | mspclk3: mspclk3@48M { | |
607 | #clock-cells = <0>; | |
608 | compatible = "st,nomadik-src-clock"; | |
609 | clock-id = <60>; | |
610 | clocks = <&clk48>; | |
611 | }; | |
612 | mshcclk: mshcclk@48M { | |
613 | #clock-cells = <0>; | |
614 | compatible = "st,nomadik-src-clock"; | |
615 | clock-id = <61>; | |
616 | clocks = <&clk48>; /* Guess */ | |
617 | }; | |
618 | usbmclk: usbmclk@48M { | |
619 | #clock-cells = <0>; | |
620 | compatible = "st,nomadik-src-clock"; | |
621 | clock-id = <62>; | |
622 | /* Stated as "48 MHz not ULPI clock" */ | |
623 | clocks = <&clk48>; | |
624 | }; | |
625 | rngcclk: rngcclk@48M { | |
626 | #clock-cells = <0>; | |
627 | compatible = "st,nomadik-src-clock"; | |
628 | clock-id = <63>; | |
629 | clocks = <&clk48>; /* Guess */ | |
6e2b07a1 LW |
630 | }; |
631 | }; | |
632 | ||
ba785205 LW |
633 | /* A NAND flash of 128 MiB */ |
634 | fsmc: flash@40000000 { | |
635 | compatible = "stericsson,fsmc-nand"; | |
636 | #address-cells = <1>; | |
637 | #size-cells = <1>; | |
638 | reg = <0x10100000 0x1000>, /* FSMC Register*/ | |
639 | <0x40000000 0x2000>, /* NAND Base DATA */ | |
640 | <0x41000000 0x2000>, /* NAND Base ADDR */ | |
641 | <0x40800000 0x2000>; /* NAND Base CMD */ | |
642 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; | |
c641d4df | 643 | clocks = <&hclksmc>; |
ba785205 | 644 | status = "okay"; |
2c5a7424 | 645 | timings = /bits/ 8 <0 0 0 0x10 0x0a 0>; |
ba785205 LW |
646 | |
647 | partition@0 { | |
648 | label = "X-Loader(NAND)"; | |
649 | reg = <0x0 0x40000>; | |
650 | }; | |
651 | partition@40000 { | |
652 | label = "MemInit(NAND)"; | |
653 | reg = <0x40000 0x40000>; | |
654 | }; | |
655 | partition@80000 { | |
656 | label = "BootLoader(NAND)"; | |
657 | reg = <0x80000 0x200000>; | |
658 | }; | |
659 | partition@280000 { | |
660 | label = "Kernel zImage(NAND)"; | |
661 | reg = <0x280000 0x300000>; | |
662 | }; | |
663 | partition@580000 { | |
664 | label = "Root Filesystem(NAND)"; | |
665 | reg = <0x580000 0x1600000>; | |
666 | }; | |
667 | partition@1b80000 { | |
668 | label = "User Filesystem(NAND)"; | |
669 | reg = <0x1b80000 0x6480000>; | |
670 | }; | |
671 | }; | |
672 | ||
09e02f4d LW |
673 | /* I2C0 connected to the STw4811 power management chip */ |
674 | i2c0 { | |
66e0c12f LW |
675 | compatible = "st,nomadik-i2c", "arm,primecell"; |
676 | reg = <0x101f8000 0x1000>; | |
677 | interrupt-parent = <&vica>; | |
678 | interrupts = <20>; | |
679 | clock-frequency = <100000>; | |
09e02f4d LW |
680 | #address-cells = <1>; |
681 | #size-cells = <0>; | |
66e0c12f LW |
682 | clocks = <&i2c0clk>, <&pclki2c0>; |
683 | clock-names = "mclk", "apb_pclk"; | |
49932f5e | 684 | pinctrl-names = "default"; |
66e0c12f | 685 | pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; |
09e02f4d LW |
686 | |
687 | stw4811@2d { | |
d9f37d9e LW |
688 | compatible = "st,stw4811"; |
689 | reg = <0x2d>; | |
690 | vmmc_regulator: vmmc { | |
691 | compatible = "st,stw481x-vmmc"; | |
692 | regulator-name = "VMMC"; | |
693 | regulator-min-microvolt = <1800000>; | |
694 | regulator-max-microvolt = <3300000>; | |
695 | }; | |
09e02f4d LW |
696 | }; |
697 | }; | |
698 | ||
699 | /* I2C1 connected to various sensors */ | |
700 | i2c1 { | |
66e0c12f LW |
701 | compatible = "st,nomadik-i2c", "arm,primecell"; |
702 | reg = <0x101f7000 0x1000>; | |
703 | interrupt-parent = <&vica>; | |
704 | interrupts = <21>; | |
705 | clock-frequency = <100000>; | |
09e02f4d LW |
706 | #address-cells = <1>; |
707 | #size-cells = <0>; | |
66e0c12f LW |
708 | clocks = <&i2c1clk>, <&pclki2c1>; |
709 | clock-names = "mclk", "apb_pclk"; | |
49932f5e | 710 | pinctrl-names = "default"; |
66e0c12f | 711 | pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; |
09e02f4d LW |
712 | |
713 | camera@2d { | |
714 | compatible = "st,camera"; | |
715 | reg = <0x10>; | |
716 | }; | |
717 | stw5095@1a { | |
718 | compatible = "st,stw5095"; | |
719 | reg = <0x1a>; | |
720 | }; | |
09e02f4d LW |
721 | }; |
722 | ||
f8635abd | 723 | amba { |
2ef7d5f3 | 724 | compatible = "simple-bus"; |
f8635abd LW |
725 | #address-cells = <1>; |
726 | #size-cells = <1>; | |
727 | ranges; | |
728 | ||
30e34001 | 729 | vica: intc@10140000 { |
f8635abd LW |
730 | compatible = "arm,versatile-vic"; |
731 | interrupt-controller; | |
732 | #interrupt-cells = <1>; | |
733 | reg = <0x10140000 0x20>; | |
734 | }; | |
735 | ||
30e34001 | 736 | vicb: intc@10140020 { |
f8635abd LW |
737 | compatible = "arm,versatile-vic"; |
738 | interrupt-controller; | |
739 | #interrupt-cells = <1>; | |
740 | reg = <0x10140020 0x20>; | |
741 | }; | |
742 | ||
743 | uart0: uart@101fd000 { | |
744 | compatible = "arm,pl011", "arm,primecell"; | |
745 | reg = <0x101fd000 0x1000>; | |
746 | interrupt-parent = <&vica>; | |
747 | interrupts = <12>; | |
c641d4df | 748 | clocks = <&uart0clk>, <&pclkuart0>; |
6e2b07a1 | 749 | clock-names = "uartclk", "apb_pclk"; |
a153790a | 750 | status = "disabled"; |
a22d7768 LW |
751 | dmas = <&dmac0 14 1>, |
752 | <&dmac0 15 1>; | |
753 | dma-names = "rx", "tx"; | |
f8635abd LW |
754 | }; |
755 | ||
756 | uart1: uart@101fb000 { | |
757 | compatible = "arm,pl011", "arm,primecell"; | |
758 | reg = <0x101fb000 0x1000>; | |
759 | interrupt-parent = <&vica>; | |
760 | interrupts = <17>; | |
c641d4df | 761 | clocks = <&uart1clk>, <&pclkuart1>; |
6e2b07a1 | 762 | clock-names = "uartclk", "apb_pclk"; |
49932f5e LW |
763 | pinctrl-names = "default"; |
764 | pinctrl-0 = <&uart1_default_mux>; | |
a22d7768 LW |
765 | dmas = <&dmac1 22 1>, |
766 | <&dmac1 23 1>; | |
767 | dma-names = "rx", "tx"; | |
f8635abd LW |
768 | }; |
769 | ||
770 | uart2: uart@101f2000 { | |
771 | compatible = "arm,pl011", "arm,primecell"; | |
772 | reg = <0x101f2000 0x1000>; | |
773 | interrupt-parent = <&vica>; | |
774 | interrupts = <28>; | |
c641d4df | 775 | clocks = <&uart2clk>, <&pclkuart2>; |
6e2b07a1 | 776 | clock-names = "uartclk", "apb_pclk"; |
f8635abd | 777 | status = "disabled"; |
a22d7768 LW |
778 | dmas = <&dmac1 30 1>, |
779 | <&dmac1 31 1>; | |
780 | dma-names = "rx", "tx"; | |
f8635abd | 781 | }; |
27bda036 LW |
782 | |
783 | rng: rng@101b0000 { | |
784 | compatible = "arm,primecell"; | |
785 | reg = <0x101b0000 0x1000>; | |
c641d4df | 786 | clocks = <&rngcclk>, <&hclkrng>; |
6e2b07a1 | 787 | clock-names = "rng", "apb_pclk"; |
27bda036 LW |
788 | }; |
789 | ||
790 | rtc: rtc@101e8000 { | |
791 | compatible = "arm,pl031", "arm,primecell"; | |
792 | reg = <0x101e8000 0x1000>; | |
6e2b07a1 LW |
793 | clocks = <&pclk>; |
794 | clock-names = "apb_pclk"; | |
27bda036 LW |
795 | interrupt-parent = <&vica>; |
796 | interrupts = <10>; | |
797 | }; | |
4fd243c6 LW |
798 | |
799 | mmcsd: sdi@101f6000 { | |
800 | compatible = "arm,pl18x", "arm,primecell"; | |
801 | reg = <0x101f6000 0x1000>; | |
c641d4df | 802 | clocks = <&sdiclk>, <&pclksdi>; |
6e2b07a1 | 803 | clock-names = "mclk", "apb_pclk"; |
4fd243c6 LW |
804 | interrupt-parent = <&vica>; |
805 | interrupts = <22>; | |
418d5516 | 806 | max-frequency = <400000>; |
4fd243c6 | 807 | bus-width = <4>; |
c1bc0e8c UH |
808 | cap-mmc-highspeed; |
809 | cap-sd-highspeed; | |
418d5516 LW |
810 | full-pwr-cycle; |
811 | /* | |
812 | * The STw4811 circuit used with the Nomadik strictly | |
813 | * requires that all of these signal direction pins be | |
814 | * routed and used for its 4-bit levelshifter. | |
815 | */ | |
816 | st,sig-dir-dat0; | |
817 | st,sig-dir-dat2; | |
818 | st,sig-dir-dat31; | |
819 | st,sig-dir-cmd; | |
820 | st,sig-pin-fbclk; | |
49932f5e LW |
821 | pinctrl-names = "default"; |
822 | pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; | |
d9f37d9e | 823 | vmmc-supply = <&vmmc_regulator>; |
4fd243c6 | 824 | }; |
a22d7768 LW |
825 | |
826 | dmac0: dma-controller@10130000 { | |
827 | compatible = "arm,pl080", "arm,primecell"; | |
828 | reg = <0x10130000 0x1000>; | |
829 | interrupt-parent = <&vica>; | |
830 | interrupts = <15>; | |
831 | clocks = <&hclkdma0>; | |
832 | clock-names = "apb_pclk"; | |
833 | lli-bus-interface-ahb1; | |
834 | lli-bus-interface-ahb2; | |
835 | mem-bus-interface-ahb2; | |
836 | memcpy-burst-size = <256>; | |
837 | memcpy-bus-width = <32>; | |
838 | #dma-cells = <2>; | |
839 | }; | |
840 | dmac1: dma-controller@10150000 { | |
841 | compatible = "arm,pl080", "arm,primecell"; | |
842 | reg = <0x10150000 0x1000>; | |
843 | interrupt-parent = <&vica>; | |
844 | interrupts = <13>; | |
845 | clocks = <&hclkdma1>; | |
846 | clock-names = "apb_pclk"; | |
847 | lli-bus-interface-ahb1; | |
848 | lli-bus-interface-ahb2; | |
849 | mem-bus-interface-ahb2; | |
850 | memcpy-burst-size = <256>; | |
851 | memcpy-bus-width = <32>; | |
852 | #dma-cells = <2>; | |
853 | }; | |
f8635abd LW |
854 | }; |
855 | }; |