projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f8635abd LW |
1 | /* |
| 2 | * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC | |
| 3 | */ | |
| 4 | /include/ "skeleton.dtsi" | |
| 5 | ||
| 6 | / { | |
| 7 | #address-cells = <1>; | |
| 8 | #size-cells = <1>; | |
| 9 | ||
| 10 | memory { | |
| 11 | reg = <0x00000000 0x04000000>, | |
| 12 | <0x08000000 0x04000000>; | |
| 13 | }; | |
| 14 | ||
| 15 | L2: l2-cache { | |
| 16 | compatible = "arm,l210-cache"; | |
| 17 | reg = <0x10210000 0x1000>; | |
| 18 | interrupt-parent = <&vica>; | |
| 19 | interrupts = <30>; | |
| 20 | cache-unified; | |
| 21 | cache-level = <2>; | |
| 22 | }; | |
| 23 | ||
| 7690fbb2 | 24 | mtu0: mtu@101e2000 { |
| f8635abd | 25 | /* Nomadik system timer */ |
| 7690fbb2 | 26 | compatible = "st,nomadik-mtu"; |
| f8635abd LW |
27 | reg = <0x101e2000 0x1000>; |
| 28 | interrupt-parent = <&vica>; | |
| 29 | interrupts = <4>; | |
| 7690fbb2 LW |
30 | clocks = <&timclk>, <&pclk>; |
| 31 | clock-names = "timclk", "apb_pclk"; | |
| f8635abd LW |
32 | }; |
| 33 | ||
| 7690fbb2 | 34 | mtu1: mtu@101e3000 { |
| f8635abd LW |
35 | /* Secondary timer */ |
| 36 | reg = <0x101e3000 0x1000>; | |
| 37 | interrupt-parent = <&vica>; | |
| 38 | interrupts = <5>; | |
| 7690fbb2 LW |
39 | clocks = <&timclk>, <&pclk>; |
| 40 | clock-names = "timclk", "apb_pclk"; | |
| f8635abd LW |
41 | }; |
| 42 | ||
| 6010d403 LW |
43 | gpio0: gpio@101e4000 { |
| 44 | compatible = "st,nomadik-gpio"; | |
| 45 | reg = <0x101e4000 0x80>; | |
| 46 | interrupt-parent = <&vica>; | |
| 47 | interrupts = <6>; | |
| 48 | interrupt-controller; | |
| 49 | #interrupt-cells = <2>; | |
| 50 | gpio-controller; | |
| 51 | #gpio-cells = <2>; | |
| 52 | gpio-bank = <0>; | |
| 6e2b07a1 | 53 | clocks = <&pclk>; |
| 6010d403 LW |
54 | }; |
| 55 | ||
| 56 | gpio1: gpio@101e5000 { | |
| 57 | compatible = "st,nomadik-gpio"; | |
| 58 | reg = <0x101e5000 0x80>; | |
| 59 | interrupt-parent = <&vica>; | |
| 60 | interrupts = <7>; | |
| 61 | interrupt-controller; | |
| 62 | #interrupt-cells = <2>; | |
| 63 | gpio-controller; | |
| 64 | #gpio-cells = <2>; | |
| 65 | gpio-bank = <1>; | |
| 6e2b07a1 | 66 | clocks = <&pclk>; |
| 6010d403 LW |
67 | }; |
| 68 | ||
| 69 | gpio2: gpio@101e6000 { | |
| 70 | compatible = "st,nomadik-gpio"; | |
| 71 | reg = <0x101e6000 0x80>; | |
| 72 | interrupt-parent = <&vica>; | |
| 73 | interrupts = <8>; | |
| 74 | interrupt-controller; | |
| 75 | #interrupt-cells = <2>; | |
| 76 | gpio-controller; | |
| 77 | #gpio-cells = <2>; | |
| 78 | gpio-bank = <2>; | |
| 6e2b07a1 | 79 | clocks = <&pclk>; |
| 6010d403 LW |
80 | }; |
| 81 | ||
| 82 | gpio3: gpio@101e7000 { | |
| 83 | compatible = "st,nomadik-gpio"; | |
| 84 | reg = <0x101e7000 0x80>; | |
| 85 | interrupt-parent = <&vica>; | |
| 86 | interrupts = <9>; | |
| 87 | interrupt-controller; | |
| 88 | #interrupt-cells = <2>; | |
| 89 | gpio-controller; | |
| 90 | #gpio-cells = <2>; | |
| 91 | gpio-bank = <3>; | |
| 6e2b07a1 | 92 | clocks = <&pclk>; |
| 6010d403 LW |
93 | }; |
| 94 | ||
| 95 | pinctrl { | |
| 96 | compatible = "stericsson,nmk-pinctrl-stn8815"; | |
| 49932f5e LW |
97 | /* Pin configurations */ |
| 98 | uart0 { | |
| 99 | uart0_default_mux: uart0_mux { | |
| 100 | u0_default_mux { | |
| 101 | ste,function = "u0"; | |
| 102 | ste,pins = "u0_a_1"; | |
| 103 | }; | |
| 104 | }; | |
| 105 | }; | |
| 106 | uart1 { | |
| 107 | uart1_default_mux: uart1_mux { | |
| 108 | u1_default_mux { | |
| 109 | ste,function = "u1"; | |
| 110 | ste,pins = "u1_a_1"; | |
| 111 | }; | |
| 112 | }; | |
| 113 | }; | |
| 114 | mmcsd { | |
| 115 | mmcsd_default_mux: mmcsd_mux { | |
| 116 | mmcsd_default_mux { | |
| 117 | ste,function = "mmcsd"; | |
| 118 | ste,pins = "mmcsd_a_1"; | |
| 119 | }; | |
| 120 | }; | |
| 121 | mmcsd_default_mode: mmcsd_default { | |
| 122 | mmcsd_default_cfg1 { | |
| 123 | /* MCCLK */ | |
| 124 | ste,pins = "GPIO8_B10"; | |
| 125 | ste,output = <0>; | |
| 126 | }; | |
| 127 | mmcsd_default_cfg2 { | |
| 128 | /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ | |
| 129 | ste,pins = "GPIO10_C11", "GPIO15_A12", | |
| 130 | "GPIO16_C13"; | |
| 131 | ste,output = <1>; | |
| 132 | }; | |
| 133 | mmcsd_default_cfg3 { | |
| 134 | /* MCCMD, MCDAT3-0, MCMSFBCLK */ | |
| 135 | ste,pins = "GPIO9_A10", "GPIO11_B11", | |
| 136 | "GPIO12_A11", "GPIO13_C12", | |
| 137 | "GPIO14_B12", "GPIO24_C15"; | |
| 138 | ste,input = <1>; | |
| 139 | }; | |
| 140 | }; | |
| 141 | }; | |
| 142 | i2c0 { | |
| 143 | i2c0_default_mode: i2c0_default { | |
| 144 | i2c0_default_cfg { | |
| 145 | ste,pins = "GPIO62_D3", "GPIO63_D2"; | |
| 146 | ste,input = <1>; | |
| 147 | }; | |
| 148 | }; | |
| 149 | }; | |
| 150 | i2c1 { | |
| 151 | i2c1_default_mode: i2c1_default { | |
| 152 | i2c1_default_cfg { | |
| 153 | ste,pins = "GPIO53_L4", "GPIO54_L3"; | |
| 154 | ste,input = <1>; | |
| 155 | }; | |
| 156 | }; | |
| 157 | }; | |
| 158 | i2c2 { | |
| 159 | i2c2_default_mode: i2c2_default { | |
| 160 | i2c2_default_cfg { | |
| 161 | ste,pins = "GPIO73_C21", "GPIO74_C20"; | |
| 162 | ste,input = <1>; | |
| 163 | }; | |
| 164 | }; | |
| 165 | }; | |
| 6010d403 LW |
166 | }; |
| 167 | ||
| 6e2b07a1 LW |
168 | src: src@101e0000 { |
| 169 | compatible = "stericsson,nomadik-src"; | |
| 170 | reg = <0x101e0000 0x1000>; | |
| 171 | clocks { | |
| 172 | /* | |
| 173 | * Dummy clock for primecells | |
| 174 | */ | |
| 175 | pclk: pclk@0 { | |
| 176 | #clock-cells = <0>; | |
| 177 | compatible = "fixed-clock"; | |
| 7690fbb2 | 178 | clock-frequency = <0>; |
| 6e2b07a1 LW |
179 | }; |
| 180 | /* | |
| 181 | * The 2.4 MHz TIMCLK reference clock is active at | |
| 182 | * boot time, this is actually the MXTALCLK @19.2 MHz | |
| 183 | * divided by 8. This clock is used by the timers and | |
| 184 | * watchdog. See page 105 ff. | |
| 185 | */ | |
| 186 | timclk: timclk@2.4M { | |
| 187 | #clock-cells = <0>; | |
| 188 | compatible = "fixed-clock"; | |
| 189 | clock-frequency = <2400000>; | |
| 190 | }; | |
| 191 | /* | |
| 192 | * At boot time, PLL2 is set to generate a set of | |
| 193 | * fixed clocks, one of them is CLK48, the 48 MHz | |
| 194 | * clock, routed to the UART, MMC/SD, I2C, IrDA, | |
| 195 | * USB and SSP blocks. | |
| 196 | */ | |
| 197 | clk48: clk48@48M { | |
| 198 | #clock-cells = <0>; | |
| 199 | compatible = "fixed-clock"; | |
| 200 | clock-frequency = <48000000>; | |
| 201 | }; | |
| 202 | }; | |
| 203 | }; | |
| 204 | ||
| ba785205 LW |
205 | /* A NAND flash of 128 MiB */ |
| 206 | fsmc: flash@40000000 { | |
| 207 | compatible = "stericsson,fsmc-nand"; | |
| 208 | #address-cells = <1>; | |
| 209 | #size-cells = <1>; | |
| 210 | reg = <0x10100000 0x1000>, /* FSMC Register*/ | |
| 211 | <0x40000000 0x2000>, /* NAND Base DATA */ | |
| 212 | <0x41000000 0x2000>, /* NAND Base ADDR */ | |
| 213 | <0x40800000 0x2000>; /* NAND Base CMD */ | |
| 214 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; | |
| 6e2b07a1 | 215 | clocks = <&pclk>; |
| ba785205 LW |
216 | status = "okay"; |
| 217 | ||
| 218 | partition@0 { | |
| 219 | label = "X-Loader(NAND)"; | |
| 220 | reg = <0x0 0x40000>; | |
| 221 | }; | |
| 222 | partition@40000 { | |
| 223 | label = "MemInit(NAND)"; | |
| 224 | reg = <0x40000 0x40000>; | |
| 225 | }; | |
| 226 | partition@80000 { | |
| 227 | label = "BootLoader(NAND)"; | |
| 228 | reg = <0x80000 0x200000>; | |
| 229 | }; | |
| 230 | partition@280000 { | |
| 231 | label = "Kernel zImage(NAND)"; | |
| 232 | reg = <0x280000 0x300000>; | |
| 233 | }; | |
| 234 | partition@580000 { | |
| 235 | label = "Root Filesystem(NAND)"; | |
| 236 | reg = <0x580000 0x1600000>; | |
| 237 | }; | |
| 238 | partition@1b80000 { | |
| 239 | label = "User Filesystem(NAND)"; | |
| 240 | reg = <0x1b80000 0x6480000>; | |
| 241 | }; | |
| 242 | }; | |
| 243 | ||
| 2ad6e398 LW |
244 | external-bus@34000000 { |
| 245 | compatible = "simple-bus"; | |
| 246 | reg = <0x34000000 0x1000000>; | |
| 247 | #address-cells = <1>; | |
| 248 | #size-cells = <1>; | |
| 249 | ranges = <0 0x34000000 0x1000000>; | |
| 250 | ethernet@300 { | |
| 251 | compatible = "smsc,lan91c111"; | |
| 252 | reg = <0x300 0x0fd00>; | |
| 253 | }; | |
| 254 | }; | |
| 255 | ||
| 09e02f4d LW |
256 | /* I2C0 connected to the STw4811 power management chip */ |
| 257 | i2c0 { | |
| 258 | compatible = "i2c-gpio"; | |
| 259 | gpios = <&gpio1 31 0>, /* sda */ | |
| 260 | <&gpio1 30 0>; /* scl */ | |
| 261 | #address-cells = <1>; | |
| 262 | #size-cells = <0>; | |
| 49932f5e LW |
263 | pinctrl-names = "default"; |
| 264 | pinctrl-0 = <&i2c0_default_mode>; | |
| 09e02f4d LW |
265 | |
| 266 | stw4811@2d { | |
| 267 | compatible = "st,stw4811"; | |
| 268 | reg = <0x2d>; | |
| 269 | }; | |
| 270 | }; | |
| 271 | ||
| 272 | /* I2C1 connected to various sensors */ | |
| 273 | i2c1 { | |
| 274 | compatible = "i2c-gpio"; | |
| 275 | gpios = <&gpio1 22 0>, /* sda */ | |
| 276 | <&gpio1 21 0>; /* scl */ | |
| 277 | #address-cells = <1>; | |
| 278 | #size-cells = <0>; | |
| 49932f5e LW |
279 | pinctrl-names = "default"; |
| 280 | pinctrl-0 = <&i2c1_default_mode>; | |
| 09e02f4d LW |
281 | |
| 282 | camera@2d { | |
| 283 | compatible = "st,camera"; | |
| 284 | reg = <0x10>; | |
| 285 | }; | |
| 286 | stw5095@1a { | |
| 287 | compatible = "st,stw5095"; | |
| 288 | reg = <0x1a>; | |
| 289 | }; | |
| 290 | lis3lv02dl@1d { | |
| 291 | compatible = "st,lis3lv02dl"; | |
| 292 | reg = <0x1d>; | |
| 293 | }; | |
| 294 | }; | |
| 295 | ||
| 296 | /* I2C2 connected to the USB portions of the STw4811 only */ | |
| 297 | i2c2 { | |
| 298 | compatible = "i2c-gpio"; | |
| 299 | gpios = <&gpio2 10 0>, /* sda */ | |
| 300 | <&gpio2 9 0>; /* scl */ | |
| 301 | #address-cells = <1>; | |
| 302 | #size-cells = <0>; | |
| 49932f5e LW |
303 | pinctrl-names = "default"; |
| 304 | pinctrl-0 = <&i2c2_default_mode>; | |
| 305 | ||
| 09e02f4d LW |
306 | stw4811@2d { |
| 307 | compatible = "st,stw4811-usb"; | |
| 308 | reg = <0x2d>; | |
| 309 | }; | |
| 310 | }; | |
| 311 | ||
| f8635abd LW |
312 | amba { |
| 313 | compatible = "arm,amba-bus"; | |
| 314 | #address-cells = <1>; | |
| 315 | #size-cells = <1>; | |
| 316 | ranges; | |
| 317 | ||
| 318 | vica: intc@0x10140000 { | |
| 319 | compatible = "arm,versatile-vic"; | |
| 320 | interrupt-controller; | |
| 321 | #interrupt-cells = <1>; | |
| 322 | reg = <0x10140000 0x20>; | |
| 323 | }; | |
| 324 | ||
| 325 | vicb: intc@0x10140020 { | |
| 326 | compatible = "arm,versatile-vic"; | |
| 327 | interrupt-controller; | |
| 328 | #interrupt-cells = <1>; | |
| 329 | reg = <0x10140020 0x20>; | |
| 330 | }; | |
| 331 | ||
| 332 | uart0: uart@101fd000 { | |
| 333 | compatible = "arm,pl011", "arm,primecell"; | |
| 334 | reg = <0x101fd000 0x1000>; | |
| 335 | interrupt-parent = <&vica>; | |
| 336 | interrupts = <12>; | |
| 6e2b07a1 LW |
337 | clocks = <&clk48>, <&pclk>; |
| 338 | clock-names = "uartclk", "apb_pclk"; | |
| 49932f5e LW |
339 | pinctrl-names = "default"; |
| 340 | pinctrl-0 = <&uart0_default_mux>; | |
| f8635abd LW |
341 | }; |
| 342 | ||
| 343 | uart1: uart@101fb000 { | |
| 344 | compatible = "arm,pl011", "arm,primecell"; | |
| 345 | reg = <0x101fb000 0x1000>; | |
| 346 | interrupt-parent = <&vica>; | |
| 347 | interrupts = <17>; | |
| 6e2b07a1 LW |
348 | clocks = <&clk48>, <&pclk>; |
| 349 | clock-names = "uartclk", "apb_pclk"; | |
| 49932f5e LW |
350 | pinctrl-names = "default"; |
| 351 | pinctrl-0 = <&uart1_default_mux>; | |
| f8635abd LW |
352 | }; |
| 353 | ||
| 354 | uart2: uart@101f2000 { | |
| 355 | compatible = "arm,pl011", "arm,primecell"; | |
| 356 | reg = <0x101f2000 0x1000>; | |
| 357 | interrupt-parent = <&vica>; | |
| 358 | interrupts = <28>; | |
| 6e2b07a1 LW |
359 | clocks = <&clk48>, <&pclk>; |
| 360 | clock-names = "uartclk", "apb_pclk"; | |
| f8635abd LW |
361 | status = "disabled"; |
| 362 | }; | |
| 27bda036 LW |
363 | |
| 364 | rng: rng@101b0000 { | |
| 365 | compatible = "arm,primecell"; | |
| 366 | reg = <0x101b0000 0x1000>; | |
| 6e2b07a1 LW |
367 | clocks = <&clk48>, <&pclk>; |
| 368 | clock-names = "rng", "apb_pclk"; | |
| 27bda036 LW |
369 | }; |
| 370 | ||
| 371 | rtc: rtc@101e8000 { | |
| 372 | compatible = "arm,pl031", "arm,primecell"; | |
| 373 | reg = <0x101e8000 0x1000>; | |
| 6e2b07a1 LW |
374 | clocks = <&pclk>; |
| 375 | clock-names = "apb_pclk"; | |
| 27bda036 LW |
376 | interrupt-parent = <&vica>; |
| 377 | interrupts = <10>; | |
| 378 | }; | |
| 4fd243c6 LW |
379 | |
| 380 | mmcsd: sdi@101f6000 { | |
| 381 | compatible = "arm,pl18x", "arm,primecell"; | |
| 382 | reg = <0x101f6000 0x1000>; | |
| 6e2b07a1 LW |
383 | clocks = <&clk48>, <&pclk>; |
| 384 | clock-names = "mclk", "apb_pclk"; | |
| 4fd243c6 LW |
385 | interrupt-parent = <&vica>; |
| 386 | interrupts = <22>; | |
| 387 | max-frequency = <48000000>; | |
| 388 | bus-width = <4>; | |
| 389 | mmc-cap-mmc-highspeed; | |
| 390 | mmc-cap-sd-highspeed; | |
| 391 | cd-gpios = <&gpio3 15 0x1>; | |
| 392 | cd-inverted; | |
| 49932f5e LW |
393 | pinctrl-names = "default"; |
| 394 | pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; | |
| 4fd243c6 | 395 | }; |
| f8635abd LW |
396 | }; |
| 397 | }; |