Commit | Line | Data |
---|---|---|
f8635abd LW |
1 | /* |
2 | * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC | |
3 | */ | |
3181788c LW |
4 | |
5 | #include <dt-bindings/gpio/gpio.h> | |
6 | #include "skeleton.dtsi" | |
f8635abd LW |
7 | |
8 | / { | |
9 | #address-cells = <1>; | |
10 | #size-cells = <1>; | |
11 | ||
12 | memory { | |
13 | reg = <0x00000000 0x04000000>, | |
14 | <0x08000000 0x04000000>; | |
15 | }; | |
16 | ||
17 | L2: l2-cache { | |
18 | compatible = "arm,l210-cache"; | |
19 | reg = <0x10210000 0x1000>; | |
20 | interrupt-parent = <&vica>; | |
21 | interrupts = <30>; | |
22 | cache-unified; | |
23 | cache-level = <2>; | |
24 | }; | |
25 | ||
7690fbb2 | 26 | mtu0: mtu@101e2000 { |
f8635abd | 27 | /* Nomadik system timer */ |
7690fbb2 | 28 | compatible = "st,nomadik-mtu"; |
f8635abd LW |
29 | reg = <0x101e2000 0x1000>; |
30 | interrupt-parent = <&vica>; | |
31 | interrupts = <4>; | |
7690fbb2 LW |
32 | clocks = <&timclk>, <&pclk>; |
33 | clock-names = "timclk", "apb_pclk"; | |
f8635abd LW |
34 | }; |
35 | ||
7690fbb2 | 36 | mtu1: mtu@101e3000 { |
f8635abd LW |
37 | /* Secondary timer */ |
38 | reg = <0x101e3000 0x1000>; | |
39 | interrupt-parent = <&vica>; | |
40 | interrupts = <5>; | |
7690fbb2 LW |
41 | clocks = <&timclk>, <&pclk>; |
42 | clock-names = "timclk", "apb_pclk"; | |
f8635abd LW |
43 | }; |
44 | ||
6010d403 LW |
45 | gpio0: gpio@101e4000 { |
46 | compatible = "st,nomadik-gpio"; | |
47 | reg = <0x101e4000 0x80>; | |
48 | interrupt-parent = <&vica>; | |
49 | interrupts = <6>; | |
50 | interrupt-controller; | |
51 | #interrupt-cells = <2>; | |
52 | gpio-controller; | |
53 | #gpio-cells = <2>; | |
54 | gpio-bank = <0>; | |
6e2b07a1 | 55 | clocks = <&pclk>; |
6010d403 LW |
56 | }; |
57 | ||
58 | gpio1: gpio@101e5000 { | |
59 | compatible = "st,nomadik-gpio"; | |
60 | reg = <0x101e5000 0x80>; | |
61 | interrupt-parent = <&vica>; | |
62 | interrupts = <7>; | |
63 | interrupt-controller; | |
64 | #interrupt-cells = <2>; | |
65 | gpio-controller; | |
66 | #gpio-cells = <2>; | |
67 | gpio-bank = <1>; | |
6e2b07a1 | 68 | clocks = <&pclk>; |
6010d403 LW |
69 | }; |
70 | ||
71 | gpio2: gpio@101e6000 { | |
72 | compatible = "st,nomadik-gpio"; | |
73 | reg = <0x101e6000 0x80>; | |
74 | interrupt-parent = <&vica>; | |
75 | interrupts = <8>; | |
76 | interrupt-controller; | |
77 | #interrupt-cells = <2>; | |
78 | gpio-controller; | |
79 | #gpio-cells = <2>; | |
80 | gpio-bank = <2>; | |
6e2b07a1 | 81 | clocks = <&pclk>; |
6010d403 LW |
82 | }; |
83 | ||
84 | gpio3: gpio@101e7000 { | |
85 | compatible = "st,nomadik-gpio"; | |
86 | reg = <0x101e7000 0x80>; | |
87 | interrupt-parent = <&vica>; | |
88 | interrupts = <9>; | |
89 | interrupt-controller; | |
90 | #interrupt-cells = <2>; | |
91 | gpio-controller; | |
92 | #gpio-cells = <2>; | |
93 | gpio-bank = <3>; | |
6e2b07a1 | 94 | clocks = <&pclk>; |
6010d403 LW |
95 | }; |
96 | ||
97 | pinctrl { | |
cdfa9273 | 98 | compatible = "stericsson,stn8815-pinctrl"; |
49932f5e LW |
99 | /* Pin configurations */ |
100 | uart0 { | |
101 | uart0_default_mux: uart0_mux { | |
102 | u0_default_mux { | |
103 | ste,function = "u0"; | |
104 | ste,pins = "u0_a_1"; | |
105 | }; | |
106 | }; | |
107 | }; | |
108 | uart1 { | |
109 | uart1_default_mux: uart1_mux { | |
110 | u1_default_mux { | |
111 | ste,function = "u1"; | |
112 | ste,pins = "u1_a_1"; | |
113 | }; | |
114 | }; | |
115 | }; | |
116 | mmcsd { | |
117 | mmcsd_default_mux: mmcsd_mux { | |
118 | mmcsd_default_mux { | |
119 | ste,function = "mmcsd"; | |
120 | ste,pins = "mmcsd_a_1"; | |
121 | }; | |
122 | }; | |
123 | mmcsd_default_mode: mmcsd_default { | |
124 | mmcsd_default_cfg1 { | |
125 | /* MCCLK */ | |
126 | ste,pins = "GPIO8_B10"; | |
127 | ste,output = <0>; | |
128 | }; | |
129 | mmcsd_default_cfg2 { | |
130 | /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR */ | |
131 | ste,pins = "GPIO10_C11", "GPIO15_A12", | |
132 | "GPIO16_C13"; | |
133 | ste,output = <1>; | |
134 | }; | |
135 | mmcsd_default_cfg3 { | |
136 | /* MCCMD, MCDAT3-0, MCMSFBCLK */ | |
137 | ste,pins = "GPIO9_A10", "GPIO11_B11", | |
138 | "GPIO12_A11", "GPIO13_C12", | |
139 | "GPIO14_B12", "GPIO24_C15"; | |
140 | ste,input = <1>; | |
141 | }; | |
142 | }; | |
143 | }; | |
144 | i2c0 { | |
66e0c12f LW |
145 | i2c0_default_mux: i2c0_mux { |
146 | i2c0_default_mux { | |
147 | ste,function = "i2c0"; | |
148 | ste,pins = "i2c0_a_1"; | |
149 | }; | |
150 | }; | |
49932f5e LW |
151 | i2c0_default_mode: i2c0_default { |
152 | i2c0_default_cfg { | |
153 | ste,pins = "GPIO62_D3", "GPIO63_D2"; | |
66e0c12f | 154 | ste,input = <0>; |
49932f5e LW |
155 | }; |
156 | }; | |
157 | }; | |
158 | i2c1 { | |
66e0c12f LW |
159 | i2c1_default_mux: i2c1_mux { |
160 | i2c1_default_mux { | |
161 | ste,function = "i2c1"; | |
162 | ste,pins = "i2c1_a_1"; | |
163 | }; | |
164 | }; | |
49932f5e LW |
165 | i2c1_default_mode: i2c1_default { |
166 | i2c1_default_cfg { | |
167 | ste,pins = "GPIO53_L4", "GPIO54_L3"; | |
66e0c12f | 168 | ste,input = <0>; |
49932f5e LW |
169 | }; |
170 | }; | |
171 | }; | |
172 | i2c2 { | |
173 | i2c2_default_mode: i2c2_default { | |
174 | i2c2_default_cfg { | |
175 | ste,pins = "GPIO73_C21", "GPIO74_C20"; | |
66e0c12f | 176 | ste,input = <0>; |
49932f5e LW |
177 | }; |
178 | }; | |
179 | }; | |
6010d403 LW |
180 | }; |
181 | ||
6e2b07a1 LW |
182 | src: src@101e0000 { |
183 | compatible = "stericsson,nomadik-src"; | |
184 | reg = <0x101e0000 0x1000>; | |
c641d4df LW |
185 | disable-sxtalo; |
186 | disable-mxtalo; | |
187 | ||
188 | /* | |
189 | * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz | |
190 | * that is parent of TIMCLK, PLL1 and PLL2 | |
191 | */ | |
192 | mxtal: mxtal@19.2M { | |
193 | #clock-cells = <0>; | |
194 | compatible = "fixed-clock"; | |
195 | clock-frequency = <19200000>; | |
196 | }; | |
197 | ||
198 | /* | |
199 | * The 2.4 MHz TIMCLK reference clock is active at | |
200 | * boot time, this is actually the MXTALCLK @19.2 MHz | |
201 | * divided by 8. This clock is used by the timers and | |
202 | * watchdog. See page 105 ff. | |
203 | */ | |
204 | timclk: timclk@2.4M { | |
205 | #clock-cells = <0>; | |
206 | compatible = "fixed-factor-clock"; | |
207 | clock-div = <8>; | |
208 | clock-mult = <1>; | |
209 | clocks = <&mxtal>; | |
210 | }; | |
211 | ||
212 | /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ | |
213 | pll1: pll1@0 { | |
214 | #clock-cells = <0>; | |
215 | compatible = "st,nomadik-pll-clock"; | |
216 | pll-id = <1>; | |
217 | clocks = <&mxtal>; | |
218 | }; | |
219 | ||
220 | /* HCLK divides the PLL1 with 1,2,3 or 4 */ | |
221 | hclk: hclk@0 { | |
222 | #clock-cells = <0>; | |
223 | compatible = "st,nomadik-hclk-clock"; | |
224 | clocks = <&pll1>; | |
225 | }; | |
226 | /* The PCLK domain uses HCLK right off */ | |
227 | pclk: pclk@0 { | |
228 | #clock-cells = <0>; | |
229 | compatible = "fixed-factor-clock"; | |
230 | clock-div = <1>; | |
231 | clock-mult = <1>; | |
232 | clocks = <&hclk>; | |
233 | }; | |
234 | ||
235 | /* PLL2 is usually 864 MHz and divided into a few fixed rates */ | |
236 | pll2: pll2@0 { | |
237 | #clock-cells = <0>; | |
238 | compatible = "st,nomadik-pll-clock"; | |
239 | pll-id = <2>; | |
240 | clocks = <&mxtal>; | |
241 | }; | |
242 | clk216: clk216@216M { | |
243 | #clock-cells = <0>; | |
244 | compatible = "fixed-factor-clock"; | |
245 | clock-div = <4>; | |
246 | clock-mult = <1>; | |
247 | clocks = <&pll2>; | |
248 | }; | |
249 | clk108: clk108@108M { | |
250 | #clock-cells = <0>; | |
251 | compatible = "fixed-factor-clock"; | |
252 | clock-div = <2>; | |
253 | clock-mult = <1>; | |
254 | clocks = <&clk216>; | |
255 | }; | |
256 | clk72: clk72@72M { | |
257 | #clock-cells = <0>; | |
258 | compatible = "fixed-factor-clock"; | |
259 | /* The data sheet does not say how this is derived */ | |
260 | clock-div = <12>; | |
261 | clock-mult = <1>; | |
262 | clocks = <&pll2>; | |
263 | }; | |
264 | clk48: clk48@48M { | |
265 | #clock-cells = <0>; | |
266 | compatible = "fixed-factor-clock"; | |
267 | /* The data sheet does not say how this is derived */ | |
268 | clock-div = <18>; | |
269 | clock-mult = <1>; | |
270 | clocks = <&pll2>; | |
271 | }; | |
272 | clk27: clk27@27M { | |
273 | #clock-cells = <0>; | |
274 | compatible = "fixed-factor-clock"; | |
275 | clock-div = <4>; | |
276 | clock-mult = <1>; | |
277 | clocks = <&clk108>; | |
278 | }; | |
279 | ||
280 | /* This apparently exists as well */ | |
281 | ulpiclk: ulpiclk@60M { | |
282 | #clock-cells = <0>; | |
283 | compatible = "fixed-clock"; | |
284 | clock-frequency = <60000000>; | |
285 | }; | |
286 | ||
287 | /* | |
288 | * IP AMBA bus clocks, driving the bus side of the | |
289 | * peripheral clocking, clock gates. | |
290 | */ | |
291 | ||
292 | hclkdma0: hclkdma0@48M { | |
293 | #clock-cells = <0>; | |
294 | compatible = "st,nomadik-src-clock"; | |
295 | clock-id = <0>; | |
296 | clocks = <&hclk>; | |
297 | }; | |
298 | hclksmc: hclksmc@48M { | |
299 | #clock-cells = <0>; | |
300 | compatible = "st,nomadik-src-clock"; | |
301 | clock-id = <1>; | |
302 | clocks = <&hclk>; | |
303 | }; | |
304 | hclksdram: hclksdram@48M { | |
305 | #clock-cells = <0>; | |
306 | compatible = "st,nomadik-src-clock"; | |
307 | clock-id = <2>; | |
308 | clocks = <&hclk>; | |
309 | }; | |
310 | hclkdma1: hclkdma1@48M { | |
311 | #clock-cells = <0>; | |
312 | compatible = "st,nomadik-src-clock"; | |
313 | clock-id = <3>; | |
314 | clocks = <&hclk>; | |
315 | }; | |
316 | hclkclcd: hclkclcd@48M { | |
317 | #clock-cells = <0>; | |
318 | compatible = "st,nomadik-src-clock"; | |
319 | clock-id = <4>; | |
320 | clocks = <&hclk>; | |
321 | }; | |
322 | pclkirda: pclkirda@48M { | |
323 | #clock-cells = <0>; | |
324 | compatible = "st,nomadik-src-clock"; | |
325 | clock-id = <5>; | |
326 | clocks = <&pclk>; | |
327 | }; | |
328 | pclkssp: pclkssp@48M { | |
329 | #clock-cells = <0>; | |
330 | compatible = "st,nomadik-src-clock"; | |
331 | clock-id = <6>; | |
332 | clocks = <&pclk>; | |
333 | }; | |
334 | pclkuart0: pclkuart0@48M { | |
335 | #clock-cells = <0>; | |
336 | compatible = "st,nomadik-src-clock"; | |
337 | clock-id = <7>; | |
338 | clocks = <&pclk>; | |
339 | }; | |
340 | pclksdi: pclksdi@48M { | |
341 | #clock-cells = <0>; | |
342 | compatible = "st,nomadik-src-clock"; | |
343 | clock-id = <8>; | |
344 | clocks = <&pclk>; | |
345 | }; | |
346 | pclki2c0: pclki2c0@48M { | |
347 | #clock-cells = <0>; | |
348 | compatible = "st,nomadik-src-clock"; | |
349 | clock-id = <9>; | |
350 | clocks = <&pclk>; | |
351 | }; | |
352 | pclki2c1: pclki2c1@48M { | |
353 | #clock-cells = <0>; | |
354 | compatible = "st,nomadik-src-clock"; | |
355 | clock-id = <10>; | |
356 | clocks = <&pclk>; | |
357 | }; | |
358 | pclkuart1: pclkuart1@48M { | |
359 | #clock-cells = <0>; | |
360 | compatible = "st,nomadik-src-clock"; | |
361 | clock-id = <11>; | |
362 | clocks = <&pclk>; | |
363 | }; | |
364 | pclkmsp0: pclkmsp0@48M { | |
365 | #clock-cells = <0>; | |
366 | compatible = "st,nomadik-src-clock"; | |
367 | clock-id = <12>; | |
368 | clocks = <&pclk>; | |
369 | }; | |
370 | hclkusb: hclkusb@48M { | |
371 | #clock-cells = <0>; | |
372 | compatible = "st,nomadik-src-clock"; | |
373 | clock-id = <13>; | |
374 | clocks = <&hclk>; | |
375 | }; | |
376 | hclkdif: hclkdif@48M { | |
377 | #clock-cells = <0>; | |
378 | compatible = "st,nomadik-src-clock"; | |
379 | clock-id = <14>; | |
380 | clocks = <&hclk>; | |
381 | }; | |
382 | hclksaa: hclksaa@48M { | |
383 | #clock-cells = <0>; | |
384 | compatible = "st,nomadik-src-clock"; | |
385 | clock-id = <15>; | |
386 | clocks = <&hclk>; | |
387 | }; | |
388 | hclksva: hclksva@48M { | |
389 | #clock-cells = <0>; | |
390 | compatible = "st,nomadik-src-clock"; | |
391 | clock-id = <16>; | |
392 | clocks = <&hclk>; | |
393 | }; | |
394 | pclkhsi: pclkhsi@48M { | |
395 | #clock-cells = <0>; | |
396 | compatible = "st,nomadik-src-clock"; | |
397 | clock-id = <17>; | |
398 | clocks = <&pclk>; | |
399 | }; | |
400 | pclkxti: pclkxti@48M { | |
401 | #clock-cells = <0>; | |
402 | compatible = "st,nomadik-src-clock"; | |
403 | clock-id = <18>; | |
404 | clocks = <&pclk>; | |
405 | }; | |
406 | pclkuart2: pclkuart2@48M { | |
407 | #clock-cells = <0>; | |
408 | compatible = "st,nomadik-src-clock"; | |
409 | clock-id = <19>; | |
410 | clocks = <&pclk>; | |
411 | }; | |
412 | pclkmsp1: pclkmsp1@48M { | |
413 | #clock-cells = <0>; | |
414 | compatible = "st,nomadik-src-clock"; | |
415 | clock-id = <20>; | |
416 | clocks = <&pclk>; | |
417 | }; | |
418 | pclkmsp2: pclkmsp2@48M { | |
419 | #clock-cells = <0>; | |
420 | compatible = "st,nomadik-src-clock"; | |
421 | clock-id = <21>; | |
422 | clocks = <&pclk>; | |
423 | }; | |
424 | pclkowm: pclkowm@48M { | |
425 | #clock-cells = <0>; | |
426 | compatible = "st,nomadik-src-clock"; | |
427 | clock-id = <22>; | |
428 | clocks = <&pclk>; | |
429 | }; | |
430 | hclkhpi: hclkhpi@48M { | |
431 | #clock-cells = <0>; | |
432 | compatible = "st,nomadik-src-clock"; | |
433 | clock-id = <23>; | |
434 | clocks = <&hclk>; | |
435 | }; | |
436 | pclkske: pclkske@48M { | |
437 | #clock-cells = <0>; | |
438 | compatible = "st,nomadik-src-clock"; | |
439 | clock-id = <24>; | |
440 | clocks = <&pclk>; | |
441 | }; | |
442 | pclkhsem: pclkhsem@48M { | |
443 | #clock-cells = <0>; | |
444 | compatible = "st,nomadik-src-clock"; | |
445 | clock-id = <25>; | |
446 | clocks = <&pclk>; | |
447 | }; | |
448 | hclk3d: hclk3d@48M { | |
449 | #clock-cells = <0>; | |
450 | compatible = "st,nomadik-src-clock"; | |
451 | clock-id = <26>; | |
452 | clocks = <&hclk>; | |
453 | }; | |
454 | hclkhash: hclkhash@48M { | |
455 | #clock-cells = <0>; | |
456 | compatible = "st,nomadik-src-clock"; | |
457 | clock-id = <27>; | |
458 | clocks = <&hclk>; | |
459 | }; | |
460 | hclkcryp: hclkcryp@48M { | |
461 | #clock-cells = <0>; | |
462 | compatible = "st,nomadik-src-clock"; | |
463 | clock-id = <28>; | |
464 | clocks = <&hclk>; | |
465 | }; | |
466 | pclkmshc: pclkmshc@48M { | |
467 | #clock-cells = <0>; | |
468 | compatible = "st,nomadik-src-clock"; | |
469 | clock-id = <29>; | |
470 | clocks = <&pclk>; | |
471 | }; | |
472 | hclkusbm: hclkusbm@48M { | |
473 | #clock-cells = <0>; | |
474 | compatible = "st,nomadik-src-clock"; | |
475 | clock-id = <30>; | |
476 | clocks = <&hclk>; | |
477 | }; | |
478 | hclkrng: hclkrng@48M { | |
479 | #clock-cells = <0>; | |
480 | compatible = "st,nomadik-src-clock"; | |
481 | clock-id = <31>; | |
482 | clocks = <&hclk>; | |
483 | }; | |
484 | ||
485 | /* IP kernel clocks */ | |
486 | clcdclk: clcdclk@0 { | |
487 | #clock-cells = <0>; | |
488 | compatible = "st,nomadik-src-clock"; | |
489 | clock-id = <36>; | |
490 | clocks = <&clk72 &clk48>; | |
491 | }; | |
492 | irdaclk: irdaclk@48M { | |
493 | #clock-cells = <0>; | |
494 | compatible = "st,nomadik-src-clock"; | |
495 | clock-id = <37>; | |
496 | clocks = <&clk48>; | |
497 | }; | |
498 | sspiclk: sspiclk@48M { | |
499 | #clock-cells = <0>; | |
500 | compatible = "st,nomadik-src-clock"; | |
501 | clock-id = <38>; | |
502 | clocks = <&clk48>; | |
503 | }; | |
504 | uart0clk: uart0clk@48M { | |
505 | #clock-cells = <0>; | |
506 | compatible = "st,nomadik-src-clock"; | |
507 | clock-id = <39>; | |
508 | clocks = <&clk48>; | |
509 | }; | |
510 | sdiclk: sdiclk@48M { | |
511 | /* Also called MCCLK in some documents */ | |
512 | #clock-cells = <0>; | |
513 | compatible = "st,nomadik-src-clock"; | |
514 | clock-id = <40>; | |
515 | clocks = <&clk48>; | |
516 | }; | |
517 | i2c0clk: i2c0clk@48M { | |
518 | #clock-cells = <0>; | |
519 | compatible = "st,nomadik-src-clock"; | |
520 | clock-id = <41>; | |
521 | clocks = <&clk48>; | |
522 | }; | |
523 | i2c1clk: i2c1clk@48M { | |
524 | #clock-cells = <0>; | |
525 | compatible = "st,nomadik-src-clock"; | |
526 | clock-id = <42>; | |
527 | clocks = <&clk48>; | |
528 | }; | |
529 | uart1clk: uart1clk@48M { | |
530 | #clock-cells = <0>; | |
531 | compatible = "st,nomadik-src-clock"; | |
532 | clock-id = <43>; | |
533 | clocks = <&clk48>; | |
534 | }; | |
535 | mspclk0: mspclk0@48M { | |
536 | #clock-cells = <0>; | |
537 | compatible = "st,nomadik-src-clock"; | |
538 | clock-id = <44>; | |
539 | clocks = <&clk48>; | |
540 | }; | |
541 | usbclk: usbclk@48M { | |
542 | #clock-cells = <0>; | |
543 | compatible = "st,nomadik-src-clock"; | |
544 | clock-id = <45>; | |
545 | clocks = <&clk48>; /* 48 MHz not ULPI */ | |
546 | }; | |
547 | difclk: difclk@72M { | |
548 | #clock-cells = <0>; | |
549 | compatible = "st,nomadik-src-clock"; | |
550 | clock-id = <46>; | |
551 | clocks = <&clk72>; | |
552 | }; | |
553 | ipi2cclk: ipi2cclk@48M { | |
554 | #clock-cells = <0>; | |
555 | compatible = "st,nomadik-src-clock"; | |
556 | clock-id = <47>; | |
557 | clocks = <&clk48>; /* Guess */ | |
558 | }; | |
559 | ipbmcclk: ipbmcclk@48M { | |
560 | #clock-cells = <0>; | |
561 | compatible = "st,nomadik-src-clock"; | |
562 | clock-id = <48>; | |
563 | clocks = <&clk48>; /* Guess */ | |
564 | }; | |
565 | hsiclkrx: hsiclkrx@216M { | |
566 | #clock-cells = <0>; | |
567 | compatible = "st,nomadik-src-clock"; | |
568 | clock-id = <49>; | |
569 | clocks = <&clk216>; | |
570 | }; | |
571 | hsiclktx: hsiclktx@108M { | |
572 | #clock-cells = <0>; | |
573 | compatible = "st,nomadik-src-clock"; | |
574 | clock-id = <50>; | |
575 | clocks = <&clk108>; | |
576 | }; | |
577 | uart2clk: uart2clk@48M { | |
578 | #clock-cells = <0>; | |
579 | compatible = "st,nomadik-src-clock"; | |
580 | clock-id = <51>; | |
581 | clocks = <&clk48>; | |
582 | }; | |
583 | mspclk1: mspclk1@48M { | |
584 | #clock-cells = <0>; | |
585 | compatible = "st,nomadik-src-clock"; | |
586 | clock-id = <52>; | |
587 | clocks = <&clk48>; | |
588 | }; | |
589 | mspclk2: mspclk2@48M { | |
590 | #clock-cells = <0>; | |
591 | compatible = "st,nomadik-src-clock"; | |
592 | clock-id = <53>; | |
593 | clocks = <&clk48>; | |
594 | }; | |
595 | owmclk: owmclk@48M { | |
596 | #clock-cells = <0>; | |
597 | compatible = "st,nomadik-src-clock"; | |
598 | clock-id = <54>; | |
599 | clocks = <&clk48>; /* Guess */ | |
600 | }; | |
601 | skeclk: skeclk@48M { | |
602 | #clock-cells = <0>; | |
603 | compatible = "st,nomadik-src-clock"; | |
604 | clock-id = <56>; | |
605 | clocks = <&clk48>; /* Guess */ | |
606 | }; | |
607 | x3dclk: x3dclk@48M { | |
608 | #clock-cells = <0>; | |
609 | compatible = "st,nomadik-src-clock"; | |
610 | clock-id = <58>; | |
611 | clocks = <&clk48>; /* Guess */ | |
612 | }; | |
613 | pclkmsp3: pclkmsp3@48M { | |
614 | #clock-cells = <0>; | |
615 | compatible = "st,nomadik-src-clock"; | |
616 | clock-id = <59>; | |
617 | clocks = <&pclk>; | |
618 | }; | |
619 | mspclk3: mspclk3@48M { | |
620 | #clock-cells = <0>; | |
621 | compatible = "st,nomadik-src-clock"; | |
622 | clock-id = <60>; | |
623 | clocks = <&clk48>; | |
624 | }; | |
625 | mshcclk: mshcclk@48M { | |
626 | #clock-cells = <0>; | |
627 | compatible = "st,nomadik-src-clock"; | |
628 | clock-id = <61>; | |
629 | clocks = <&clk48>; /* Guess */ | |
630 | }; | |
631 | usbmclk: usbmclk@48M { | |
632 | #clock-cells = <0>; | |
633 | compatible = "st,nomadik-src-clock"; | |
634 | clock-id = <62>; | |
635 | /* Stated as "48 MHz not ULPI clock" */ | |
636 | clocks = <&clk48>; | |
637 | }; | |
638 | rngcclk: rngcclk@48M { | |
639 | #clock-cells = <0>; | |
640 | compatible = "st,nomadik-src-clock"; | |
641 | clock-id = <63>; | |
642 | clocks = <&clk48>; /* Guess */ | |
6e2b07a1 LW |
643 | }; |
644 | }; | |
645 | ||
ba785205 LW |
646 | /* A NAND flash of 128 MiB */ |
647 | fsmc: flash@40000000 { | |
648 | compatible = "stericsson,fsmc-nand"; | |
649 | #address-cells = <1>; | |
650 | #size-cells = <1>; | |
651 | reg = <0x10100000 0x1000>, /* FSMC Register*/ | |
652 | <0x40000000 0x2000>, /* NAND Base DATA */ | |
653 | <0x41000000 0x2000>, /* NAND Base ADDR */ | |
654 | <0x40800000 0x2000>; /* NAND Base CMD */ | |
655 | reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; | |
c641d4df | 656 | clocks = <&hclksmc>; |
ba785205 | 657 | status = "okay"; |
2c5a7424 | 658 | timings = /bits/ 8 <0 0 0 0x10 0x0a 0>; |
ba785205 LW |
659 | |
660 | partition@0 { | |
661 | label = "X-Loader(NAND)"; | |
662 | reg = <0x0 0x40000>; | |
663 | }; | |
664 | partition@40000 { | |
665 | label = "MemInit(NAND)"; | |
666 | reg = <0x40000 0x40000>; | |
667 | }; | |
668 | partition@80000 { | |
669 | label = "BootLoader(NAND)"; | |
670 | reg = <0x80000 0x200000>; | |
671 | }; | |
672 | partition@280000 { | |
673 | label = "Kernel zImage(NAND)"; | |
674 | reg = <0x280000 0x300000>; | |
675 | }; | |
676 | partition@580000 { | |
677 | label = "Root Filesystem(NAND)"; | |
678 | reg = <0x580000 0x1600000>; | |
679 | }; | |
680 | partition@1b80000 { | |
681 | label = "User Filesystem(NAND)"; | |
682 | reg = <0x1b80000 0x6480000>; | |
683 | }; | |
684 | }; | |
685 | ||
2ad6e398 LW |
686 | external-bus@34000000 { |
687 | compatible = "simple-bus"; | |
688 | reg = <0x34000000 0x1000000>; | |
689 | #address-cells = <1>; | |
690 | #size-cells = <1>; | |
691 | ranges = <0 0x34000000 0x1000000>; | |
692 | ethernet@300 { | |
693 | compatible = "smsc,lan91c111"; | |
694 | reg = <0x300 0x0fd00>; | |
695 | }; | |
696 | }; | |
697 | ||
09e02f4d LW |
698 | /* I2C0 connected to the STw4811 power management chip */ |
699 | i2c0 { | |
66e0c12f LW |
700 | compatible = "st,nomadik-i2c", "arm,primecell"; |
701 | reg = <0x101f8000 0x1000>; | |
702 | interrupt-parent = <&vica>; | |
703 | interrupts = <20>; | |
704 | clock-frequency = <100000>; | |
09e02f4d LW |
705 | #address-cells = <1>; |
706 | #size-cells = <0>; | |
66e0c12f LW |
707 | clocks = <&i2c0clk>, <&pclki2c0>; |
708 | clock-names = "mclk", "apb_pclk"; | |
49932f5e | 709 | pinctrl-names = "default"; |
66e0c12f | 710 | pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; |
09e02f4d LW |
711 | |
712 | stw4811@2d { | |
d9f37d9e LW |
713 | compatible = "st,stw4811"; |
714 | reg = <0x2d>; | |
715 | vmmc_regulator: vmmc { | |
716 | compatible = "st,stw481x-vmmc"; | |
717 | regulator-name = "VMMC"; | |
718 | regulator-min-microvolt = <1800000>; | |
719 | regulator-max-microvolt = <3300000>; | |
720 | }; | |
09e02f4d LW |
721 | }; |
722 | }; | |
723 | ||
724 | /* I2C1 connected to various sensors */ | |
725 | i2c1 { | |
66e0c12f LW |
726 | compatible = "st,nomadik-i2c", "arm,primecell"; |
727 | reg = <0x101f7000 0x1000>; | |
728 | interrupt-parent = <&vica>; | |
729 | interrupts = <21>; | |
730 | clock-frequency = <100000>; | |
09e02f4d LW |
731 | #address-cells = <1>; |
732 | #size-cells = <0>; | |
66e0c12f LW |
733 | clocks = <&i2c1clk>, <&pclki2c1>; |
734 | clock-names = "mclk", "apb_pclk"; | |
49932f5e | 735 | pinctrl-names = "default"; |
66e0c12f | 736 | pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; |
09e02f4d LW |
737 | |
738 | camera@2d { | |
739 | compatible = "st,camera"; | |
740 | reg = <0x10>; | |
741 | }; | |
742 | stw5095@1a { | |
743 | compatible = "st,stw5095"; | |
744 | reg = <0x1a>; | |
745 | }; | |
746 | lis3lv02dl@1d { | |
747 | compatible = "st,lis3lv02dl"; | |
748 | reg = <0x1d>; | |
749 | }; | |
750 | }; | |
751 | ||
752 | /* I2C2 connected to the USB portions of the STw4811 only */ | |
753 | i2c2 { | |
754 | compatible = "i2c-gpio"; | |
755 | gpios = <&gpio2 10 0>, /* sda */ | |
756 | <&gpio2 9 0>; /* scl */ | |
757 | #address-cells = <1>; | |
758 | #size-cells = <0>; | |
49932f5e LW |
759 | pinctrl-names = "default"; |
760 | pinctrl-0 = <&i2c2_default_mode>; | |
761 | ||
09e02f4d LW |
762 | stw4811@2d { |
763 | compatible = "st,stw4811-usb"; | |
764 | reg = <0x2d>; | |
765 | }; | |
766 | }; | |
767 | ||
f8635abd LW |
768 | amba { |
769 | compatible = "arm,amba-bus"; | |
770 | #address-cells = <1>; | |
771 | #size-cells = <1>; | |
772 | ranges; | |
773 | ||
30e34001 | 774 | vica: intc@10140000 { |
f8635abd LW |
775 | compatible = "arm,versatile-vic"; |
776 | interrupt-controller; | |
777 | #interrupt-cells = <1>; | |
778 | reg = <0x10140000 0x20>; | |
779 | }; | |
780 | ||
30e34001 | 781 | vicb: intc@10140020 { |
f8635abd LW |
782 | compatible = "arm,versatile-vic"; |
783 | interrupt-controller; | |
784 | #interrupt-cells = <1>; | |
785 | reg = <0x10140020 0x20>; | |
786 | }; | |
787 | ||
788 | uart0: uart@101fd000 { | |
789 | compatible = "arm,pl011", "arm,primecell"; | |
790 | reg = <0x101fd000 0x1000>; | |
791 | interrupt-parent = <&vica>; | |
792 | interrupts = <12>; | |
c641d4df | 793 | clocks = <&uart0clk>, <&pclkuart0>; |
6e2b07a1 | 794 | clock-names = "uartclk", "apb_pclk"; |
49932f5e LW |
795 | pinctrl-names = "default"; |
796 | pinctrl-0 = <&uart0_default_mux>; | |
f8635abd LW |
797 | }; |
798 | ||
799 | uart1: uart@101fb000 { | |
800 | compatible = "arm,pl011", "arm,primecell"; | |
801 | reg = <0x101fb000 0x1000>; | |
802 | interrupt-parent = <&vica>; | |
803 | interrupts = <17>; | |
c641d4df | 804 | clocks = <&uart1clk>, <&pclkuart1>; |
6e2b07a1 | 805 | clock-names = "uartclk", "apb_pclk"; |
49932f5e LW |
806 | pinctrl-names = "default"; |
807 | pinctrl-0 = <&uart1_default_mux>; | |
f8635abd LW |
808 | }; |
809 | ||
810 | uart2: uart@101f2000 { | |
811 | compatible = "arm,pl011", "arm,primecell"; | |
812 | reg = <0x101f2000 0x1000>; | |
813 | interrupt-parent = <&vica>; | |
814 | interrupts = <28>; | |
c641d4df | 815 | clocks = <&uart2clk>, <&pclkuart2>; |
6e2b07a1 | 816 | clock-names = "uartclk", "apb_pclk"; |
f8635abd LW |
817 | status = "disabled"; |
818 | }; | |
27bda036 LW |
819 | |
820 | rng: rng@101b0000 { | |
821 | compatible = "arm,primecell"; | |
822 | reg = <0x101b0000 0x1000>; | |
c641d4df | 823 | clocks = <&rngcclk>, <&hclkrng>; |
6e2b07a1 | 824 | clock-names = "rng", "apb_pclk"; |
27bda036 LW |
825 | }; |
826 | ||
827 | rtc: rtc@101e8000 { | |
828 | compatible = "arm,pl031", "arm,primecell"; | |
829 | reg = <0x101e8000 0x1000>; | |
6e2b07a1 LW |
830 | clocks = <&pclk>; |
831 | clock-names = "apb_pclk"; | |
27bda036 LW |
832 | interrupt-parent = <&vica>; |
833 | interrupts = <10>; | |
834 | }; | |
4fd243c6 LW |
835 | |
836 | mmcsd: sdi@101f6000 { | |
837 | compatible = "arm,pl18x", "arm,primecell"; | |
838 | reg = <0x101f6000 0x1000>; | |
c641d4df | 839 | clocks = <&sdiclk>, <&pclksdi>; |
6e2b07a1 | 840 | clock-names = "mclk", "apb_pclk"; |
4fd243c6 LW |
841 | interrupt-parent = <&vica>; |
842 | interrupts = <22>; | |
843 | max-frequency = <48000000>; | |
844 | bus-width = <4>; | |
c1bc0e8c UH |
845 | cap-mmc-highspeed; |
846 | cap-sd-highspeed; | |
3181788c | 847 | cd-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; |
49932f5e LW |
848 | pinctrl-names = "default"; |
849 | pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; | |
d9f37d9e | 850 | vmmc-supply = <&vmmc_regulator>; |
4fd243c6 | 851 | }; |
f8635abd LW |
852 | }; |
853 | }; |