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f563a571 MC |
1 | /* |
2 | * Copyright (C) 2014 STMicroelectronics Limited. | |
3 | * Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
f563a571 | 9 | #include "stih407-pinctrl.dtsi" |
358764f3 | 10 | #include <dt-bindings/mfd/st-lpc.h> |
b3d37f92 | 11 | #include <dt-bindings/phy/phy.h> |
b864a0b9 | 12 | #include <dt-bindings/reset-controller/stih407-resets.h> |
107dea0c | 13 | #include <dt-bindings/interrupt-controller/irq-st.h> |
f563a571 MC |
14 | / { |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | ||
18 | cpus { | |
19 | #address-cells = <1>; | |
20 | #size-cells = <0>; | |
21 | cpu@0 { | |
22 | device_type = "cpu"; | |
23 | compatible = "arm,cortex-a9"; | |
24 | reg = <0>; | |
25 | }; | |
26 | cpu@1 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a9"; | |
29 | reg = <1>; | |
30 | }; | |
31 | }; | |
32 | ||
33 | intc: interrupt-controller@08761000 { | |
34 | compatible = "arm,cortex-a9-gic"; | |
35 | #interrupt-cells = <3>; | |
36 | interrupt-controller; | |
37 | reg = <0x08761000 0x1000>, <0x08760100 0x100>; | |
38 | }; | |
39 | ||
40 | scu@08760000 { | |
41 | compatible = "arm,cortex-a9-scu"; | |
42 | reg = <0x08760000 0x1000>; | |
43 | }; | |
44 | ||
45 | timer@08760200 { | |
46 | interrupt-parent = <&intc>; | |
47 | compatible = "arm,cortex-a9-global-timer"; | |
48 | reg = <0x08760200 0x100>; | |
49 | interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
50 | clocks = <&arm_periph_clk>; | |
51 | }; | |
52 | ||
53 | l2: cache-controller { | |
54 | compatible = "arm,pl310-cache"; | |
55 | reg = <0x08762000 0x1000>; | |
56 | arm,data-latency = <3 3 3>; | |
57 | arm,tag-latency = <2 2 2>; | |
58 | cache-unified; | |
59 | cache-level = <2>; | |
60 | }; | |
61 | ||
00133b91 LJ |
62 | arm-pmu { |
63 | interrupt-parent = <&intc>; | |
64 | compatible = "arm,cortex-a9-pmu"; | |
65 | interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; | |
66 | }; | |
67 | ||
f563a571 MC |
68 | soc { |
69 | #address-cells = <1>; | |
70 | #size-cells = <1>; | |
71 | interrupt-parent = <&intc>; | |
72 | ranges; | |
73 | compatible = "simple-bus"; | |
74 | ||
48f3fe6b LJ |
75 | restart { |
76 | compatible = "st,stih407-restart"; | |
77 | st,syscfg = <&syscfg_sbc_reg>; | |
78 | status = "okay"; | |
79 | }; | |
80 | ||
b864a0b9 PG |
81 | powerdown: powerdown-controller { |
82 | compatible = "st,stih407-powerdown"; | |
83 | #reset-cells = <1>; | |
84 | }; | |
85 | ||
86 | softreset: softreset-controller { | |
87 | compatible = "st,stih407-softreset"; | |
88 | #reset-cells = <1>; | |
89 | }; | |
90 | ||
91 | picophyreset: picophyreset-controller { | |
92 | compatible = "st,stih407-picophyreset"; | |
93 | #reset-cells = <1>; | |
94 | }; | |
95 | ||
f563a571 MC |
96 | syscfg_sbc: sbc-syscfg@9620000 { |
97 | compatible = "st,stih407-sbc-syscfg", "syscon"; | |
98 | reg = <0x9620000 0x1000>; | |
99 | }; | |
100 | ||
101 | syscfg_front: front-syscfg@9280000 { | |
102 | compatible = "st,stih407-front-syscfg", "syscon"; | |
103 | reg = <0x9280000 0x1000>; | |
104 | }; | |
105 | ||
106 | syscfg_rear: rear-syscfg@9290000 { | |
107 | compatible = "st,stih407-rear-syscfg", "syscon"; | |
108 | reg = <0x9290000 0x1000>; | |
109 | }; | |
110 | ||
111 | syscfg_flash: flash-syscfg@92a0000 { | |
112 | compatible = "st,stih407-flash-syscfg", "syscon"; | |
113 | reg = <0x92a0000 0x1000>; | |
114 | }; | |
115 | ||
116 | syscfg_sbc_reg: fvdp-lite-syscfg@9600000 { | |
117 | compatible = "st,stih407-sbc-reg-syscfg", "syscon"; | |
118 | reg = <0x9600000 0x1000>; | |
119 | }; | |
120 | ||
121 | syscfg_core: core-syscfg@92b0000 { | |
122 | compatible = "st,stih407-core-syscfg", "syscon"; | |
123 | reg = <0x92b0000 0x1000>; | |
124 | }; | |
125 | ||
126 | syscfg_lpm: lpm-syscfg@94b5100 { | |
127 | compatible = "st,stih407-lpm-syscfg", "syscon"; | |
128 | reg = <0x94b5100 0x1000>; | |
129 | }; | |
130 | ||
107dea0c LJ |
131 | irq-syscfg { |
132 | compatible = "st,stih407-irq-syscfg"; | |
133 | st,syscfg = <&syscfg_core>; | |
134 | st,irq-device = <ST_IRQ_SYSCFG_PMU_0>, | |
135 | <ST_IRQ_SYSCFG_PMU_1>; | |
136 | st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>, | |
137 | <ST_IRQ_SYSCFG_DISABLED>; | |
138 | }; | |
139 | ||
f563a571 MC |
140 | serial@9830000 { |
141 | compatible = "st,asc"; | |
142 | reg = <0x9830000 0x2c>; | |
143 | interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>; | |
144 | pinctrl-names = "default"; | |
145 | pinctrl-0 = <&pinctrl_serial0>; | |
1befe7e4 | 146 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
147 | |
148 | status = "disabled"; | |
149 | }; | |
150 | ||
151 | serial@9831000 { | |
152 | compatible = "st,asc"; | |
153 | reg = <0x9831000 0x2c>; | |
154 | interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>; | |
155 | pinctrl-names = "default"; | |
156 | pinctrl-0 = <&pinctrl_serial1>; | |
1befe7e4 | 157 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
158 | |
159 | status = "disabled"; | |
160 | }; | |
161 | ||
162 | serial@9832000 { | |
163 | compatible = "st,asc"; | |
164 | reg = <0x9832000 0x2c>; | |
165 | interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; | |
166 | pinctrl-names = "default"; | |
167 | pinctrl-0 = <&pinctrl_serial2>; | |
1befe7e4 | 168 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
169 | |
170 | status = "disabled"; | |
171 | }; | |
172 | ||
173 | /* SBC_ASC0 - UART10 */ | |
174 | sbc_serial0: serial@9530000 { | |
175 | compatible = "st,asc"; | |
176 | reg = <0x9530000 0x2c>; | |
177 | interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>; | |
178 | pinctrl-names = "default"; | |
179 | pinctrl-0 = <&pinctrl_sbc_serial0>; | |
180 | clocks = <&clk_sysin>; | |
181 | ||
182 | status = "disabled"; | |
183 | }; | |
184 | ||
185 | serial@9531000 { | |
186 | compatible = "st,asc"; | |
187 | reg = <0x9531000 0x2c>; | |
188 | interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>; | |
189 | pinctrl-names = "default"; | |
190 | pinctrl-0 = <&pinctrl_sbc_serial1>; | |
191 | clocks = <&clk_sysin>; | |
192 | ||
193 | status = "disabled"; | |
194 | }; | |
195 | ||
196 | i2c@9840000 { | |
197 | compatible = "st,comms-ssc4-i2c"; | |
198 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
199 | reg = <0x9840000 0x110>; | |
1befe7e4 | 200 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
201 | clock-names = "ssc"; |
202 | clock-frequency = <400000>; | |
203 | pinctrl-names = "default"; | |
204 | pinctrl-0 = <&pinctrl_i2c0_default>; | |
205 | ||
206 | status = "disabled"; | |
207 | }; | |
208 | ||
209 | i2c@9841000 { | |
210 | compatible = "st,comms-ssc4-i2c"; | |
211 | reg = <0x9841000 0x110>; | |
212 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 213 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
214 | clock-names = "ssc"; |
215 | clock-frequency = <400000>; | |
216 | pinctrl-names = "default"; | |
217 | pinctrl-0 = <&pinctrl_i2c1_default>; | |
218 | ||
219 | status = "disabled"; | |
220 | }; | |
221 | ||
222 | i2c@9842000 { | |
223 | compatible = "st,comms-ssc4-i2c"; | |
224 | reg = <0x9842000 0x110>; | |
225 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 226 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
227 | clock-names = "ssc"; |
228 | clock-frequency = <400000>; | |
229 | pinctrl-names = "default"; | |
230 | pinctrl-0 = <&pinctrl_i2c2_default>; | |
231 | ||
232 | status = "disabled"; | |
233 | }; | |
234 | ||
235 | i2c@9843000 { | |
236 | compatible = "st,comms-ssc4-i2c"; | |
237 | reg = <0x9843000 0x110>; | |
238 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 239 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
240 | clock-names = "ssc"; |
241 | clock-frequency = <400000>; | |
242 | pinctrl-names = "default"; | |
243 | pinctrl-0 = <&pinctrl_i2c3_default>; | |
244 | ||
245 | status = "disabled"; | |
246 | }; | |
247 | ||
248 | i2c@9844000 { | |
249 | compatible = "st,comms-ssc4-i2c"; | |
250 | reg = <0x9844000 0x110>; | |
251 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 252 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
253 | clock-names = "ssc"; |
254 | clock-frequency = <400000>; | |
255 | pinctrl-names = "default"; | |
256 | pinctrl-0 = <&pinctrl_i2c4_default>; | |
257 | ||
258 | status = "disabled"; | |
259 | }; | |
260 | ||
261 | i2c@9845000 { | |
262 | compatible = "st,comms-ssc4-i2c"; | |
263 | reg = <0x9845000 0x110>; | |
264 | interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
1befe7e4 | 265 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; |
f563a571 MC |
266 | clock-names = "ssc"; |
267 | clock-frequency = <400000>; | |
268 | pinctrl-names = "default"; | |
269 | pinctrl-0 = <&pinctrl_i2c5_default>; | |
270 | ||
271 | status = "disabled"; | |
272 | }; | |
273 | ||
274 | ||
275 | /* SSCs on SBC */ | |
276 | i2c@9540000 { | |
277 | compatible = "st,comms-ssc4-i2c"; | |
278 | reg = <0x9540000 0x110>; | |
279 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
280 | clocks = <&clk_sysin>; | |
281 | clock-names = "ssc"; | |
282 | clock-frequency = <400000>; | |
283 | pinctrl-names = "default"; | |
284 | pinctrl-0 = <&pinctrl_i2c10_default>; | |
285 | ||
286 | status = "disabled"; | |
287 | }; | |
288 | ||
289 | i2c@9541000 { | |
290 | compatible = "st,comms-ssc4-i2c"; | |
291 | reg = <0x9541000 0x110>; | |
292 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | |
293 | clocks = <&clk_sysin>; | |
294 | clock-names = "ssc"; | |
295 | clock-frequency = <400000>; | |
296 | pinctrl-names = "default"; | |
297 | pinctrl-0 = <&pinctrl_i2c11_default>; | |
298 | ||
299 | status = "disabled"; | |
300 | }; | |
8facce13 PG |
301 | |
302 | usb2_picophy0: phy1 { | |
303 | compatible = "st,stih407-usb2-phy"; | |
304 | #phy-cells = <0>; | |
305 | st,syscfg = <&syscfg_core 0x100 0xf4>; | |
306 | resets = <&softreset STIH407_PICOPHY_SOFTRESET>, | |
743ac9d2 | 307 | <&picophyreset STIH407_PICOPHY2_RESET>; |
8facce13 PG |
308 | reset-names = "global", "port"; |
309 | }; | |
b26373c0 GF |
310 | |
311 | miphy28lp_phy: miphy28lp@9b22000 { | |
312 | compatible = "st,miphy28lp-phy"; | |
313 | st,syscfg = <&syscfg_core>; | |
314 | #address-cells = <1>; | |
315 | #size-cells = <1>; | |
316 | ranges; | |
317 | ||
318 | phy_port0: port@9b22000 { | |
319 | reg = <0x9b22000 0xff>, | |
320 | <0x9b09000 0xff>, | |
321 | <0x9b04000 0xff>; | |
322 | reg-names = "sata-up", | |
323 | "pcie-up", | |
324 | "pipew"; | |
325 | ||
326 | st,syscfg = <0x114 0x818 0xe0 0xec>; | |
327 | #phy-cells = <1>; | |
328 | ||
329 | reset-names = "miphy-sw-rst"; | |
330 | resets = <&softreset STIH407_MIPHY0_SOFTRESET>; | |
331 | }; | |
332 | ||
333 | phy_port1: port@9b2a000 { | |
334 | reg = <0x9b2a000 0xff>, | |
335 | <0x9b19000 0xff>, | |
336 | <0x9b14000 0xff>; | |
337 | reg-names = "sata-up", | |
338 | "pcie-up", | |
339 | "pipew"; | |
340 | ||
341 | st,syscfg = <0x118 0x81c 0xe4 0xf0>; | |
342 | ||
343 | #phy-cells = <1>; | |
344 | ||
345 | reset-names = "miphy-sw-rst"; | |
346 | resets = <&softreset STIH407_MIPHY1_SOFTRESET>; | |
347 | }; | |
348 | ||
349 | phy_port2: port@8f95000 { | |
350 | reg = <0x8f95000 0xff>, | |
351 | <0x8f90000 0xff>; | |
352 | reg-names = "pipew", | |
353 | "usb3-up"; | |
354 | ||
355 | st,syscfg = <0x11c 0x820>; | |
356 | ||
357 | #phy-cells = <1>; | |
358 | ||
359 | reset-names = "miphy-sw-rst"; | |
360 | resets = <&softreset STIH407_MIPHY2_SOFTRESET>; | |
361 | }; | |
362 | }; | |
2c53c272 LJ |
363 | |
364 | spi@9840000 { | |
365 | compatible = "st,comms-ssc4-spi"; | |
366 | reg = <0x9840000 0x110>; | |
367 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; | |
368 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
369 | clock-names = "ssc"; | |
370 | pinctrl-0 = <&pinctrl_spi0_default>; | |
371 | pinctrl-names = "default"; | |
372 | #address-cells = <1>; | |
373 | #size-cells = <0>; | |
374 | ||
375 | status = "disabled"; | |
376 | }; | |
377 | ||
378 | spi@9841000 { | |
379 | compatible = "st,comms-ssc4-spi"; | |
380 | reg = <0x9841000 0x110>; | |
381 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
382 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
383 | clock-names = "ssc"; | |
384 | ||
385 | status = "disabled"; | |
386 | }; | |
387 | ||
388 | spi@9842000 { | |
389 | compatible = "st,comms-ssc4-spi"; | |
390 | reg = <0x9842000 0x110>; | |
391 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
392 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
393 | clock-names = "ssc"; | |
394 | ||
395 | status = "disabled"; | |
396 | }; | |
397 | ||
398 | spi@9843000 { | |
399 | compatible = "st,comms-ssc4-spi"; | |
400 | reg = <0x9843000 0x110>; | |
401 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
402 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
403 | clock-names = "ssc"; | |
404 | ||
405 | status = "disabled"; | |
406 | }; | |
407 | ||
408 | spi@9844000 { | |
409 | compatible = "st,comms-ssc4-spi"; | |
410 | reg = <0x9844000 0x110>; | |
411 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
412 | clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>; | |
413 | clock-names = "ssc"; | |
414 | ||
415 | status = "disabled"; | |
416 | }; | |
b0bb2bae LJ |
417 | |
418 | /* SBC SSC */ | |
419 | spi@9540000 { | |
420 | compatible = "st,comms-ssc4-spi"; | |
421 | reg = <0x9540000 0x110>; | |
422 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; | |
423 | clocks = <&clk_sysin>; | |
424 | clock-names = "ssc"; | |
425 | ||
426 | status = "disabled"; | |
427 | }; | |
428 | ||
429 | spi@9541000 { | |
430 | compatible = "st,comms-ssc4-spi"; | |
431 | reg = <0x9541000 0x110>; | |
432 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; | |
433 | clocks = <&clk_sysin>; | |
434 | clock-names = "ssc"; | |
435 | ||
436 | status = "disabled"; | |
437 | }; | |
438 | ||
439 | spi@9542000 { | |
440 | compatible = "st,comms-ssc4-spi"; | |
441 | reg = <0x9542000 0x110>; | |
442 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; | |
443 | clocks = <&clk_sysin>; | |
444 | clock-names = "ssc"; | |
445 | ||
446 | status = "disabled"; | |
447 | }; | |
9286ac48 PG |
448 | |
449 | mmc0: sdhci@09060000 { | |
450 | compatible = "st,sdhci-stih407", "st,sdhci"; | |
451 | status = "disabled"; | |
452 | reg = <0x09060000 0x7ff>, <0x9061008 0x20>; | |
453 | reg-names = "mmc", "top-mmc-delay"; | |
454 | interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>; | |
455 | interrupt-names = "mmcirq"; | |
456 | pinctrl-names = "default"; | |
457 | pinctrl-0 = <&pinctrl_mmc0>; | |
458 | clock-names = "mmc"; | |
459 | clocks = <&clk_s_c0_flexgen CLK_MMC_0>; | |
460 | bus-width = <8>; | |
461 | non-removable; | |
462 | }; | |
463 | ||
464 | mmc1: sdhci@09080000 { | |
465 | compatible = "st,sdhci-stih407", "st,sdhci"; | |
466 | status = "disabled"; | |
467 | reg = <0x09080000 0x7ff>; | |
468 | reg-names = "mmc"; | |
469 | interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>; | |
470 | interrupt-names = "mmcirq"; | |
471 | pinctrl-names = "default"; | |
472 | pinctrl-0 = <&pinctrl_sd1>; | |
473 | clock-names = "mmc"; | |
474 | clocks = <&clk_s_c0_flexgen CLK_MMC_1>; | |
475 | resets = <&softreset STIH407_MMC1_SOFTRESET>; | |
476 | bus-width = <4>; | |
477 | }; | |
358764f3 LJ |
478 | |
479 | /* Watchdog and Real-Time Clock */ | |
480 | lpc@8787000 { | |
481 | compatible = "st,stih407-lpc"; | |
482 | reg = <0x8787000 0x1000>; | |
483 | interrupts = <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>; | |
484 | clocks = <&clk_s_d3_flexgen CLK_LPC_0>; | |
485 | timeout-sec = <120>; | |
486 | st,syscfg = <&syscfg_core>; | |
487 | st,lpc-mode = <ST_LPC_MODE_WDT>; | |
488 | }; | |
489 | ||
490 | lpc@8788000 { | |
491 | compatible = "st,stih407-lpc"; | |
492 | reg = <0x8788000 0x1000>; | |
493 | interrupts = <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>; | |
494 | clocks = <&clk_s_d3_flexgen CLK_LPC_1>; | |
495 | st,lpc-mode = <ST_LPC_MODE_RTC>; | |
496 | }; | |
b3d37f92 PG |
497 | |
498 | sata0: sata@9b20000 { | |
499 | compatible = "st,ahci"; | |
500 | reg = <0x9b20000 0x1000>; | |
501 | ||
502 | interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; | |
503 | interrupt-names = "hostc"; | |
504 | ||
505 | phys = <&phy_port0 PHY_TYPE_SATA>; | |
506 | phy-names = "ahci_phy"; | |
507 | ||
508 | resets = <&powerdown STIH407_SATA0_POWERDOWN>, | |
509 | <&softreset STIH407_SATA0_SOFTRESET>, | |
510 | <&softreset STIH407_SATA0_PWR_SOFTRESET>; | |
511 | reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; | |
512 | ||
513 | clock-names = "ahci_clk"; | |
514 | clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; | |
515 | ||
516 | status = "disabled"; | |
517 | }; | |
518 | ||
519 | sata1: sata@9b28000 { | |
520 | compatible = "st,ahci"; | |
521 | reg = <0x9b28000 0x1000>; | |
522 | ||
523 | interrupts = <GIC_SPI 170 IRQ_TYPE_NONE>; | |
524 | interrupt-names = "hostc"; | |
525 | ||
526 | phys = <&phy_port1 PHY_TYPE_SATA>; | |
527 | phy-names = "ahci_phy"; | |
528 | ||
529 | resets = <&powerdown STIH407_SATA1_POWERDOWN>, | |
530 | <&softreset STIH407_SATA1_SOFTRESET>, | |
531 | <&softreset STIH407_SATA1_PWR_SOFTRESET>; | |
532 | reset-names = "pwr-dwn", | |
533 | "sw-rst", | |
534 | "pwr-rst"; | |
535 | ||
536 | clock-names = "ahci_clk"; | |
537 | clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; | |
538 | ||
539 | status = "disabled"; | |
540 | }; | |
fd555998 PG |
541 | |
542 | st_dwc3: dwc3@8f94000 { | |
543 | compatible = "st,stih407-dwc3"; | |
544 | reg = <0x08f94000 0x1000>, <0x110 0x4>; | |
545 | reg-names = "reg-glue", "syscfg-reg"; | |
546 | st,syscfg = <&syscfg_core>; | |
547 | resets = <&powerdown STIH407_USB3_POWERDOWN>, | |
548 | <&softreset STIH407_MIPHY2_SOFTRESET>; | |
549 | reset-names = "powerdown", "softreset"; | |
550 | #address-cells = <1>; | |
551 | #size-cells = <1>; | |
552 | pinctrl-names = "default"; | |
553 | pinctrl-0 = <&pinctrl_usb3>; | |
554 | ranges; | |
555 | ||
556 | status = "disabled"; | |
557 | ||
558 | dwc3: dwc3@9900000 { | |
559 | compatible = "snps,dwc3"; | |
560 | reg = <0x09900000 0x100000>; | |
561 | interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>; | |
562 | dr_mode = "host"; | |
563 | phy-names = "usb2-phy", "usb3-phy"; | |
564 | phys = <&usb2_picophy0>, | |
565 | <&phy_port2 PHY_TYPE_USB3>; | |
566 | }; | |
567 | }; | |
f563a571 MC |
568 | }; |
569 | }; |