Commit | Line | Data |
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65ebcc11 SK |
1 | /* |
2 | * Copyright (C) 2013 STMicroelectronics (R&D) Limited. | |
3 | * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com> | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * publishhed by the Free Software Foundation. | |
8 | */ | |
9 | #include "st-pincfg.h" | |
7ec5183a | 10 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
65ebcc11 SK |
11 | / { |
12 | ||
13 | aliases { | |
dc62bfdf LJ |
14 | gpio0 = &pio0; |
15 | gpio1 = &pio1; | |
16 | gpio2 = &pio2; | |
17 | gpio3 = &pio3; | |
18 | gpio4 = &pio4; | |
19 | gpio5 = &pio5; | |
20 | gpio6 = &pio6; | |
21 | gpio7 = &pio7; | |
22 | gpio8 = &pio8; | |
23 | gpio9 = &pio9; | |
24 | gpio10 = &pio10; | |
25 | gpio11 = &pio11; | |
26 | gpio12 = &pio12; | |
27 | gpio13 = &pio13; | |
28 | gpio14 = &pio14; | |
29 | gpio15 = &pio15; | |
30 | gpio16 = &pio16; | |
31 | gpio17 = &pio17; | |
32 | gpio18 = &pio18; | |
33 | gpio19 = &pio100; | |
34 | gpio20 = &pio101; | |
35 | gpio21 = &pio102; | |
36 | gpio22 = &pio103; | |
37 | gpio23 = &pio104; | |
38 | gpio24 = &pio105; | |
39 | gpio25 = &pio106; | |
40 | gpio26 = &pio107; | |
65ebcc11 SK |
41 | }; |
42 | ||
43 | soc { | |
44 | pin-controller-sbc { | |
45 | #address-cells = <1>; | |
46 | #size-cells = <1>; | |
47 | compatible = "st,stih415-sbc-pinctrl"; | |
48 | st,syscfg = <&syscfg_sbc>; | |
7ec5183a SK |
49 | reg = <0xfe61f080 0x4>; |
50 | reg-names = "irqmux"; | |
51 | interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 52 | interrupt-names = "irqmux"; |
65ebcc11 SK |
53 | ranges = <0 0xfe610000 0x5000>; |
54 | ||
dc62bfdf | 55 | pio0: gpio@fe610000 { |
65ebcc11 SK |
56 | gpio-controller; |
57 | #gpio-cells = <1>; | |
7ec5183a SK |
58 | interrupt-controller; |
59 | #interrupt-cells = <2>; | |
65ebcc11 SK |
60 | reg = <0 0x100>; |
61 | st,bank-name = "PIO0"; | |
62 | }; | |
dc62bfdf | 63 | pio1: gpio@fe611000 { |
65ebcc11 SK |
64 | gpio-controller; |
65 | #gpio-cells = <1>; | |
7ec5183a SK |
66 | interrupt-controller; |
67 | #interrupt-cells = <2>; | |
65ebcc11 SK |
68 | reg = <0x1000 0x100>; |
69 | st,bank-name = "PIO1"; | |
70 | }; | |
dc62bfdf | 71 | pio2: gpio@fe612000 { |
65ebcc11 SK |
72 | gpio-controller; |
73 | #gpio-cells = <1>; | |
7ec5183a SK |
74 | interrupt-controller; |
75 | #interrupt-cells = <2>; | |
65ebcc11 SK |
76 | reg = <0x2000 0x100>; |
77 | st,bank-name = "PIO2"; | |
78 | }; | |
dc62bfdf | 79 | pio3: gpio@fe613000 { |
65ebcc11 SK |
80 | gpio-controller; |
81 | #gpio-cells = <1>; | |
7ec5183a SK |
82 | interrupt-controller; |
83 | #interrupt-cells = <2>; | |
65ebcc11 SK |
84 | reg = <0x3000 0x100>; |
85 | st,bank-name = "PIO3"; | |
86 | }; | |
dc62bfdf | 87 | pio4: gpio@fe614000 { |
65ebcc11 SK |
88 | gpio-controller; |
89 | #gpio-cells = <1>; | |
7ec5183a SK |
90 | interrupt-controller; |
91 | #interrupt-cells = <2>; | |
65ebcc11 SK |
92 | reg = <0x4000 0x100>; |
93 | st,bank-name = "PIO4"; | |
94 | }; | |
95 | ||
96 | sbc_serial1 { | |
97 | pinctrl_sbc_serial1:sbc_serial1 { | |
98 | st,pins { | |
dc62bfdf LJ |
99 | tx = <&pio2 6 ALT3 OUT>; |
100 | rx = <&pio2 7 ALT3 IN>; | |
65ebcc11 SK |
101 | }; |
102 | }; | |
103 | }; | |
5bbb7527 | 104 | |
c316d7d4 GF |
105 | keyscan { |
106 | pinctrl_keyscan: keyscan { | |
107 | st,pins { | |
dc62bfdf LJ |
108 | keyin0 = <&pio0 2 ALT2 IN>; |
109 | keyin1 = <&pio0 3 ALT2 IN>; | |
110 | keyin2 = <&pio0 4 ALT2 IN>; | |
111 | keyin3 = <&pio2 6 ALT2 IN>; | |
112 | ||
113 | keyout0 = <&pio1 6 ALT2 OUT>; | |
114 | keyout1 = <&pio1 7 ALT2 OUT>; | |
115 | keyout2 = <&pio0 6 ALT2 OUT>; | |
116 | keyout3 = <&pio2 7 ALT2 OUT>; | |
c316d7d4 GF |
117 | }; |
118 | }; | |
119 | }; | |
120 | ||
5bbb7527 MC |
121 | sbc_i2c0 { |
122 | pinctrl_sbc_i2c0_default: sbc_i2c0-default { | |
123 | st,pins { | |
dc62bfdf LJ |
124 | sda = <&pio4 6 ALT1 BIDIR>; |
125 | scl = <&pio4 5 ALT1 BIDIR>; | |
5bbb7527 MC |
126 | }; |
127 | }; | |
128 | }; | |
129 | ||
130 | sbc_i2c1 { | |
131 | pinctrl_sbc_i2c1_default: sbc_i2c1-default { | |
132 | st,pins { | |
dc62bfdf LJ |
133 | sda = <&pio3 2 ALT2 BIDIR>; |
134 | scl = <&pio3 1 ALT2 BIDIR>; | |
5bbb7527 MC |
135 | }; |
136 | }; | |
137 | }; | |
c80fe335 | 138 | |
8ccd3f3a SK |
139 | rc{ |
140 | pinctrl_ir: ir0 { | |
141 | st,pins { | |
dc62bfdf | 142 | ir = <&pio4 0 ALT2 IN>; |
8ccd3f3a SK |
143 | }; |
144 | }; | |
145 | }; | |
146 | ||
c80fe335 SK |
147 | gmac1 { |
148 | pinctrl_mii1: mii1 { | |
149 | st,pins { | |
dc62bfdf LJ |
150 | txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>; |
151 | txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
152 | txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
153 | txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
154 | txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
155 | txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>; | |
156 | txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; | |
157 | col = <&pio0 7 ALT1 IN BYPASS 1000>; | |
158 | mdio = <&pio1 0 ALT1 OUT BYPASS 0>; | |
159 | mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; | |
160 | crs = <&pio1 2 ALT1 IN BYPASS 1000>; | |
161 | mdint = <&pio1 3 ALT1 IN BYPASS 0>; | |
162 | rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
163 | rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
164 | rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
165 | rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
166 | rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
167 | rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>; | |
168 | rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; | |
169 | phyclk = <&pio2 3 ALT1 IN NICLK 1000 CLK_A>; | |
c80fe335 SK |
170 | }; |
171 | }; | |
172 | ||
173 | pinctrl_rgmii1: rgmii1-0 { | |
174 | st,pins { | |
dc62bfdf LJ |
175 | txd0 = <&pio0 0 ALT1 OUT DE_IO 1000 CLK_A>; |
176 | txd1 = <&pio0 1 ALT1 OUT DE_IO 1000 CLK_A>; | |
177 | txd2 = <&pio0 2 ALT1 OUT DE_IO 1000 CLK_A>; | |
178 | txd3 = <&pio0 3 ALT1 OUT DE_IO 1000 CLK_A>; | |
179 | txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>; | |
180 | txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>; | |
181 | mdio = <&pio1 0 ALT1 OUT BYPASS 0>; | |
182 | mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>; | |
183 | rxd0 = <&pio1 4 ALT1 IN DE_IO 0 CLK_A>; | |
184 | rxd1 = <&pio1 5 ALT1 IN DE_IO 0 CLK_A>; | |
185 | rxd2 = <&pio1 6 ALT1 IN DE_IO 0 CLK_A>; | |
186 | rxd3 = <&pio1 7 ALT1 IN DE_IO 0 CLK_A>; | |
187 | ||
188 | rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>; | |
189 | rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>; | |
190 | phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>; | |
191 | ||
192 | clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>; | |
c80fe335 SK |
193 | }; |
194 | }; | |
195 | }; | |
65ebcc11 SK |
196 | }; |
197 | ||
198 | pin-controller-front { | |
199 | #address-cells = <1>; | |
200 | #size-cells = <1>; | |
201 | compatible = "st,stih415-front-pinctrl"; | |
202 | st,syscfg = <&syscfg_front>; | |
7ec5183a SK |
203 | reg = <0xfee0f080 0x4>; |
204 | reg-names = "irqmux"; | |
205 | interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 206 | interrupt-names = "irqmux"; |
65ebcc11 SK |
207 | ranges = <0 0xfee00000 0x8000>; |
208 | ||
dc62bfdf | 209 | pio5: gpio@fee00000 { |
65ebcc11 SK |
210 | gpio-controller; |
211 | #gpio-cells = <1>; | |
7ec5183a SK |
212 | interrupt-controller; |
213 | #interrupt-cells = <2>; | |
65ebcc11 SK |
214 | reg = <0 0x100>; |
215 | st,bank-name = "PIO5"; | |
216 | }; | |
dc62bfdf | 217 | pio6: gpio@fee01000 { |
65ebcc11 SK |
218 | gpio-controller; |
219 | #gpio-cells = <1>; | |
7ec5183a SK |
220 | interrupt-controller; |
221 | #interrupt-cells = <2>; | |
65ebcc11 SK |
222 | reg = <0x1000 0x100>; |
223 | st,bank-name = "PIO6"; | |
224 | }; | |
dc62bfdf | 225 | pio7: gpio@fee02000 { |
65ebcc11 SK |
226 | gpio-controller; |
227 | #gpio-cells = <1>; | |
7ec5183a SK |
228 | interrupt-controller; |
229 | #interrupt-cells = <2>; | |
65ebcc11 SK |
230 | reg = <0x2000 0x100>; |
231 | st,bank-name = "PIO7"; | |
232 | }; | |
dc62bfdf | 233 | pio8: gpio@fee03000 { |
65ebcc11 SK |
234 | gpio-controller; |
235 | #gpio-cells = <1>; | |
7ec5183a SK |
236 | interrupt-controller; |
237 | #interrupt-cells = <2>; | |
65ebcc11 SK |
238 | reg = <0x3000 0x100>; |
239 | st,bank-name = "PIO8"; | |
240 | }; | |
dc62bfdf | 241 | pio9: gpio@fee04000 { |
65ebcc11 SK |
242 | gpio-controller; |
243 | #gpio-cells = <1>; | |
7ec5183a SK |
244 | interrupt-controller; |
245 | #interrupt-cells = <2>; | |
65ebcc11 SK |
246 | reg = <0x4000 0x100>; |
247 | st,bank-name = "PIO9"; | |
248 | }; | |
dc62bfdf | 249 | pio10: gpio@fee05000 { |
65ebcc11 SK |
250 | gpio-controller; |
251 | #gpio-cells = <1>; | |
7ec5183a SK |
252 | interrupt-controller; |
253 | #interrupt-cells = <2>; | |
65ebcc11 SK |
254 | reg = <0x5000 0x100>; |
255 | st,bank-name = "PIO10"; | |
256 | }; | |
dc62bfdf | 257 | pio11: gpio@fee06000 { |
65ebcc11 SK |
258 | gpio-controller; |
259 | #gpio-cells = <1>; | |
7ec5183a SK |
260 | interrupt-controller; |
261 | #interrupt-cells = <2>; | |
65ebcc11 SK |
262 | reg = <0x6000 0x100>; |
263 | st,bank-name = "PIO11"; | |
264 | }; | |
dc62bfdf | 265 | pio12: gpio@fee07000 { |
65ebcc11 SK |
266 | gpio-controller; |
267 | #gpio-cells = <1>; | |
7ec5183a SK |
268 | interrupt-controller; |
269 | #interrupt-cells = <2>; | |
65ebcc11 SK |
270 | reg = <0x7000 0x100>; |
271 | st,bank-name = "PIO12"; | |
272 | }; | |
5bbb7527 MC |
273 | |
274 | i2c0 { | |
275 | pinctrl_i2c0_default: i2c0-default { | |
276 | st,pins { | |
dc62bfdf LJ |
277 | sda = <&pio9 3 ALT1 BIDIR>; |
278 | scl = <&pio9 2 ALT1 BIDIR>; | |
5bbb7527 MC |
279 | }; |
280 | }; | |
281 | }; | |
282 | ||
283 | i2c1 { | |
284 | pinctrl_i2c1_default: i2c1-default { | |
285 | st,pins { | |
dc62bfdf LJ |
286 | sda = <&pio12 1 ALT1 BIDIR>; |
287 | scl = <&pio12 0 ALT1 BIDIR>; | |
5bbb7527 MC |
288 | }; |
289 | }; | |
290 | }; | |
65ebcc11 SK |
291 | }; |
292 | ||
293 | pin-controller-rear { | |
294 | #address-cells = <1>; | |
295 | #size-cells = <1>; | |
296 | compatible = "st,stih415-rear-pinctrl"; | |
297 | st,syscfg = <&syscfg_rear>; | |
7ec5183a SK |
298 | reg = <0xfe82f080 0x4>; |
299 | reg-names = "irqmux"; | |
300 | interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 301 | interrupt-names = "irqmux"; |
65ebcc11 SK |
302 | ranges = <0 0xfe820000 0x8000>; |
303 | ||
dc62bfdf | 304 | pio13: gpio@fe820000 { |
65ebcc11 SK |
305 | gpio-controller; |
306 | #gpio-cells = <1>; | |
7ec5183a SK |
307 | interrupt-controller; |
308 | #interrupt-cells = <2>; | |
65ebcc11 SK |
309 | reg = <0 0x100>; |
310 | st,bank-name = "PIO13"; | |
311 | }; | |
dc62bfdf | 312 | pio14: gpio@fe821000 { |
65ebcc11 SK |
313 | gpio-controller; |
314 | #gpio-cells = <1>; | |
7ec5183a SK |
315 | interrupt-controller; |
316 | #interrupt-cells = <2>; | |
65ebcc11 SK |
317 | reg = <0x1000 0x100>; |
318 | st,bank-name = "PIO14"; | |
319 | }; | |
dc62bfdf | 320 | pio15: gpio@fe822000 { |
65ebcc11 SK |
321 | gpio-controller; |
322 | #gpio-cells = <1>; | |
7ec5183a SK |
323 | interrupt-controller; |
324 | #interrupt-cells = <2>; | |
65ebcc11 SK |
325 | reg = <0x2000 0x100>; |
326 | st,bank-name = "PIO15"; | |
327 | }; | |
dc62bfdf | 328 | pio16: gpio@fe823000 { |
65ebcc11 SK |
329 | gpio-controller; |
330 | #gpio-cells = <1>; | |
7ec5183a SK |
331 | interrupt-controller; |
332 | #interrupt-cells = <2>; | |
65ebcc11 SK |
333 | reg = <0x3000 0x100>; |
334 | st,bank-name = "PIO16"; | |
335 | }; | |
dc62bfdf | 336 | pio17: gpio@fe824000 { |
65ebcc11 SK |
337 | gpio-controller; |
338 | #gpio-cells = <1>; | |
7ec5183a SK |
339 | interrupt-controller; |
340 | #interrupt-cells = <2>; | |
65ebcc11 SK |
341 | reg = <0x4000 0x100>; |
342 | st,bank-name = "PIO17"; | |
343 | }; | |
dc62bfdf | 344 | pio18: gpio@fe825000 { |
65ebcc11 SK |
345 | gpio-controller; |
346 | #gpio-cells = <1>; | |
7ec5183a SK |
347 | interrupt-controller; |
348 | #interrupt-cells = <2>; | |
65ebcc11 SK |
349 | reg = <0x5000 0x100>; |
350 | st,bank-name = "PIO18"; | |
351 | }; | |
352 | ||
353 | serial2 { | |
354 | pinctrl_serial2: serial2-0 { | |
355 | st,pins { | |
dc62bfdf LJ |
356 | tx = <&pio17 4 ALT2 OUT>; |
357 | rx = <&pio17 5 ALT2 IN>; | |
65ebcc11 SK |
358 | }; |
359 | }; | |
360 | }; | |
c80fe335 SK |
361 | |
362 | gmac0{ | |
363 | pinctrl_mii0: mii0 { | |
364 | st,pins { | |
dc62bfdf LJ |
365 | mdint = <&pio13 6 ALT2 IN BYPASS 0>; |
366 | txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
367 | ||
368 | txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
369 | txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
370 | txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>; | |
371 | txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>; | |
372 | ||
373 | txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; | |
374 | txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>; | |
375 | crs = <&pio15 2 ALT2 IN BYPASS 1000>; | |
376 | col = <&pio15 3 ALT2 IN BYPASS 1000>; | |
377 | mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; | |
378 | mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; | |
379 | ||
380 | rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
381 | rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
382 | rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
383 | rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
384 | rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
385 | rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>; | |
386 | rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; | |
387 | phyclk = <&pio13 5 ALT2 OUT NICLK 1000 CLK_A>; | |
c80fe335 SK |
388 | |
389 | }; | |
390 | }; | |
391 | ||
392 | pinctrl_gmii0: gmii0 { | |
393 | st,pins { | |
dc62bfdf LJ |
394 | mdint = <&pio13 6 ALT2 IN BYPASS 0>; |
395 | mdio = <&pio15 4 ALT2 OUT BYPASS 3000>; | |
396 | mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>; | |
397 | txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; | |
398 | ||
399 | txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; | |
400 | txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; | |
401 | txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
402 | txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
403 | txd4 = <&pio14 4 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
404 | txd5 = <&pio14 5 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
405 | txd6 = <&pio14 6 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
406 | txd7 = <&pio14 7 ALT2 OUT SE_NICLK_IO 3000 CLK_B>; | |
407 | ||
408 | txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>; | |
409 | txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 3000 CLK_A>; | |
410 | crs = <&pio15 2 ALT2 IN BYPASS 1000>; | |
411 | col = <&pio15 3 ALT2 IN BYPASS 1000>; | |
412 | rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
413 | rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
414 | ||
415 | rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
416 | rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
417 | rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
418 | rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
419 | rxd4 = <&pio16 4 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
420 | rxd5 = <&pio16 5 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
421 | rxd6 = <&pio16 6 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
422 | rxd7 = <&pio16 7 ALT2 IN SE_NICLK_IO 1500 CLK_A>; | |
423 | ||
424 | rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>; | |
425 | clk125 = <&pio17 6 ALT1 IN NICLK 0 CLK_A>; | |
426 | phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>; | |
c80fe335 SK |
427 | |
428 | ||
429 | }; | |
430 | }; | |
431 | }; | |
14304e00 PG |
432 | |
433 | mmc0 { | |
434 | pinctrl_mmc0: mmc0 { | |
435 | st,pins { | |
436 | mmcclk = <&pio13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>; | |
437 | data0 = <&pio14 4 ALT4 BIDIR_PU BYPASS 0>; | |
438 | data1 = <&pio14 5 ALT4 BIDIR_PU BYPASS 0>; | |
439 | data2 = <&pio14 6 ALT4 BIDIR_PU BYPASS 0>; | |
440 | data3 = <&pio14 7 ALT4 BIDIR_PU BYPASS 0>; | |
441 | cmd = <&pio15 1 ALT4 BIDIR_PU BYPASS 0>; | |
442 | wp = <&pio15 3 ALT4 IN>; | |
443 | data4 = <&pio16 4 ALT4 BIDIR_PU BYPASS 0>; | |
444 | data5 = <&pio16 5 ALT4 BIDIR_PU BYPASS 0>; | |
445 | data6 = <&pio16 6 ALT4 BIDIR_PU BYPASS 0>; | |
446 | data7 = <&pio16 7 ALT4 BIDIR_PU BYPASS 0>; | |
447 | pwr = <&pio17 1 ALT4 OUT>; | |
448 | cd = <&pio17 2 ALT4 IN>; | |
449 | led = <&pio17 3 ALT4 OUT>; | |
450 | }; | |
451 | }; | |
452 | }; | |
65ebcc11 SK |
453 | }; |
454 | ||
455 | pin-controller-left { | |
456 | #address-cells = <1>; | |
457 | #size-cells = <1>; | |
458 | compatible = "st,stih415-left-pinctrl"; | |
459 | st,syscfg = <&syscfg_left>; | |
7ec5183a SK |
460 | reg = <0xfd6bf080 0x4>; |
461 | reg-names = "irqmux"; | |
462 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 463 | interrupt-names = "irqmux"; |
65ebcc11 SK |
464 | ranges = <0 0xfd6b0000 0x3000>; |
465 | ||
dc62bfdf | 466 | pio100: gpio@fd6b0000 { |
65ebcc11 SK |
467 | gpio-controller; |
468 | #gpio-cells = <1>; | |
7ec5183a SK |
469 | interrupt-controller; |
470 | #interrupt-cells = <2>; | |
65ebcc11 SK |
471 | reg = <0 0x100>; |
472 | st,bank-name = "PIO100"; | |
473 | }; | |
dc62bfdf | 474 | pio101: gpio@fd6b1000 { |
65ebcc11 SK |
475 | gpio-controller; |
476 | #gpio-cells = <1>; | |
7ec5183a SK |
477 | interrupt-controller; |
478 | #interrupt-cells = <2>; | |
65ebcc11 SK |
479 | reg = <0x1000 0x100>; |
480 | st,bank-name = "PIO101"; | |
481 | }; | |
dc62bfdf | 482 | pio102: gpio@fd6b2000 { |
65ebcc11 SK |
483 | gpio-controller; |
484 | #gpio-cells = <1>; | |
7ec5183a SK |
485 | interrupt-controller; |
486 | #interrupt-cells = <2>; | |
65ebcc11 SK |
487 | reg = <0x2000 0x100>; |
488 | st,bank-name = "PIO102"; | |
489 | }; | |
490 | }; | |
491 | ||
492 | pin-controller-right { | |
493 | #address-cells = <1>; | |
494 | #size-cells = <1>; | |
495 | compatible = "st,stih415-right-pinctrl"; | |
496 | st,syscfg = <&syscfg_right>; | |
7ec5183a SK |
497 | reg = <0xfd33f080 0x4>; |
498 | reg-names = "irqmux"; | |
499 | interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
ae107d06 | 500 | interrupt-names = "irqmux"; |
65ebcc11 SK |
501 | ranges = <0 0xfd330000 0x5000>; |
502 | ||
dc62bfdf | 503 | pio103: gpio@fd330000 { |
65ebcc11 SK |
504 | gpio-controller; |
505 | #gpio-cells = <1>; | |
7ec5183a SK |
506 | interrupt-controller; |
507 | #interrupt-cells = <2>; | |
65ebcc11 SK |
508 | reg = <0 0x100>; |
509 | st,bank-name = "PIO103"; | |
510 | }; | |
dc62bfdf | 511 | pio104: gpio@fd331000 { |
65ebcc11 SK |
512 | gpio-controller; |
513 | #gpio-cells = <1>; | |
7ec5183a SK |
514 | interrupt-controller; |
515 | #interrupt-cells = <2>; | |
65ebcc11 SK |
516 | reg = <0x1000 0x100>; |
517 | st,bank-name = "PIO104"; | |
518 | }; | |
dc62bfdf | 519 | pio105: gpio@fd332000 { |
65ebcc11 SK |
520 | gpio-controller; |
521 | #gpio-cells = <1>; | |
7ec5183a SK |
522 | interrupt-controller; |
523 | #interrupt-cells = <2>; | |
65ebcc11 SK |
524 | reg = <0x2000 0x100>; |
525 | st,bank-name = "PIO105"; | |
526 | }; | |
dc62bfdf | 527 | pio106: gpio@fd333000 { |
65ebcc11 SK |
528 | gpio-controller; |
529 | #gpio-cells = <1>; | |
7ec5183a SK |
530 | interrupt-controller; |
531 | #interrupt-cells = <2>; | |
65ebcc11 SK |
532 | reg = <0x3000 0x100>; |
533 | st,bank-name = "PIO106"; | |
534 | }; | |
dc62bfdf | 535 | pio107: gpio@fd334000 { |
65ebcc11 SK |
536 | gpio-controller; |
537 | #gpio-cells = <1>; | |
7ec5183a SK |
538 | interrupt-controller; |
539 | #interrupt-cells = <2>; | |
65ebcc11 SK |
540 | reg = <0x4000 0x100>; |
541 | st,bank-name = "PIO107"; | |
542 | }; | |
543 | }; | |
544 | }; | |
545 | }; |