[deliverable/linux.git] / arch / arm / boot / dts / stih416-pinctrl.dtsi


/*
 * Copyright (C) 2013 STMicroelectronics Limited.
 * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * publishhed by the Free Software Foundation.
 */
#include "st-pincfg.h"
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {

	aliases {
		gpio0	= &pio0;
		gpio1	= &pio1;
		gpio2	= &pio2;
		gpio3	= &pio3;
		gpio4	= &pio4;
		gpio5	= &pio40;
		gpio6	= &pio5;
		gpio7	= &pio6;
		gpio8	= &pio7;
		gpio9	= &pio8;
		gpio10	= &pio9;
		gpio11	= &pio10;
		gpio12	= &pio11;
		gpio13	= &pio12;
		gpio14	= &pio30;
		gpio15	= &pio31;
		gpio16	= &pio13;
		gpio17	= &pio14;
		gpio18	= &pio15;
		gpio19	= &pio16;
		gpio20	= &pio17;
		gpio21	= &pio18;
		gpio22	= &pio100;
		gpio23	= &pio101;
		gpio24	= &pio102;
		gpio25	= &pio103;
		gpio26	= &pio104;
		gpio27	= &pio105;
		gpio28	= &pio106;
		gpio29	= &pio107;
	};

	soc {
		pin-controller-sbc {
			#address-cells	= <1>;
			#size-cells	= <1>;
			compatible	= "st,stih416-sbc-pinctrl";
			st,syscfg	= <&syscfg_sbc>;
			reg 		= <0xfe61f080 0x4>;
			reg-names	= "irqmux";
			interrupts 	= <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names	= "irqmux";
			ranges		= <0 0xfe610000 0x6000>;

			pio0: gpio@fe610000 {
				gpio-controller;
				#gpio-cells = <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0 0x100>;
				st,bank-name	= "PIO0";
			};
			pio1: gpio@fe611000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x1000 0x100>;
				st,bank-name	= "PIO1";
			};
			pio2: gpio@fe612000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x2000 0x100>;
				st,bank-name	= "PIO2";
			};
			pio3: gpio@fe613000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x3000 0x100>;
				st,bank-name	= "PIO3";
			};
			pio4: gpio@fe614000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x4000 0x100>;
				st,bank-name	= "PIO4";
			};
			pio40: gpio@fe615000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x5000 0x100>;
				st,bank-name	= "PIO40";
				st,retime-pin-mask = <0x7f>;
			};

			rc{
				pinctrl_ir: ir0 {
					st,pins {
						ir = <&pio4 0 ALT2 IN>;
					};
				};
			};
			sbc_serial1 {
				pinctrl_sbc_serial1: sbc_serial1 {
					st,pins {
						tx	= <&pio2 6 ALT3 OUT>;
						rx	= <&pio2 7 ALT3 IN>;
					};
				};
			};

			keyscan {
				pinctrl_keyscan: keyscan {
					st,pins {
						keyin0 = <&pio0 2 ALT2 IN>;
						keyin1 = <&pio0 3 ALT2 IN>;
						keyin2 = <&pio0 4 ALT2 IN>;
						keyin3 = <&pio2 6 ALT2 IN>;

						keyout0 = <&pio1 6 ALT2 OUT>;
						keyout1 = <&pio1 7 ALT2 OUT>;
						keyout2 = <&pio0 6 ALT2 OUT>;
						keyout3 = <&pio2 7 ALT2 OUT>;
					};
				};
			};

			sbc_i2c0 {
				pinctrl_sbc_i2c0_default: sbc_i2c0-default {
					st,pins {
						sda = <&pio4 6 ALT1 BIDIR>;
						scl = <&pio4 5 ALT1 BIDIR>;
					};
				};
			};

			sbc_i2c1 {
				pinctrl_sbc_i2c1_default: sbc_i2c1-default {
					st,pins {
						sda = <&pio3 2 ALT2 BIDIR>;
						scl = <&pio3 1 ALT2 BIDIR>;
					};
				};
			};

			gmac1 {
				pinctrl_mii1: mii1 {
					st,pins {
						txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
						txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
						col =   <&pio0 7 ALT1 IN BYPASS 1000>;

						mdio =  <&pio1 0 ALT1 OUT BYPASS 1500>;
						mdc =   <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
						crs =   <&pio1 2 ALT1 IN BYPASS 1000>;
						mdint = <&pio1 3 ALT1 IN BYPASS 0>;
						rxd0 =  <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rxd1 =  <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rxd2 =  <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rxd3 =  <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;

						rxdv =  <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
						rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
						phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
					};
				};
				pinctrl_rgmii1: rgmii1-0 {
					st,pins {
						txd0 =  <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
						txd1 =  <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
						txd2 =  <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
						txd3 =  <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
						txen =  <&pio0 5 ALT1 OUT DE_IO 0   CLK_A>;
						txclk = <&pio0 6 ALT1 IN  NICLK 0   CLK_A>;

						mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
						mdc  = <&pio1 1 ALT1 OUT NICLK  0 CLK_A>;
						rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
						rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
						rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
						rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;

						rxdv   = <&pio2 0 ALT1 IN  DE_IO 500 CLK_A>;
						rxclk  = <&pio2 2 ALT1 IN  NICLK 0   CLK_A>;
						phyclk = <&pio2 3 ALT4 OUT NICLK 0   CLK_B>;

						clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
					};
				};
			};
		};

		pin-controller-front {
			#address-cells	= <1>;
			#size-cells	= <1>;
			compatible	= "st,stih416-front-pinctrl";
			st,syscfg	= <&syscfg_front>;
			reg 		= <0xfee0f080 0x4>;
			reg-names	= "irqmux";
			interrupts 	= <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names	= "irqmux";
			ranges		= <0 0xfee00000 0x10000>;

			pio5: gpio@fee00000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0 0x100>;
				st,bank-name	= "PIO5";
			};
			pio6: gpio@fee01000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x1000 0x100>;
				st,bank-name	= "PIO6";
			};
			pio7: gpio@fee02000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x2000 0x100>;
				st,bank-name	= "PIO7";
			};
			pio8: gpio@fee03000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x3000 0x100>;
				st,bank-name	= "PIO8";
			};
			pio9: gpio@fee04000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x4000 0x100>;
				st,bank-name	= "PIO9";
			};
			pio10: gpio@fee05000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x5000 0x100>;
				st,bank-name	= "PIO10";
			};
			pio11: gpio@fee06000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x6000 0x100>;
				st,bank-name	= "PIO11";
			};
			pio12: gpio@fee07000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x7000 0x100>;
				st,bank-name	= "PIO12";
			};
			pio30: gpio@fee08000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x8000 0x100>;
				st,bank-name	= "PIO30";
			};
			pio31: gpio@fee09000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x9000 0x100>;
				st,bank-name	= "PIO31";
			};

			serial2-oe {
				pinctrl_serial2_oe: serial2-1 {
					st,pins {
						output-enable	= <&pio11 3 ALT2 OUT>;
					};
				};
			};

			i2c0 {
				pinctrl_i2c0_default: i2c0-default {
					st,pins {
						sda = <&pio9 3 ALT1 BIDIR>;
						scl = <&pio9 2 ALT1 BIDIR>;
					};
				};
			};

			i2c1 {
				pinctrl_i2c1_default: i2c1-default {
					st,pins {
						sda = <&pio12 1 ALT1 BIDIR>;
						scl = <&pio12 0 ALT1 BIDIR>;
					};
				};
			};

			fsm {
				pinctrl_fsm: fsm {
					st,pins {
						spi-fsm-clk  = <&pio12 2 ALT1 OUT>;
						spi-fsm-cs   = <&pio12 3 ALT1 OUT>;
						spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
						spi-fsm-miso = <&pio12 5 ALT1 IN>;
						spi-fsm-hol  = <&pio12 6 ALT1 OUT>;
						spi-fsm-wp   = <&pio12 7 ALT1 OUT>;
					};
				};
			};
		};

		pin-controller-rear {
			#address-cells	= <1>;
			#size-cells	= <1>;
			compatible	= "st,stih416-rear-pinctrl";
			st,syscfg	= <&syscfg_rear>;
			reg 		= <0xfe82f080 0x4>;
			reg-names	= "irqmux";
			interrupts 	= <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names	= "irqmux";
			ranges 		= <0 0xfe820000 0x6000>;

			pio13: gpio@fe820000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0 0x100>;
				st,bank-name	= "PIO13";
			};
			pio14: gpio@fe821000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x1000 0x100>;
				st,bank-name	= "PIO14";
			};
			pio15: gpio@fe822000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x2000 0x100>;
				st,bank-name	= "PIO15";
			};
			pio16: gpio@fe823000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x3000 0x100>;
				st,bank-name	= "PIO16";
			};
			pio17: gpio@fe824000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x4000 0x100>;
				st,bank-name	= "PIO17";
			};
			pio18: gpio@fe825000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x5000 0x100>;
				st,bank-name	= "PIO18";
				st,retime-pin-mask = <0xf>;
			};

			serial2 {
				pinctrl_serial2: serial2-0 {
					st,pins {
						tx	= <&pio17 4 ALT2 OUT>;
						rx	= <&pio17 5 ALT2 IN>;
					};
				};
			};

			gmac0 {
				pinctrl_mii0: mii0 {
					st,pins {
						mdint = <&pio13 6 ALT2 IN  BYPASS      0>;
						txen =  <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
						txd0 =  <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
						txd1 =  <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
						txd2 =  <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
						txd3 =  <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;

						txclk = <&pio15 0 ALT2 IN  NICLK       0 CLK_A>;
						txer =  <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
						crs = <&pio15 2 ALT2 IN  BYPASS 1000>;
						col = <&pio15 3 ALT2 IN  BYPASS 1000>;
						mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
						mdc = <&pio15 5 ALT2 OUT NICLK  0    CLK_B>;

						rxd0 =  <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						rxd1 =  <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						rxd2 =  <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						rxd3 =  <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						rxdv =  <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
						rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
						phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
					};
				};

				pinctrl_gmii0: gmii0 {
					st,pins {
						};
				};
				pinctrl_rgmii0: rgmii0 {
					st,pins {
						 phyclk = <&pio13  5 ALT4 OUT NICLK 0 CLK_B>;
						 txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
						 txd0  = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
						 txd1  = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
						 txd2  = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
						 txd3  = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
						 txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;

						 mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
						 mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;

						 rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
						 rxd0 =<&pio16 0 ALT2 IN DE_IO	500 CLK_A>;
						 rxd1 =<&pio16 1 ALT2 IN DE_IO	500 CLK_A>;
						 rxd2 =<&pio16 2 ALT2 IN DE_IO	500 CLK_A>;
						 rxd3  =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
						 rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;

						 clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
					};
				};
			};
		};

		pin-controller-fvdp-fe {
			#address-cells	= <1>;
			#size-cells	= <1>;
			compatible	= "st,stih416-fvdp-fe-pinctrl";
			st,syscfg	= <&syscfg_fvdp_fe>;
			reg 		= <0xfd6bf080 0x4>;
			reg-names	= "irqmux";
			interrupts 	= <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names	= "irqmux";
			ranges		= <0 0xfd6b0000 0x3000>;

			pio100: gpio@fd6b0000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0 0x100>;
				st,bank-name	= "PIO100";
			};
			pio101: gpio@fd6b1000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x1000 0x100>;
				st,bank-name	= "PIO101";
			};
			pio102: gpio@fd6b2000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x2000 0x100>;
				st,bank-name	= "PIO102";
			};
		};

		pin-controller-fvdp-lite {
			#address-cells	= <1>;
			#size-cells	= <1>;
			compatible	= "st,stih416-fvdp-lite-pinctrl";
			st,syscfg		= <&syscfg_fvdp_lite>;
			reg 		= <0xfd33f080 0x4>;
			reg-names	= "irqmux";
			interrupts 	= <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names	= "irqmux";
			ranges			= <0 0xfd330000 0x5000>;

			pio103: gpio@fd330000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0 0x100>;
				st,bank-name	= "PIO103";
			};
			pio104: gpio@fd331000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x1000 0x100>;
				st,bank-name	= "PIO104";
			};
			pio105: gpio@fd332000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x2000 0x100>;
				st,bank-name	= "PIO105";
			};
			pio106: gpio@fd333000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x3000 0x100>;
				st,bank-name	= "PIO106";
			};

			pio107: gpio@fd334000 {
				gpio-controller;
				#gpio-cells	= <1>;
				interrupt-controller;
				#interrupt-cells = <2>;
				reg		= <0x4000 0x100>;
				st,bank-name	= "PIO107";
				st,retime-pin-mask = <0xf>;
			};
		};
	};
};
Commit	Line	Data
15969b45 SK	1
	2	/*
	3	* Copyright (C) 2013 STMicroelectronics Limited.
	4	* Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* publishhed by the Free Software Foundation.
	9	*/
	10	#include "st-pincfg.h"
bdda8b05	11	#include <dt-bindings/interrupt-controller/arm-gic.h>
15969b45 SK	12	/ {
	13
	14	aliases {
dc62bfdf LJ	15	gpio0 = &pio0;
	16	gpio1 = &pio1;
	17	gpio2 = &pio2;
	18	gpio3 = &pio3;
	19	gpio4 = &pio4;
	20	gpio5 = &pio40;
	21	gpio6 = &pio5;
	22	gpio7 = &pio6;
	23	gpio8 = &pio7;
	24	gpio9 = &pio8;
	25	gpio10 = &pio9;
	26	gpio11 = &pio10;
	27	gpio12 = &pio11;
	28	gpio13 = &pio12;
	29	gpio14 = &pio30;
	30	gpio15 = &pio31;
	31	gpio16 = &pio13;
	32	gpio17 = &pio14;
	33	gpio18 = &pio15;
	34	gpio19 = &pio16;
	35	gpio20 = &pio17;
	36	gpio21 = &pio18;
	37	gpio22 = &pio100;
	38	gpio23 = &pio101;
	39	gpio24 = &pio102;
	40	gpio25 = &pio103;
	41	gpio26 = &pio104;
	42	gpio27 = &pio105;
	43	gpio28 = &pio106;
	44	gpio29 = &pio107;
15969b45 SK	45	};
	46
	47	soc {
	48	pin-controller-sbc {
	49	#address-cells = <1>;
	50	#size-cells = <1>;
	51	compatible = "st,stih416-sbc-pinctrl";
	52	st,syscfg = <&syscfg_sbc>;
bdda8b05 SK	53	reg = <0xfe61f080 0x4>;
	54	reg-names = "irqmux";
	55	interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
ae107d06	56	interrupt-names = "irqmux";
15969b45 SK	57	ranges = <0 0xfe610000 0x6000>;
15969b45 SK	58
dc62bfdf	59	pio0: gpio@fe610000 {
15969b45 SK	60	gpio-controller;
15969b45 SK	61	#gpio-cells = <1>;
bdda8b05 SK	62	interrupt-controller;
bdda8b05 SK	63	#interrupt-cells = <2>;
15969b45 SK	64	reg = <0 0x100>;
	65	st,bank-name = "PIO0";
	66	};
dc62bfdf	67	pio1: gpio@fe611000 {
15969b45 SK	68	gpio-controller;
15969b45 SK	69	#gpio-cells = <1>;
bdda8b05 SK	70	interrupt-controller;
bdda8b05 SK	71	#interrupt-cells = <2>;
15969b45 SK	72	reg = <0x1000 0x100>;
	73	st,bank-name = "PIO1";
	74	};
dc62bfdf	75	pio2: gpio@fe612000 {
15969b45 SK	76	gpio-controller;
15969b45 SK	77	#gpio-cells = <1>;
bdda8b05 SK	78	interrupt-controller;
bdda8b05 SK	79	#interrupt-cells = <2>;
15969b45 SK	80	reg = <0x2000 0x100>;
	81	st,bank-name = "PIO2";
	82	};
dc62bfdf	83	pio3: gpio@fe613000 {
15969b45 SK	84	gpio-controller;
15969b45 SK	85	#gpio-cells = <1>;
bdda8b05 SK	86	interrupt-controller;
bdda8b05 SK	87	#interrupt-cells = <2>;
15969b45 SK	88	reg = <0x3000 0x100>;
	89	st,bank-name = "PIO3";
	90	};
dc62bfdf	91	pio4: gpio@fe614000 {
15969b45 SK	92	gpio-controller;
15969b45 SK	93	#gpio-cells = <1>;
bdda8b05 SK	94	interrupt-controller;
bdda8b05 SK	95	#interrupt-cells = <2>;
15969b45 SK	96	reg = <0x4000 0x100>;
	97	st,bank-name = "PIO4";
	98	};
dc62bfdf	99	pio40: gpio@fe615000 {
15969b45 SK	100	gpio-controller;
15969b45 SK	101	#gpio-cells = <1>;
bdda8b05 SK	102	interrupt-controller;
bdda8b05 SK	103	#interrupt-cells = <2>;
15969b45 SK	104	reg = <0x5000 0x100>;
	105	st,bank-name = "PIO40";
	106	st,retime-pin-mask = <0x7f>;
	107	};
	108
e063735f SK	109	rc{
	110	pinctrl_ir: ir0 {
	111	st,pins {
dc62bfdf	112	ir = <&pio4 0 ALT2 IN>;
e063735f SK	113	};
	114	};
	115	};
15969b45 SK	116	sbc_serial1 {
	117	pinctrl_sbc_serial1: sbc_serial1 {
	118	st,pins {
dc62bfdf LJ	119	tx = <&pio2 6 ALT3 OUT>;
dc62bfdf LJ	120	rx = <&pio2 7 ALT3 IN>;
15969b45 SK	121	};
	122	};
	123	};
f53e99a9	124
948d8ffb GF	125	keyscan {
	126	pinctrl_keyscan: keyscan {
	127	st,pins {
dc62bfdf LJ	128	keyin0 = <&pio0 2 ALT2 IN>;
	129	keyin1 = <&pio0 3 ALT2 IN>;
	130	keyin2 = <&pio0 4 ALT2 IN>;
	131	keyin3 = <&pio2 6 ALT2 IN>;
	132
	133	keyout0 = <&pio1 6 ALT2 OUT>;
	134	keyout1 = <&pio1 7 ALT2 OUT>;
	135	keyout2 = <&pio0 6 ALT2 OUT>;
	136	keyout3 = <&pio2 7 ALT2 OUT>;
948d8ffb GF	137	};
	138	};
	139	};
	140
f53e99a9 MC	141	sbc_i2c0 {
	142	pinctrl_sbc_i2c0_default: sbc_i2c0-default {
	143	st,pins {
dc62bfdf LJ	144	sda = <&pio4 6 ALT1 BIDIR>;
dc62bfdf LJ	145	scl = <&pio4 5 ALT1 BIDIR>;
f53e99a9 MC	146	};
	147	};
	148	};
	149
	150	sbc_i2c1 {
	151	pinctrl_sbc_i2c1_default: sbc_i2c1-default {
	152	st,pins {
dc62bfdf LJ	153	sda = <&pio3 2 ALT2 BIDIR>;
dc62bfdf LJ	154	scl = <&pio3 1 ALT2 BIDIR>;
f53e99a9 MC	155	};
	156	};
	157	};
d25ea584 SK	158
	159	gmac1 {
	160	pinctrl_mii1: mii1 {
	161	st,pins {
dc62bfdf LJ	162	txd0 = <&pio0 0 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
	163	txd1 = <&pio0 1 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
	164	txd2 = <&pio0 2 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
	165	txd3 = <&pio0 3 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
	166	txer = <&pio0 4 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
	167	txen = <&pio0 5 ALT1 OUT SE_NICLK_IO 0 CLK_A>;
	168	txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
	169	col = <&pio0 7 ALT1 IN BYPASS 1000>;
	170
	171	mdio = <&pio1 0 ALT1 OUT BYPASS 1500>;
	172	mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
	173	crs = <&pio1 2 ALT1 IN BYPASS 1000>;
	174	mdint = <&pio1 3 ALT1 IN BYPASS 0>;
	175	rxd0 = <&pio1 4 ALT1 IN SE_NICLK_IO 0 CLK_A>;
	176	rxd1 = <&pio1 5 ALT1 IN SE_NICLK_IO 0 CLK_A>;
	177	rxd2 = <&pio1 6 ALT1 IN SE_NICLK_IO 0 CLK_A>;
	178	rxd3 = <&pio1 7 ALT1 IN SE_NICLK_IO 0 CLK_A>;
	179
	180	rxdv = <&pio2 0 ALT1 IN SE_NICLK_IO 0 CLK_A>;
	181	rx_er = <&pio2 1 ALT1 IN SE_NICLK_IO 0 CLK_A>;
	182	rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
	183	phyclk = <&pio2 3 ALT1 OUT NICLK 0 CLK_A>;
d25ea584 SK	184	};
	185	};
	186	pinctrl_rgmii1: rgmii1-0 {
	187	st,pins {
dc62bfdf LJ	188	txd0 = <&pio0 0 ALT1 OUT DE_IO 500 CLK_A>;
	189	txd1 = <&pio0 1 ALT1 OUT DE_IO 500 CLK_A>;
	190	txd2 = <&pio0 2 ALT1 OUT DE_IO 500 CLK_A>;
	191	txd3 = <&pio0 3 ALT1 OUT DE_IO 500 CLK_A>;
	192	txen = <&pio0 5 ALT1 OUT DE_IO 0 CLK_A>;
	193	txclk = <&pio0 6 ALT1 IN NICLK 0 CLK_A>;
	194
	195	mdio = <&pio1 0 ALT1 OUT BYPASS 0>;
	196	mdc = <&pio1 1 ALT1 OUT NICLK 0 CLK_A>;
	197	rxd0 = <&pio1 4 ALT1 IN DE_IO 500 CLK_A>;
	198	rxd1 = <&pio1 5 ALT1 IN DE_IO 500 CLK_A>;
	199	rxd2 = <&pio1 6 ALT1 IN DE_IO 500 CLK_A>;
	200	rxd3 = <&pio1 7 ALT1 IN DE_IO 500 CLK_A>;
	201
	202	rxdv = <&pio2 0 ALT1 IN DE_IO 500 CLK_A>;
	203	rxclk = <&pio2 2 ALT1 IN NICLK 0 CLK_A>;
	204	phyclk = <&pio2 3 ALT4 OUT NICLK 0 CLK_B>;
	205
	206	clk125= <&pio3 7 ALT4 IN NICLK 0 CLK_A>;
d25ea584 SK	207	};
	208	};
	209	};
15969b45 SK	210	};
	211
	212	pin-controller-front {
	213	#address-cells = <1>;
	214	#size-cells = <1>;
	215	compatible = "st,stih416-front-pinctrl";
	216	st,syscfg = <&syscfg_front>;
bdda8b05 SK	217	reg = <0xfee0f080 0x4>;
	218	reg-names = "irqmux";
	219	interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
ae107d06	220	interrupt-names = "irqmux";
15969b45 SK	221	ranges = <0 0xfee00000 0x10000>;
15969b45 SK	222
dc62bfdf	223	pio5: gpio@fee00000 {
15969b45 SK	224	gpio-controller;
15969b45 SK	225	#gpio-cells = <1>;
bdda8b05 SK	226	interrupt-controller;
bdda8b05 SK	227	#interrupt-cells = <2>;
15969b45 SK	228	reg = <0 0x100>;
	229	st,bank-name = "PIO5";
	230	};
dc62bfdf	231	pio6: gpio@fee01000 {
15969b45 SK	232	gpio-controller;
15969b45 SK	233	#gpio-cells = <1>;
bdda8b05 SK	234	interrupt-controller;
bdda8b05 SK	235	#interrupt-cells = <2>;
15969b45 SK	236	reg = <0x1000 0x100>;
	237	st,bank-name = "PIO6";
	238	};
dc62bfdf	239	pio7: gpio@fee02000 {
15969b45 SK	240	gpio-controller;
15969b45 SK	241	#gpio-cells = <1>;
bdda8b05 SK	242	interrupt-controller;
bdda8b05 SK	243	#interrupt-cells = <2>;
15969b45 SK	244	reg = <0x2000 0x100>;
	245	st,bank-name = "PIO7";
	246	};
dc62bfdf	247	pio8: gpio@fee03000 {
15969b45 SK	248	gpio-controller;
15969b45 SK	249	#gpio-cells = <1>;
bdda8b05 SK	250	interrupt-controller;
bdda8b05 SK	251	#interrupt-cells = <2>;
15969b45 SK	252	reg = <0x3000 0x100>;
	253	st,bank-name = "PIO8";
	254	};
dc62bfdf	255	pio9: gpio@fee04000 {
15969b45 SK	256	gpio-controller;
15969b45 SK	257	#gpio-cells = <1>;
bdda8b05 SK	258	interrupt-controller;
bdda8b05 SK	259	#interrupt-cells = <2>;
15969b45 SK	260	reg = <0x4000 0x100>;
	261	st,bank-name = "PIO9";
	262	};
dc62bfdf	263	pio10: gpio@fee05000 {
15969b45 SK	264	gpio-controller;
15969b45 SK	265	#gpio-cells = <1>;
bdda8b05 SK	266	interrupt-controller;
bdda8b05 SK	267	#interrupt-cells = <2>;
15969b45 SK	268	reg = <0x5000 0x100>;
	269	st,bank-name = "PIO10";
	270	};
dc62bfdf	271	pio11: gpio@fee06000 {
15969b45 SK	272	gpio-controller;
15969b45 SK	273	#gpio-cells = <1>;
bdda8b05 SK	274	interrupt-controller;
bdda8b05 SK	275	#interrupt-cells = <2>;
15969b45 SK	276	reg = <0x6000 0x100>;
	277	st,bank-name = "PIO11";
	278	};
dc62bfdf	279	pio12: gpio@fee07000 {
15969b45 SK	280	gpio-controller;
15969b45 SK	281	#gpio-cells = <1>;
bdda8b05 SK	282	interrupt-controller;
bdda8b05 SK	283	#interrupt-cells = <2>;
15969b45 SK	284	reg = <0x7000 0x100>;
	285	st,bank-name = "PIO12";
	286	};
dc62bfdf	287	pio30: gpio@fee08000 {
15969b45 SK	288	gpio-controller;
15969b45 SK	289	#gpio-cells = <1>;
bdda8b05 SK	290	interrupt-controller;
bdda8b05 SK	291	#interrupt-cells = <2>;
15969b45 SK	292	reg = <0x8000 0x100>;
	293	st,bank-name = "PIO30";
	294	};
dc62bfdf	295	pio31: gpio@fee09000 {
15969b45 SK	296	gpio-controller;
15969b45 SK	297	#gpio-cells = <1>;
bdda8b05 SK	298	interrupt-controller;
bdda8b05 SK	299	#interrupt-cells = <2>;
15969b45 SK	300	reg = <0x9000 0x100>;
	301	st,bank-name = "PIO31";
	302	};
334ab91d SK	303
	304	serial2-oe {
	305	pinctrl_serial2_oe: serial2-1 {
	306	st,pins {
dc62bfdf	307	output-enable = <&pio11 3 ALT2 OUT>;
334ab91d SK	308	};
	309	};
	310	};
	311
f53e99a9 MC	312	i2c0 {
	313	pinctrl_i2c0_default: i2c0-default {
	314	st,pins {
dc62bfdf LJ	315	sda = <&pio9 3 ALT1 BIDIR>;
dc62bfdf LJ	316	scl = <&pio9 2 ALT1 BIDIR>;
f53e99a9 MC	317	};
	318	};
	319	};
	320
	321	i2c1 {
	322	pinctrl_i2c1_default: i2c1-default {
	323	st,pins {
dc62bfdf LJ	324	sda = <&pio12 1 ALT1 BIDIR>;
dc62bfdf LJ	325	scl = <&pio12 0 ALT1 BIDIR>;
f53e99a9 MC	326	};
	327	};
	328	};
77f8d9b7 LJ	329
	330	fsm {
	331	pinctrl_fsm: fsm {
	332	st,pins {
dc62bfdf LJ	333	spi-fsm-clk = <&pio12 2 ALT1 OUT>;
	334	spi-fsm-cs = <&pio12 3 ALT1 OUT>;
	335	spi-fsm-mosi = <&pio12 4 ALT1 OUT>;
	336	spi-fsm-miso = <&pio12 5 ALT1 IN>;
	337	spi-fsm-hol = <&pio12 6 ALT1 OUT>;
	338	spi-fsm-wp = <&pio12 7 ALT1 OUT>;
77f8d9b7 LJ	339	};
	340	};
	341	};
15969b45 SK	342	};
	343
	344	pin-controller-rear {
	345	#address-cells = <1>;
	346	#size-cells = <1>;
	347	compatible = "st,stih416-rear-pinctrl";
	348	st,syscfg = <&syscfg_rear>;
bdda8b05 SK	349	reg = <0xfe82f080 0x4>;
	350	reg-names = "irqmux";
	351	interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
ae107d06	352	interrupt-names = "irqmux";
15969b45 SK	353	ranges = <0 0xfe820000 0x6000>;
15969b45 SK	354
dc62bfdf	355	pio13: gpio@fe820000 {
15969b45 SK	356	gpio-controller;
15969b45 SK	357	#gpio-cells = <1>;
bdda8b05 SK	358	interrupt-controller;
bdda8b05 SK	359	#interrupt-cells = <2>;
15969b45 SK	360	reg = <0 0x100>;
	361	st,bank-name = "PIO13";
	362	};
dc62bfdf	363	pio14: gpio@fe821000 {
15969b45 SK	364	gpio-controller;
15969b45 SK	365	#gpio-cells = <1>;
bdda8b05 SK	366	interrupt-controller;
bdda8b05 SK	367	#interrupt-cells = <2>;
15969b45 SK	368	reg = <0x1000 0x100>;
	369	st,bank-name = "PIO14";
	370	};
dc62bfdf	371	pio15: gpio@fe822000 {
15969b45 SK	372	gpio-controller;
15969b45 SK	373	#gpio-cells = <1>;
bdda8b05 SK	374	interrupt-controller;
bdda8b05 SK	375	#interrupt-cells = <2>;
15969b45 SK	376	reg = <0x2000 0x100>;
	377	st,bank-name = "PIO15";
	378	};
dc62bfdf	379	pio16: gpio@fe823000 {
15969b45 SK	380	gpio-controller;
15969b45 SK	381	#gpio-cells = <1>;
bdda8b05 SK	382	interrupt-controller;
bdda8b05 SK	383	#interrupt-cells = <2>;
15969b45 SK	384	reg = <0x3000 0x100>;
	385	st,bank-name = "PIO16";
	386	};
dc62bfdf	387	pio17: gpio@fe824000 {
15969b45 SK	388	gpio-controller;
15969b45 SK	389	#gpio-cells = <1>;
bdda8b05 SK	390	interrupt-controller;
bdda8b05 SK	391	#interrupt-cells = <2>;
15969b45 SK	392	reg = <0x4000 0x100>;
	393	st,bank-name = "PIO17";
	394	};
dc62bfdf	395	pio18: gpio@fe825000 {
15969b45 SK	396	gpio-controller;
15969b45 SK	397	#gpio-cells = <1>;
bdda8b05 SK	398	interrupt-controller;
bdda8b05 SK	399	#interrupt-cells = <2>;
15969b45 SK	400	reg = <0x5000 0x100>;
	401	st,bank-name = "PIO18";
	402	st,retime-pin-mask = <0xf>;
	403	};
	404
	405	serial2 {
	406	pinctrl_serial2: serial2-0 {
	407	st,pins {
dc62bfdf LJ	408	tx = <&pio17 4 ALT2 OUT>;
dc62bfdf LJ	409	rx = <&pio17 5 ALT2 IN>;
15969b45 SK	410	};
	411	};
	412	};
d25ea584 SK	413
	414	gmac0 {
	415	pinctrl_mii0: mii0 {
	416	st,pins {
dc62bfdf LJ	417	mdint = <&pio13 6 ALT2 IN BYPASS 0>;
	418	txen = <&pio13 7 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
	419	txd0 = <&pio14 0 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
	420	txd1 = <&pio14 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
	421	txd2 = <&pio14 2 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
	422	txd3 = <&pio14 3 ALT2 OUT SE_NICLK_IO 0 CLK_B>;
	423
	424	txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
	425	txer = <&pio15 1 ALT2 OUT SE_NICLK_IO 0 CLK_A>;
	426	crs = <&pio15 2 ALT2 IN BYPASS 1000>;
	427	col = <&pio15 3 ALT2 IN BYPASS 1000>;
	428	mdio= <&pio15 4 ALT2 OUT BYPASS 1500>;
	429	mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
	430
	431	rxd0 = <&pio16 0 ALT2 IN SE_NICLK_IO 0 CLK_A>;
	432	rxd1 = <&pio16 1 ALT2 IN SE_NICLK_IO 0 CLK_A>;
	433	rxd2 = <&pio16 2 ALT2 IN SE_NICLK_IO 0 CLK_A>;
	434	rxd3 = <&pio16 3 ALT2 IN SE_NICLK_IO 0 CLK_A>;
	435	rxdv = <&pio15 6 ALT2 IN SE_NICLK_IO 0 CLK_A>;
	436	rx_er = <&pio15 7 ALT2 IN SE_NICLK_IO 0 CLK_A>;
	437	rxclk = <&pio17 0 ALT2 IN NICLK 0 CLK_A>;
	438	phyclk = <&pio13 5 ALT2 OUT NICLK 0 CLK_B>;
d25ea584 SK	439	};
	440	};
	441
	442	pinctrl_gmii0: gmii0 {
	443	st,pins {
	444	};
	445	};
	446	pinctrl_rgmii0: rgmii0 {
	447	st,pins {
dc62bfdf LJ	448	phyclk = <&pio13 5 ALT4 OUT NICLK 0 CLK_B>;
	449	txen = <&pio13 7 ALT2 OUT DE_IO 0 CLK_A>;
	450	txd0 = <&pio14 0 ALT2 OUT DE_IO 500 CLK_A>;
	451	txd1 = <&pio14 1 ALT2 OUT DE_IO 500 CLK_A>;
	452	txd2 = <&pio14 2 ALT2 OUT DE_IO 500 CLK_B>;
	453	txd3 = <&pio14 3 ALT2 OUT DE_IO 500 CLK_B>;
	454	txclk = <&pio15 0 ALT2 IN NICLK 0 CLK_A>;
	455
	456	mdio = <&pio15 4 ALT2 OUT BYPASS 0>;
	457	mdc = <&pio15 5 ALT2 OUT NICLK 0 CLK_B>;
	458
	459	rxdv = <&pio15 6 ALT2 IN DE_IO 500 CLK_A>;
	460	rxd0 =<&pio16 0 ALT2 IN DE_IO 500 CLK_A>;
	461	rxd1 =<&pio16 1 ALT2 IN DE_IO 500 CLK_A>;
	462	rxd2 =<&pio16 2 ALT2 IN DE_IO 500 CLK_A>;
	463	rxd3 =<&pio16 3 ALT2 IN DE_IO 500 CLK_A>;
	464	rxclk =<&pio17 0 ALT2 IN NICLK 0 CLK_A>;
	465
	466	clk125=<&pio17 6 ALT1 IN NICLK 0 CLK_A>;
d25ea584 SK	467	};
	468	};
	469	};
15969b45 SK	470	};
	471
	472	pin-controller-fvdp-fe {
	473	#address-cells = <1>;
	474	#size-cells = <1>;
	475	compatible = "st,stih416-fvdp-fe-pinctrl";
	476	st,syscfg = <&syscfg_fvdp_fe>;
bdda8b05 SK	477	reg = <0xfd6bf080 0x4>;
	478	reg-names = "irqmux";
	479	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
ae107d06	480	interrupt-names = "irqmux";
15969b45 SK	481	ranges = <0 0xfd6b0000 0x3000>;
15969b45 SK	482
dc62bfdf	483	pio100: gpio@fd6b0000 {
15969b45 SK	484	gpio-controller;
15969b45 SK	485	#gpio-cells = <1>;
bdda8b05 SK	486	interrupt-controller;
bdda8b05 SK	487	#interrupt-cells = <2>;
15969b45 SK	488	reg = <0 0x100>;
	489	st,bank-name = "PIO100";
	490	};
dc62bfdf	491	pio101: gpio@fd6b1000 {
15969b45 SK	492	gpio-controller;
15969b45 SK	493	#gpio-cells = <1>;
bdda8b05 SK	494	interrupt-controller;
bdda8b05 SK	495	#interrupt-cells = <2>;
15969b45 SK	496	reg = <0x1000 0x100>;
	497	st,bank-name = "PIO101";
	498	};
dc62bfdf	499	pio102: gpio@fd6b2000 {
15969b45 SK	500	gpio-controller;
15969b45 SK	501	#gpio-cells = <1>;
bdda8b05 SK	502	interrupt-controller;
bdda8b05 SK	503	#interrupt-cells = <2>;
15969b45 SK	504	reg = <0x2000 0x100>;
	505	st,bank-name = "PIO102";
	506	};
	507	};
	508
	509	pin-controller-fvdp-lite {
	510	#address-cells = <1>;
	511	#size-cells = <1>;
	512	compatible = "st,stih416-fvdp-lite-pinctrl";
	513	st,syscfg = <&syscfg_fvdp_lite>;
bdda8b05 SK	514	reg = <0xfd33f080 0x4>;
	515	reg-names = "irqmux";
	516	interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
ae107d06	517	interrupt-names = "irqmux";
15969b45 SK	518	ranges = <0 0xfd330000 0x5000>;
15969b45 SK	519
dc62bfdf	520	pio103: gpio@fd330000 {
15969b45 SK	521	gpio-controller;
15969b45 SK	522	#gpio-cells = <1>;
bdda8b05 SK	523	interrupt-controller;
bdda8b05 SK	524	#interrupt-cells = <2>;
15969b45 SK	525	reg = <0 0x100>;
	526	st,bank-name = "PIO103";
	527	};
dc62bfdf	528	pio104: gpio@fd331000 {
15969b45 SK	529	gpio-controller;
15969b45 SK	530	#gpio-cells = <1>;
bdda8b05 SK	531	interrupt-controller;
bdda8b05 SK	532	#interrupt-cells = <2>;
15969b45 SK	533	reg = <0x1000 0x100>;
	534	st,bank-name = "PIO104";
	535	};
dc62bfdf	536	pio105: gpio@fd332000 {
15969b45 SK	537	gpio-controller;
15969b45 SK	538	#gpio-cells = <1>;
bdda8b05 SK	539	interrupt-controller;
bdda8b05 SK	540	#interrupt-cells = <2>;
15969b45 SK	541	reg = <0x2000 0x100>;
	542	st,bank-name = "PIO105";
	543	};
dc62bfdf	544	pio106: gpio@fd333000 {
15969b45 SK	545	gpio-controller;
15969b45 SK	546	#gpio-cells = <1>;
bdda8b05 SK	547	interrupt-controller;
bdda8b05 SK	548	#interrupt-cells = <2>;
15969b45 SK	549	reg = <0x3000 0x100>;
	550	st,bank-name = "PIO106";
	551	};
	552
dc62bfdf	553	pio107: gpio@fd334000 {
15969b45 SK	554	gpio-controller;
15969b45 SK	555	#gpio-cells = <1>;
bdda8b05 SK	556	interrupt-controller;
bdda8b05 SK	557	#interrupt-cells = <2>;
15969b45 SK	558	reg = <0x4000 0x100>;
	559	st,bank-name = "PIO107";
	560	st,retime-pin-mask = <0xf>;
	561	};
	562	};
	563	};
	564	};