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338a6aaa MC |
1 | /* |
2 | * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com> | |
3 | * | |
4 | * This file is dual-licensed: you can use it either under the terms | |
5 | * of the GPL or the X11 license, at your option. Note that this dual | |
6 | * licensing only applies to this file, and not this project as a | |
7 | * whole. | |
8 | * | |
9 | * a) This file is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of the | |
12 | * License, or (at your option) any later version. | |
13 | * | |
14 | * This file is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public | |
20 | * License along with this file; if not, write to the Free | |
21 | * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, | |
22 | * MA 02110-1301 USA | |
23 | * | |
24 | * Or, alternatively, | |
25 | * | |
26 | * b) Permission is hereby granted, free of charge, to any person | |
27 | * obtaining a copy of this software and associated documentation | |
28 | * files (the "Software"), to deal in the Software without | |
29 | * restriction, including without limitation the rights to use, | |
30 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
31 | * sell copies of the Software, and to permit persons to whom the | |
32 | * Software is furnished to do so, subject to the following | |
33 | * conditions: | |
34 | * | |
35 | * The above copyright notice and this permission notice shall be | |
36 | * included in all copies or substantial portions of the Software. | |
37 | * | |
38 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
39 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
40 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
41 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
42 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
43 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
44 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
45 | * OTHER DEALINGS IN THE SOFTWARE. | |
46 | */ | |
47 | ||
48 | #include "armv7-m.dtsi" | |
2dbd0593 | 49 | #include <dt-bindings/pinctrl/stm32f429-pinfunc.h> |
338a6aaa MC |
50 | |
51 | / { | |
52 | clocks { | |
9dc24a2d | 53 | clk_hse: clk-hse { |
338a6aaa MC |
54 | #clock-cells = <0>; |
55 | compatible = "fixed-clock"; | |
9dc24a2d | 56 | clock-frequency = <0>; |
338a6aaa MC |
57 | }; |
58 | }; | |
59 | ||
60 | soc { | |
b2aa7f77 MC |
61 | dma-ranges = <0xc0000000 0x0 0x10000000>; |
62 | ||
338a6aaa MC |
63 | timer2: timer@40000000 { |
64 | compatible = "st,stm32-timer"; | |
65 | reg = <0x40000000 0x400>; | |
66 | interrupts = <28>; | |
9dc24a2d | 67 | clocks = <&rcc 0 128>; |
338a6aaa MC |
68 | status = "disabled"; |
69 | }; | |
70 | ||
71 | timer3: timer@40000400 { | |
72 | compatible = "st,stm32-timer"; | |
73 | reg = <0x40000400 0x400>; | |
74 | interrupts = <29>; | |
9dc24a2d | 75 | clocks = <&rcc 0 129>; |
338a6aaa MC |
76 | status = "disabled"; |
77 | }; | |
78 | ||
79 | timer4: timer@40000800 { | |
80 | compatible = "st,stm32-timer"; | |
81 | reg = <0x40000800 0x400>; | |
82 | interrupts = <30>; | |
9dc24a2d | 83 | clocks = <&rcc 0 130>; |
338a6aaa MC |
84 | status = "disabled"; |
85 | }; | |
86 | ||
87 | timer5: timer@40000c00 { | |
88 | compatible = "st,stm32-timer"; | |
89 | reg = <0x40000c00 0x400>; | |
90 | interrupts = <50>; | |
9dc24a2d | 91 | clocks = <&rcc 0 131>; |
338a6aaa MC |
92 | }; |
93 | ||
94 | timer6: timer@40001000 { | |
95 | compatible = "st,stm32-timer"; | |
96 | reg = <0x40001000 0x400>; | |
97 | interrupts = <54>; | |
9dc24a2d | 98 | clocks = <&rcc 0 132>; |
338a6aaa MC |
99 | status = "disabled"; |
100 | }; | |
101 | ||
102 | timer7: timer@40001400 { | |
103 | compatible = "st,stm32-timer"; | |
104 | reg = <0x40001400 0x400>; | |
105 | interrupts = <55>; | |
9dc24a2d | 106 | clocks = <&rcc 0 133>; |
338a6aaa MC |
107 | status = "disabled"; |
108 | }; | |
109 | ||
110 | usart2: serial@40004400 { | |
111 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
112 | reg = <0x40004400 0x400>; | |
113 | interrupts = <38>; | |
9dc24a2d | 114 | clocks = <&rcc 0 145>; |
338a6aaa MC |
115 | status = "disabled"; |
116 | }; | |
117 | ||
118 | usart3: serial@40004800 { | |
119 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
120 | reg = <0x40004800 0x400>; | |
121 | interrupts = <39>; | |
9dc24a2d | 122 | clocks = <&rcc 0 146>; |
338a6aaa MC |
123 | status = "disabled"; |
124 | }; | |
125 | ||
126 | usart4: serial@40004c00 { | |
127 | compatible = "st,stm32-uart"; | |
128 | reg = <0x40004c00 0x400>; | |
129 | interrupts = <52>; | |
9dc24a2d | 130 | clocks = <&rcc 0 147>; |
338a6aaa MC |
131 | status = "disabled"; |
132 | }; | |
133 | ||
134 | usart5: serial@40005000 { | |
135 | compatible = "st,stm32-uart"; | |
136 | reg = <0x40005000 0x400>; | |
137 | interrupts = <53>; | |
9dc24a2d | 138 | clocks = <&rcc 0 148>; |
338a6aaa MC |
139 | status = "disabled"; |
140 | }; | |
141 | ||
142 | usart7: serial@40007800 { | |
143 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
144 | reg = <0x40007800 0x400>; | |
145 | interrupts = <82>; | |
9dc24a2d | 146 | clocks = <&rcc 0 158>; |
338a6aaa MC |
147 | status = "disabled"; |
148 | }; | |
149 | ||
150 | usart8: serial@40007c00 { | |
151 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
152 | reg = <0x40007c00 0x400>; | |
153 | interrupts = <83>; | |
9dc24a2d | 154 | clocks = <&rcc 0 159>; |
338a6aaa MC |
155 | status = "disabled"; |
156 | }; | |
157 | ||
158 | usart1: serial@40011000 { | |
159 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
160 | reg = <0x40011000 0x400>; | |
161 | interrupts = <37>; | |
9dc24a2d | 162 | clocks = <&rcc 0 164>; |
338a6aaa MC |
163 | status = "disabled"; |
164 | }; | |
165 | ||
166 | usart6: serial@40011400 { | |
167 | compatible = "st,stm32-usart", "st,stm32-uart"; | |
168 | reg = <0x40011400 0x400>; | |
169 | interrupts = <71>; | |
9dc24a2d | 170 | clocks = <&rcc 0 165>; |
338a6aaa MC |
171 | status = "disabled"; |
172 | }; | |
9dc24a2d | 173 | |
e78b6555 AT |
174 | syscfg: system-config@40013800 { |
175 | compatible = "syscon"; | |
176 | reg = <0x40013800 0x400>; | |
177 | }; | |
178 | ||
2dbd0593 MC |
179 | pin-controller { |
180 | #address-cells = <1>; | |
181 | #size-cells = <1>; | |
182 | compatible = "st,stm32f429-pinctrl"; | |
183 | ranges = <0 0x40020000 0x3000>; | |
184 | pins-are-numbered; | |
185 | ||
186 | gpioa: gpio@40020000 { | |
187 | gpio-controller; | |
188 | #gpio-cells = <2>; | |
189 | reg = <0x0 0x400>; | |
a985b66a | 190 | clocks = <&rcc 0 0>; |
2dbd0593 MC |
191 | st,bank-name = "GPIOA"; |
192 | }; | |
193 | ||
194 | gpiob: gpio@40020400 { | |
195 | gpio-controller; | |
196 | #gpio-cells = <2>; | |
197 | reg = <0x400 0x400>; | |
a985b66a | 198 | clocks = <&rcc 0 1>; |
2dbd0593 MC |
199 | st,bank-name = "GPIOB"; |
200 | }; | |
201 | ||
202 | gpioc: gpio@40020800 { | |
203 | gpio-controller; | |
204 | #gpio-cells = <2>; | |
205 | reg = <0x800 0x400>; | |
a985b66a | 206 | clocks = <&rcc 0 2>; |
2dbd0593 MC |
207 | st,bank-name = "GPIOC"; |
208 | }; | |
209 | ||
210 | gpiod: gpio@40020c00 { | |
211 | gpio-controller; | |
212 | #gpio-cells = <2>; | |
213 | reg = <0xc00 0x400>; | |
a985b66a | 214 | clocks = <&rcc 0 3>; |
2dbd0593 MC |
215 | st,bank-name = "GPIOD"; |
216 | }; | |
217 | ||
218 | gpioe: gpio@40021000 { | |
219 | gpio-controller; | |
220 | #gpio-cells = <2>; | |
221 | reg = <0x1000 0x400>; | |
a985b66a | 222 | clocks = <&rcc 0 4>; |
2dbd0593 MC |
223 | st,bank-name = "GPIOE"; |
224 | }; | |
225 | ||
226 | gpiof: gpio@40021400 { | |
227 | gpio-controller; | |
228 | #gpio-cells = <2>; | |
229 | reg = <0x1400 0x400>; | |
a985b66a | 230 | clocks = <&rcc 0 5>; |
2dbd0593 MC |
231 | st,bank-name = "GPIOF"; |
232 | }; | |
233 | ||
234 | gpiog: gpio@40021800 { | |
235 | gpio-controller; | |
236 | #gpio-cells = <2>; | |
237 | reg = <0x1800 0x400>; | |
a985b66a | 238 | clocks = <&rcc 0 6>; |
2dbd0593 MC |
239 | st,bank-name = "GPIOG"; |
240 | }; | |
241 | ||
242 | gpioh: gpio@40021c00 { | |
243 | gpio-controller; | |
244 | #gpio-cells = <2>; | |
245 | reg = <0x1c00 0x400>; | |
a985b66a | 246 | clocks = <&rcc 0 7>; |
2dbd0593 MC |
247 | st,bank-name = "GPIOH"; |
248 | }; | |
249 | ||
250 | gpioi: gpio@40022000 { | |
251 | gpio-controller; | |
252 | #gpio-cells = <2>; | |
253 | reg = <0x2000 0x400>; | |
a985b66a | 254 | clocks = <&rcc 0 8>; |
2dbd0593 MC |
255 | st,bank-name = "GPIOI"; |
256 | }; | |
257 | ||
258 | gpioj: gpio@40022400 { | |
259 | gpio-controller; | |
260 | #gpio-cells = <2>; | |
261 | reg = <0x2400 0x400>; | |
a985b66a | 262 | clocks = <&rcc 0 9>; |
2dbd0593 MC |
263 | st,bank-name = "GPIOJ"; |
264 | }; | |
265 | ||
266 | gpiok: gpio@40022800 { | |
267 | gpio-controller; | |
268 | #gpio-cells = <2>; | |
269 | reg = <0x2800 0x400>; | |
a985b66a | 270 | clocks = <&rcc 0 10>; |
2dbd0593 MC |
271 | st,bank-name = "GPIOK"; |
272 | }; | |
521df6f5 MC |
273 | |
274 | usart1_pins_a: usart1@0 { | |
275 | pins1 { | |
276 | pinmux = <STM32F429_PA9_FUNC_USART1_TX>; | |
277 | bias-disable; | |
278 | drive-push-pull; | |
279 | slew-rate = <0>; | |
280 | }; | |
281 | pins2 { | |
282 | pinmux = <STM32F429_PA10_FUNC_USART1_RX>; | |
283 | bias-disable; | |
284 | }; | |
285 | }; | |
c8cc1b72 MC |
286 | |
287 | usbotg_hs_pins_a: usbotg_hs@0 { | |
288 | pins { | |
289 | pinmux = <STM32F429_PH4_FUNC_OTG_HS_ULPI_NXT>, | |
290 | <STM32F429_PI11_FUNC_OTG_HS_ULPI_DIR>, | |
291 | <STM32F429_PC0_FUNC_OTG_HS_ULPI_STP>, | |
292 | <STM32F429_PA5_FUNC_OTG_HS_ULPI_CK>, | |
293 | <STM32F429_PA3_FUNC_OTG_HS_ULPI_D0>, | |
294 | <STM32F429_PB0_FUNC_OTG_HS_ULPI_D1>, | |
295 | <STM32F429_PB1_FUNC_OTG_HS_ULPI_D2>, | |
296 | <STM32F429_PB10_FUNC_OTG_HS_ULPI_D3>, | |
297 | <STM32F429_PB11_FUNC_OTG_HS_ULPI_D4>, | |
298 | <STM32F429_PB12_FUNC_OTG_HS_ULPI_D5>, | |
299 | <STM32F429_PB13_FUNC_OTG_HS_ULPI_D6>, | |
300 | <STM32F429_PB5_FUNC_OTG_HS_ULPI_D7>; | |
301 | bias-disable; | |
302 | drive-push-pull; | |
303 | slew-rate = <2>; | |
304 | }; | |
305 | }; | |
9ee33d66 AT |
306 | |
307 | ethernet0_mii: mii@0 { | |
308 | pins { | |
309 | pinmux = <STM32F429_PG13_FUNC_ETH_MII_TXD0_ETH_RMII_TXD0>, | |
310 | <STM32F429_PG14_FUNC_ETH_MII_TXD1_ETH_RMII_TXD1>, | |
311 | <STM32F429_PC2_FUNC_ETH_MII_TXD2>, | |
312 | <STM32F429_PB8_FUNC_ETH_MII_TXD3>, | |
313 | <STM32F429_PC3_FUNC_ETH_MII_TX_CLK>, | |
314 | <STM32F429_PG11_FUNC_ETH_MII_TX_EN_ETH_RMII_TX_EN>, | |
315 | <STM32F429_PA2_FUNC_ETH_MDIO>, | |
316 | <STM32F429_PC1_FUNC_ETH_MDC>, | |
317 | <STM32F429_PA1_FUNC_ETH_MII_RX_CLK_ETH_RMII_REF_CLK>, | |
318 | <STM32F429_PA7_FUNC_ETH_MII_RX_DV_ETH_RMII_CRS_DV>, | |
319 | <STM32F429_PC4_FUNC_ETH_MII_RXD0_ETH_RMII_RXD0>, | |
320 | <STM32F429_PC5_FUNC_ETH_MII_RXD1_ETH_RMII_RXD1>, | |
321 | <STM32F429_PH6_FUNC_ETH_MII_RXD2>, | |
322 | <STM32F429_PH7_FUNC_ETH_MII_RXD3>; | |
323 | slew-rate = <2>; | |
324 | }; | |
325 | }; | |
2dbd0593 MC |
326 | }; |
327 | ||
9dc24a2d | 328 | rcc: rcc@40023810 { |
9af80712 | 329 | #reset-cells = <1>; |
9dc24a2d DT |
330 | #clock-cells = <2>; |
331 | compatible = "st,stm32f42xx-rcc", "st,stm32-rcc"; | |
332 | reg = <0x40023800 0x400>; | |
333 | clocks = <&clk_hse>; | |
334 | }; | |
b47c9fab | 335 | |
9ee9e281 CM |
336 | dma1: dma-controller@40026000 { |
337 | compatible = "st,stm32-dma"; | |
338 | reg = <0x40026000 0x400>; | |
339 | interrupts = <11>, | |
340 | <12>, | |
341 | <13>, | |
342 | <14>, | |
343 | <15>, | |
344 | <16>, | |
345 | <17>, | |
346 | <47>; | |
347 | clocks = <&rcc 0 21>; | |
348 | #dma-cells = <4>; | |
349 | }; | |
350 | ||
351 | dma2: dma-controller@40026400 { | |
352 | compatible = "st,stm32-dma"; | |
353 | reg = <0x40026400 0x400>; | |
354 | interrupts = <56>, | |
355 | <57>, | |
356 | <58>, | |
357 | <59>, | |
358 | <60>, | |
359 | <68>, | |
360 | <69>, | |
361 | <70>; | |
362 | clocks = <&rcc 0 22>; | |
363 | #dma-cells = <4>; | |
364 | st,mem2mem; | |
365 | }; | |
366 | ||
9ee33d66 AT |
367 | ethernet0: dwmac@40028000 { |
368 | compatible = "st,stm32-dwmac", "snps,dwmac-3.50a"; | |
369 | reg = <0x40028000 0x8000>; | |
370 | reg-names = "stmmaceth"; | |
371 | interrupts = <61>, <62>; | |
372 | interrupt-names = "macirq", "eth_wake_irq"; | |
373 | clock-names = "stmmaceth", "tx-clk", "rx-clk"; | |
374 | clocks = <&rcc 0 25>, <&rcc 0 26>, <&rcc 0 27>; | |
375 | st,syscon = <&syscfg 0x4>; | |
376 | snps,pbl = <8>; | |
377 | snps,mixed-burst; | |
378 | dma-ranges; | |
379 | status = "disabled"; | |
380 | }; | |
381 | ||
c8cc1b72 MC |
382 | usbotg_hs: usb@40040000 { |
383 | compatible = "snps,dwc2"; | |
384 | dma-ranges; | |
385 | reg = <0x40040000 0x40000>; | |
386 | interrupts = <77>; | |
387 | clocks = <&rcc 0 29>; | |
388 | clock-names = "otg"; | |
389 | status = "disabled"; | |
390 | }; | |
391 | ||
b47c9fab DT |
392 | rng: rng@50060800 { |
393 | compatible = "st,stm32-rng"; | |
394 | reg = <0x50060800 0x400>; | |
395 | interrupts = <80>; | |
396 | clocks = <&rcc 0 38>; | |
397 | }; | |
338a6aaa MC |
398 | }; |
399 | }; | |
400 | ||
401 | &systick { | |
9dc24a2d | 402 | clocks = <&rcc 1 0>; |
338a6aaa MC |
403 | status = "okay"; |
404 | }; |