projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 7423d2d8 SR |
1 | /* |
| 2 | * Copyright 2012 Stefan Roese | |
| 3 | * Stefan Roese <sr@denx.de> | |
| 4 | * | |
| 5 | * The code contained herein is licensed under the GNU General Public | |
| 6 | * License. You may obtain a copy of the GNU General Public License | |
| 7 | * Version 2 or later at the following locations: | |
| 8 | * | |
| 9 | * http://www.opensource.org/licenses/gpl-license.html | |
| 10 | * http://www.gnu.org/copyleft/gpl.html | |
| 11 | */ | |
| 12 | ||
| 69144e3b | 13 | /include/ "skeleton.dtsi" |
| 7423d2d8 SR |
14 | |
| 15 | / { | |
| 69144e3b MR |
16 | interrupt-parent = <&intc>; |
| 17 | ||
| e751cce9 EL |
18 | aliases { |
| 19 | ethernet0 = &emac; | |
| 10b302a2 MR |
20 | serial0 = &uart0; |
| 21 | serial1 = &uart1; | |
| 143b13d6 MR |
22 | serial2 = &uart2; |
| 23 | serial3 = &uart3; | |
| 24 | serial4 = &uart4; | |
| 25 | serial5 = &uart5; | |
| 26 | serial6 = &uart6; | |
| 27 | serial7 = &uart7; | |
| e751cce9 EL |
28 | }; |
| 29 | ||
| 5790d4ee HG |
30 | chosen { |
| 31 | #address-cells = <1>; | |
| 32 | #size-cells = <1>; | |
| 33 | ranges; | |
| 34 | ||
| a9f8cda3 HG |
35 | framebuffer@0 { |
| 36 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
| 37 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | |
| 678e75d3 HG |
38 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
| 39 | <&ahb_gates 44>; | |
| 5790d4ee HG |
40 | status = "disabled"; |
| 41 | }; | |
| 42 | }; | |
| 43 | ||
| 69144e3b | 44 | cpus { |
| 8b2efa89 AB |
45 | #address-cells = <1>; |
| 46 | #size-cells = <0>; | |
| 69144e3b | 47 | cpu@0 { |
| 14c44aa5 | 48 | device_type = "cpu"; |
| 69144e3b | 49 | compatible = "arm,cortex-a8"; |
| 14c44aa5 | 50 | reg = <0x0>; |
| 69144e3b MR |
51 | }; |
| 52 | }; | |
| 53 | ||
| 7423d2d8 SR |
54 | memory { |
| 55 | reg = <0x40000000 0x80000000>; | |
| 56 | }; | |
| 874b4e45 | 57 | |
| 69144e3b MR |
58 | clocks { |
| 59 | #address-cells = <1>; | |
| 60 | #size-cells = <1>; | |
| 61 | ranges; | |
| 62 | ||
| 63 | /* | |
| 64 | * This is a dummy clock, to be used as placeholder on | |
| 65 | * other mux clocks when a specific parent clock is not | |
| 66 | * yet implemented. It should be dropped when the driver | |
| 67 | * is complete. | |
| 68 | */ | |
| 69 | dummy: dummy { | |
| 70 | #clock-cells = <0>; | |
| 71 | compatible = "fixed-clock"; | |
| 72 | clock-frequency = <0>; | |
| 73 | }; | |
| 74 | ||
| dfb12c0c | 75 | osc24M: clk@01c20050 { |
| 69144e3b | 76 | #clock-cells = <0>; |
| bf6534a1 | 77 | compatible = "allwinner,sun4i-a10-osc-clk"; |
| 69144e3b | 78 | reg = <0x01c20050 0x4>; |
| 92fd6e06 | 79 | clock-frequency = <24000000>; |
| dfb12c0c | 80 | clock-output-names = "osc24M"; |
| 69144e3b MR |
81 | }; |
| 82 | ||
| dfb12c0c | 83 | osc32k: clk@0 { |
| 69144e3b MR |
84 | #clock-cells = <0>; |
| 85 | compatible = "fixed-clock"; | |
| 86 | clock-frequency = <32768>; | |
| dfb12c0c | 87 | clock-output-names = "osc32k"; |
| 69144e3b MR |
88 | }; |
| 89 | ||
| dfb12c0c | 90 | pll1: clk@01c20000 { |
| 69144e3b | 91 | #clock-cells = <0>; |
| bf6534a1 | 92 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| 69144e3b MR |
93 | reg = <0x01c20000 0x4>; |
| 94 | clocks = <&osc24M>; | |
| dfb12c0c | 95 | clock-output-names = "pll1"; |
| 69144e3b MR |
96 | }; |
| 97 | ||
| dfb12c0c | 98 | pll4: clk@01c20018 { |
| ec5589f7 | 99 | #clock-cells = <0>; |
| bf6534a1 | 100 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
| ec5589f7 EL |
101 | reg = <0x01c20018 0x4>; |
| 102 | clocks = <&osc24M>; | |
| dfb12c0c | 103 | clock-output-names = "pll4"; |
| ec5589f7 EL |
104 | }; |
| 105 | ||
| dfb12c0c | 106 | pll5: clk@01c20020 { |
| c3e5e66b | 107 | #clock-cells = <1>; |
| bf6534a1 | 108 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
| c3e5e66b EL |
109 | reg = <0x01c20020 0x4>; |
| 110 | clocks = <&osc24M>; | |
| 111 | clock-output-names = "pll5_ddr", "pll5_other"; | |
| 112 | }; | |
| 113 | ||
| dfb12c0c | 114 | pll6: clk@01c20028 { |
| c3e5e66b | 115 | #clock-cells = <1>; |
| bf6534a1 | 116 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
| c3e5e66b EL |
117 | reg = <0x01c20028 0x4>; |
| 118 | clocks = <&osc24M>; | |
| 119 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
| 120 | }; | |
| 121 | ||
| 69144e3b MR |
122 | /* dummy is 200M */ |
| 123 | cpu: cpu@01c20054 { | |
| 124 | #clock-cells = <0>; | |
| bf6534a1 | 125 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
| 69144e3b MR |
126 | reg = <0x01c20054 0x4>; |
| 127 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
| dfb12c0c | 128 | clock-output-names = "cpu"; |
| 69144e3b MR |
129 | }; |
| 130 | ||
| 131 | axi: axi@01c20054 { | |
| 132 | #clock-cells = <0>; | |
| bf6534a1 | 133 | compatible = "allwinner,sun4i-a10-axi-clk"; |
| 69144e3b MR |
134 | reg = <0x01c20054 0x4>; |
| 135 | clocks = <&cpu>; | |
| dfb12c0c | 136 | clock-output-names = "axi"; |
| 69144e3b MR |
137 | }; |
| 138 | ||
| dfb12c0c | 139 | axi_gates: clk@01c2005c { |
| 69144e3b | 140 | #clock-cells = <1>; |
| bf6534a1 | 141 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
| 69144e3b MR |
142 | reg = <0x01c2005c 0x4>; |
| 143 | clocks = <&axi>; | |
| 144 | clock-output-names = "axi_dram"; | |
| 145 | }; | |
| 146 | ||
| 147 | ahb: ahb@01c20054 { | |
| 148 | #clock-cells = <0>; | |
| bf6534a1 | 149 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
| 69144e3b MR |
150 | reg = <0x01c20054 0x4>; |
| 151 | clocks = <&axi>; | |
| dfb12c0c | 152 | clock-output-names = "ahb"; |
| 69144e3b MR |
153 | }; |
| 154 | ||
| dfb12c0c | 155 | ahb_gates: clk@01c20060 { |
| 69144e3b | 156 | #clock-cells = <1>; |
| bf6534a1 | 157 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
| 69144e3b MR |
158 | reg = <0x01c20060 0x8>; |
| 159 | clocks = <&ahb>; | |
| 160 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
| 161 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
| 162 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
| 163 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
| 164 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
| 165 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
| 166 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
| 167 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
| 168 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
| 169 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
| 170 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
| 171 | }; | |
| 172 | ||
| 173 | apb0: apb0@01c20054 { | |
| 174 | #clock-cells = <0>; | |
| bf6534a1 | 175 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
| 69144e3b MR |
176 | reg = <0x01c20054 0x4>; |
| 177 | clocks = <&ahb>; | |
| dfb12c0c | 178 | clock-output-names = "apb0"; |
| 69144e3b MR |
179 | }; |
| 180 | ||
| dfb12c0c | 181 | apb0_gates: clk@01c20068 { |
| 69144e3b | 182 | #clock-cells = <1>; |
| bf6534a1 | 183 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
| 69144e3b MR |
184 | reg = <0x01c20068 0x4>; |
| 185 | clocks = <&apb0>; | |
| 186 | clock-output-names = "apb0_codec", "apb0_spdif", | |
| 187 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
| 188 | "apb0_ir1", "apb0_keypad"; | |
| 189 | }; | |
| 190 | ||
| 69144e3b MR |
191 | apb1_mux: apb1_mux@01c20058 { |
| 192 | #clock-cells = <0>; | |
| bf6534a1 | 193 | compatible = "allwinner,sun4i-a10-apb1-mux-clk"; |
| 69144e3b | 194 | reg = <0x01c20058 0x4>; |
| c3e5e66b | 195 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
| dfb12c0c | 196 | clock-output-names = "apb1_mux"; |
| 69144e3b MR |
197 | }; |
| 198 | ||
| 199 | apb1: apb1@01c20058 { | |
| 200 | #clock-cells = <0>; | |
| bf6534a1 | 201 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
| 69144e3b MR |
202 | reg = <0x01c20058 0x4>; |
| 203 | clocks = <&apb1_mux>; | |
| dfb12c0c | 204 | clock-output-names = "apb1"; |
| 69144e3b MR |
205 | }; |
| 206 | ||
| dfb12c0c | 207 | apb1_gates: clk@01c2006c { |
| 69144e3b | 208 | #clock-cells = <1>; |
| bf6534a1 | 209 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
| 69144e3b MR |
210 | reg = <0x01c2006c 0x4>; |
| 211 | clocks = <&apb1>; | |
| 212 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
| 213 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
| 214 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
| 215 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
| 216 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
| 217 | "apb1_uart7"; | |
| 218 | }; | |
| 4b756ffb EL |
219 | |
| 220 | nand_clk: clk@01c20080 { | |
| 221 | #clock-cells = <0>; | |
| bf6534a1 | 222 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
223 | reg = <0x01c20080 0x4>; |
| 224 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 225 | clock-output-names = "nand"; | |
| 226 | }; | |
| 227 | ||
| 228 | ms_clk: clk@01c20084 { | |
| 229 | #clock-cells = <0>; | |
| bf6534a1 | 230 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
231 | reg = <0x01c20084 0x4>; |
| 232 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 233 | clock-output-names = "ms"; | |
| 234 | }; | |
| 235 | ||
| 236 | mmc0_clk: clk@01c20088 { | |
| 237 | #clock-cells = <0>; | |
| bf6534a1 | 238 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
239 | reg = <0x01c20088 0x4>; |
| 240 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 241 | clock-output-names = "mmc0"; | |
| 242 | }; | |
| 243 | ||
| 244 | mmc1_clk: clk@01c2008c { | |
| 245 | #clock-cells = <0>; | |
| bf6534a1 | 246 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
247 | reg = <0x01c2008c 0x4>; |
| 248 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 249 | clock-output-names = "mmc1"; | |
| 250 | }; | |
| 251 | ||
| 252 | mmc2_clk: clk@01c20090 { | |
| 253 | #clock-cells = <0>; | |
| bf6534a1 | 254 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
255 | reg = <0x01c20090 0x4>; |
| 256 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 257 | clock-output-names = "mmc2"; | |
| 258 | }; | |
| 259 | ||
| 260 | mmc3_clk: clk@01c20094 { | |
| 261 | #clock-cells = <0>; | |
| bf6534a1 | 262 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
263 | reg = <0x01c20094 0x4>; |
| 264 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 265 | clock-output-names = "mmc3"; | |
| 266 | }; | |
| 267 | ||
| 268 | ts_clk: clk@01c20098 { | |
| 269 | #clock-cells = <0>; | |
| bf6534a1 | 270 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
271 | reg = <0x01c20098 0x4>; |
| 272 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 273 | clock-output-names = "ts"; | |
| 274 | }; | |
| 275 | ||
| 276 | ss_clk: clk@01c2009c { | |
| 277 | #clock-cells = <0>; | |
| bf6534a1 | 278 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
279 | reg = <0x01c2009c 0x4>; |
| 280 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 281 | clock-output-names = "ss"; | |
| 282 | }; | |
| 283 | ||
| 284 | spi0_clk: clk@01c200a0 { | |
| 285 | #clock-cells = <0>; | |
| bf6534a1 | 286 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
287 | reg = <0x01c200a0 0x4>; |
| 288 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 289 | clock-output-names = "spi0"; | |
| 290 | }; | |
| 291 | ||
| 292 | spi1_clk: clk@01c200a4 { | |
| 293 | #clock-cells = <0>; | |
| bf6534a1 | 294 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
295 | reg = <0x01c200a4 0x4>; |
| 296 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 297 | clock-output-names = "spi1"; | |
| 298 | }; | |
| 299 | ||
| 300 | spi2_clk: clk@01c200a8 { | |
| 301 | #clock-cells = <0>; | |
| bf6534a1 | 302 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
303 | reg = <0x01c200a8 0x4>; |
| 304 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 305 | clock-output-names = "spi2"; | |
| 306 | }; | |
| 307 | ||
| 308 | pata_clk: clk@01c200ac { | |
| 309 | #clock-cells = <0>; | |
| bf6534a1 | 310 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
311 | reg = <0x01c200ac 0x4>; |
| 312 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 313 | clock-output-names = "pata"; | |
| 314 | }; | |
| 315 | ||
| 316 | ir0_clk: clk@01c200b0 { | |
| 317 | #clock-cells = <0>; | |
| bf6534a1 | 318 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
319 | reg = <0x01c200b0 0x4>; |
| 320 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 321 | clock-output-names = "ir0"; | |
| 322 | }; | |
| 323 | ||
| 324 | ir1_clk: clk@01c200b4 { | |
| 325 | #clock-cells = <0>; | |
| bf6534a1 | 326 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
327 | reg = <0x01c200b4 0x4>; |
| 328 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 329 | clock-output-names = "ir1"; | |
| 330 | }; | |
| 331 | ||
| 0076c8bd RB |
332 | usb_clk: clk@01c200cc { |
| 333 | #clock-cells = <1>; | |
| 334 | #reset-cells = <1>; | |
| 335 | compatible = "allwinner,sun4i-a10-usb-clk"; | |
| 336 | reg = <0x01c200cc 0x4>; | |
| 337 | clocks = <&pll6 1>; | |
| 338 | clock-output-names = "usb_ohci0", "usb_ohci1", "usb_phy"; | |
| 339 | }; | |
| 340 | ||
| 4b756ffb EL |
341 | spi3_clk: clk@01c200d4 { |
| 342 | #clock-cells = <0>; | |
| bf6534a1 | 343 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
| 4b756ffb EL |
344 | reg = <0x01c200d4 0x4>; |
| 345 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
| 346 | clock-output-names = "spi3"; | |
| 347 | }; | |
| 69144e3b MR |
348 | }; |
| 349 | ||
| b74aec1a | 350 | soc@01c00000 { |
| 69144e3b MR |
351 | compatible = "simple-bus"; |
| 352 | #address-cells = <1>; | |
| 353 | #size-cells = <1>; | |
| 69144e3b MR |
354 | ranges; |
| 355 | ||
| 1324f532 EL |
356 | dma: dma-controller@01c02000 { |
| 357 | compatible = "allwinner,sun4i-a10-dma"; | |
| 358 | reg = <0x01c02000 0x1000>; | |
| 359 | interrupts = <27>; | |
| 360 | clocks = <&ahb_gates 6>; | |
| 361 | #dma-cells = <2>; | |
| 362 | }; | |
| 363 | ||
| 65918e26 MR |
364 | spi0: spi@01c05000 { |
| 365 | compatible = "allwinner,sun4i-a10-spi"; | |
| 366 | reg = <0x01c05000 0x1000>; | |
| 367 | interrupts = <10>; | |
| 368 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
| 369 | clock-names = "ahb", "mod"; | |
| 4192ff81 EL |
370 | dmas = <&dma 1 27>, <&dma 1 26>; |
| 371 | dma-names = "rx", "tx"; | |
| 65918e26 MR |
372 | status = "disabled"; |
| 373 | #address-cells = <1>; | |
| 374 | #size-cells = <0>; | |
| 375 | }; | |
| 376 | ||
| 377 | spi1: spi@01c06000 { | |
| 378 | compatible = "allwinner,sun4i-a10-spi"; | |
| 379 | reg = <0x01c06000 0x1000>; | |
| 380 | interrupts = <11>; | |
| 381 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
| 382 | clock-names = "ahb", "mod"; | |
| 4192ff81 EL |
383 | dmas = <&dma 1 9>, <&dma 1 8>; |
| 384 | dma-names = "rx", "tx"; | |
| 65918e26 MR |
385 | status = "disabled"; |
| 386 | #address-cells = <1>; | |
| 387 | #size-cells = <0>; | |
| 388 | }; | |
| 389 | ||
| e38afcb3 | 390 | emac: ethernet@01c0b000 { |
| 1c70e099 | 391 | compatible = "allwinner,sun4i-a10-emac"; |
| e38afcb3 MR |
392 | reg = <0x01c0b000 0x1000>; |
| 393 | interrupts = <55>; | |
| 394 | clocks = <&ahb_gates 17>; | |
| 395 | status = "disabled"; | |
| 396 | }; | |
| 397 | ||
| 398 | mdio@01c0b080 { | |
| 1c70e099 | 399 | compatible = "allwinner,sun4i-a10-mdio"; |
| e38afcb3 MR |
400 | reg = <0x01c0b080 0x14>; |
| 401 | status = "disabled"; | |
| 402 | #address-cells = <1>; | |
| 403 | #size-cells = <0>; | |
| 404 | }; | |
| 405 | ||
| b258b369 DL |
406 | mmc0: mmc@01c0f000 { |
| 407 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 408 | reg = <0x01c0f000 0x1000>; | |
| 409 | clocks = <&ahb_gates 8>, <&mmc0_clk>; | |
| 410 | clock-names = "ahb", "mmc"; | |
| 411 | interrupts = <32>; | |
| 412 | status = "disabled"; | |
| 413 | }; | |
| 414 | ||
| 415 | mmc1: mmc@01c10000 { | |
| 416 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 417 | reg = <0x01c10000 0x1000>; | |
| 418 | clocks = <&ahb_gates 9>, <&mmc1_clk>; | |
| 419 | clock-names = "ahb", "mmc"; | |
| 420 | interrupts = <33>; | |
| 421 | status = "disabled"; | |
| 422 | }; | |
| 423 | ||
| 424 | mmc2: mmc@01c11000 { | |
| 425 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 426 | reg = <0x01c11000 0x1000>; | |
| 427 | clocks = <&ahb_gates 10>, <&mmc2_clk>; | |
| 428 | clock-names = "ahb", "mmc"; | |
| 429 | interrupts = <34>; | |
| 430 | status = "disabled"; | |
| 431 | }; | |
| 432 | ||
| 433 | mmc3: mmc@01c12000 { | |
| 434 | compatible = "allwinner,sun4i-a10-mmc"; | |
| 435 | reg = <0x01c12000 0x1000>; | |
| 436 | clocks = <&ahb_gates 11>, <&mmc3_clk>; | |
| 437 | clock-names = "ahb", "mmc"; | |
| 438 | interrupts = <35>; | |
| 439 | status = "disabled"; | |
| 440 | }; | |
| 441 | ||
| 6ab1ce24 RB |
442 | usbphy: phy@01c13400 { |
| 443 | #phy-cells = <1>; | |
| 444 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
| 445 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
| 446 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
| 447 | clocks = <&usb_clk 8>; | |
| 448 | clock-names = "usb_phy"; | |
| 449 | resets = <&usb_clk 1>, <&usb_clk 2>; | |
| 450 | reset-names = "usb1_reset", "usb2_reset"; | |
| 451 | status = "disabled"; | |
| 452 | }; | |
| 453 | ||
| 454 | ehci0: usb@01c14000 { | |
| 455 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
| 456 | reg = <0x01c14000 0x100>; | |
| 457 | interrupts = <39>; | |
| 458 | clocks = <&ahb_gates 1>; | |
| 459 | phys = <&usbphy 1>; | |
| 460 | phy-names = "usb"; | |
| 461 | status = "disabled"; | |
| 462 | }; | |
| 463 | ||
| 464 | ohci0: usb@01c14400 { | |
| 465 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
| 466 | reg = <0x01c14400 0x100>; | |
| 467 | interrupts = <64>; | |
| 468 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
| 469 | phys = <&usbphy 1>; | |
| 470 | phy-names = "usb"; | |
| 471 | status = "disabled"; | |
| 472 | }; | |
| 473 | ||
| 65918e26 MR |
474 | spi2: spi@01c17000 { |
| 475 | compatible = "allwinner,sun4i-a10-spi"; | |
| 476 | reg = <0x01c17000 0x1000>; | |
| 477 | interrupts = <12>; | |
| 478 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
| 479 | clock-names = "ahb", "mod"; | |
| 4192ff81 EL |
480 | dmas = <&dma 1 29>, <&dma 1 28>; |
| 481 | dma-names = "rx", "tx"; | |
| 65918e26 MR |
482 | status = "disabled"; |
| 483 | #address-cells = <1>; | |
| 484 | #size-cells = <0>; | |
| 485 | }; | |
| 486 | ||
| 248bd1e2 OS |
487 | ahci: sata@01c18000 { |
| 488 | compatible = "allwinner,sun4i-a10-ahci"; | |
| 489 | reg = <0x01c18000 0x1000>; | |
| 490 | interrupts = <56>; | |
| 491 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
| 492 | status = "disabled"; | |
| 493 | }; | |
| 494 | ||
| 6ab1ce24 RB |
495 | ehci1: usb@01c1c000 { |
| 496 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
| 497 | reg = <0x01c1c000 0x100>; | |
| 498 | interrupts = <40>; | |
| 499 | clocks = <&ahb_gates 3>; | |
| 500 | phys = <&usbphy 2>; | |
| 501 | phy-names = "usb"; | |
| 502 | status = "disabled"; | |
| 503 | }; | |
| 504 | ||
| 505 | ohci1: usb@01c1c400 { | |
| 506 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
| 507 | reg = <0x01c1c400 0x100>; | |
| 508 | interrupts = <65>; | |
| 509 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
| 510 | phys = <&usbphy 2>; | |
| 511 | phy-names = "usb"; | |
| 512 | status = "disabled"; | |
| 513 | }; | |
| 514 | ||
| 65918e26 MR |
515 | spi3: spi@01c1f000 { |
| 516 | compatible = "allwinner,sun4i-a10-spi"; | |
| 517 | reg = <0x01c1f000 0x1000>; | |
| 518 | interrupts = <50>; | |
| 519 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
| 520 | clock-names = "ahb", "mod"; | |
| 4192ff81 EL |
521 | dmas = <&dma 1 31>, <&dma 1 30>; |
| 522 | dma-names = "rx", "tx"; | |
| 65918e26 MR |
523 | status = "disabled"; |
| 524 | #address-cells = <1>; | |
| 525 | #size-cells = <0>; | |
| 526 | }; | |
| 527 | ||
| 69144e3b | 528 | intc: interrupt-controller@01c20400 { |
| 09504a7d | 529 | compatible = "allwinner,sun4i-a10-ic"; |
| 69144e3b MR |
530 | reg = <0x01c20400 0x400>; |
| 531 | interrupt-controller; | |
| 532 | #interrupt-cells = <1>; | |
| 533 | }; | |
| 534 | ||
| e10911e1 | 535 | pio: pinctrl@01c20800 { |
| 874b4e45 MR |
536 | compatible = "allwinner,sun4i-a10-pinctrl"; |
| 537 | reg = <0x01c20800 0x400>; | |
| 39138bc6 | 538 | interrupts = <28>; |
| 36386d6e | 539 | clocks = <&apb0_gates 5>; |
| e10911e1 | 540 | gpio-controller; |
| 39138bc6 | 541 | interrupt-controller; |
| 7d4ff96d | 542 | #interrupt-cells = <2>; |
| 874b4e45 | 543 | #size-cells = <0>; |
| e10911e1 | 544 | #gpio-cells = <3>; |
| 581981be | 545 | |
| 1d5726e9 AB |
546 | pwm0_pins_a: pwm0@0 { |
| 547 | allwinner,pins = "PB2"; | |
| 548 | allwinner,function = "pwm"; | |
| 549 | allwinner,drive = <0>; | |
| 550 | allwinner,pull = <0>; | |
| 551 | }; | |
| 552 | ||
| 553 | pwm1_pins_a: pwm1@0 { | |
| 554 | allwinner,pins = "PI3"; | |
| 555 | allwinner,function = "pwm"; | |
| 556 | allwinner,drive = <0>; | |
| 557 | allwinner,pull = <0>; | |
| 558 | }; | |
| 559 | ||
| 581981be MR |
560 | uart0_pins_a: uart0@0 { |
| 561 | allwinner,pins = "PB22", "PB23"; | |
| 562 | allwinner,function = "uart0"; | |
| 563 | allwinner,drive = <0>; | |
| 564 | allwinner,pull = <0>; | |
| 565 | }; | |
| 566 | ||
| 567 | uart0_pins_b: uart0@1 { | |
| 568 | allwinner,pins = "PF2", "PF4"; | |
| 569 | allwinner,function = "uart0"; | |
| 570 | allwinner,drive = <0>; | |
| 571 | allwinner,pull = <0>; | |
| 572 | }; | |
| 573 | ||
| 574 | uart1_pins_a: uart1@0 { | |
| 575 | allwinner,pins = "PA10", "PA11"; | |
| 576 | allwinner,function = "uart1"; | |
| 577 | allwinner,drive = <0>; | |
| 578 | allwinner,pull = <0>; | |
| 579 | }; | |
| 27cce4ff MR |
580 | |
| 581 | i2c0_pins_a: i2c0@0 { | |
| 582 | allwinner,pins = "PB0", "PB1"; | |
| 583 | allwinner,function = "i2c0"; | |
| 584 | allwinner,drive = <0>; | |
| 585 | allwinner,pull = <0>; | |
| 586 | }; | |
| 587 | ||
| 588 | i2c1_pins_a: i2c1@0 { | |
| 589 | allwinner,pins = "PB18", "PB19"; | |
| 590 | allwinner,function = "i2c1"; | |
| 591 | allwinner,drive = <0>; | |
| 592 | allwinner,pull = <0>; | |
| 593 | }; | |
| 594 | ||
| 595 | i2c2_pins_a: i2c2@0 { | |
| 596 | allwinner,pins = "PB20", "PB21"; | |
| 597 | allwinner,function = "i2c2"; | |
| 598 | allwinner,drive = <0>; | |
| 599 | allwinner,pull = <0>; | |
| 600 | }; | |
| 496322bc | 601 | |
| b21da664 MR |
602 | emac_pins_a: emac0@0 { |
| 603 | allwinner,pins = "PA0", "PA1", "PA2", | |
| 604 | "PA3", "PA4", "PA5", "PA6", | |
| 605 | "PA7", "PA8", "PA9", "PA10", | |
| 606 | "PA11", "PA12", "PA13", "PA14", | |
| 607 | "PA15", "PA16"; | |
| 608 | allwinner,function = "emac"; | |
| 609 | allwinner,drive = <0>; | |
| 610 | allwinner,pull = <0>; | |
| 611 | }; | |
| b5f86a3a HG |
612 | |
| 613 | mmc0_pins_a: mmc0@0 { | |
| 614 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
| 615 | allwinner,function = "mmc0"; | |
| 616 | allwinner,drive = <2>; | |
| 617 | allwinner,pull = <0>; | |
| 618 | }; | |
| 619 | ||
| 620 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
| 621 | allwinner,pins = "PH1"; | |
| 622 | allwinner,function = "gpio_in"; | |
| 623 | allwinner,drive = <0>; | |
| 624 | allwinner,pull = <1>; | |
| 625 | }; | |
| a4e1099a HG |
626 | |
| 627 | ir0_pins_a: ir0@0 { | |
| 628 | allwinner,pins = "PB3","PB4"; | |
| 629 | allwinner,function = "ir0"; | |
| 630 | allwinner,drive = <0>; | |
| 631 | allwinner,pull = <0>; | |
| 632 | }; | |
| 633 | ||
| 634 | ir1_pins_a: ir1@0 { | |
| 635 | allwinner,pins = "PB22","PB23"; | |
| 636 | allwinner,function = "ir1"; | |
| 637 | allwinner,drive = <0>; | |
| 638 | allwinner,pull = <0>; | |
| 639 | }; | |
| 874b4e45 | 640 | }; |
| 89b3c99f | 641 | |
| 69144e3b | 642 | timer@01c20c00 { |
| b4f26440 | 643 | compatible = "allwinner,sun4i-a10-timer"; |
| 69144e3b MR |
644 | reg = <0x01c20c00 0x90>; |
| 645 | interrupts = <22>; | |
| 646 | clocks = <&osc24M>; | |
| 647 | }; | |
| 648 | ||
| 649 | wdt: watchdog@01c20c90 { | |
| ca5d04d9 | 650 | compatible = "allwinner,sun4i-a10-wdt"; |
| 69144e3b MR |
651 | reg = <0x01c20c90 0x10>; |
| 652 | }; | |
| 653 | ||
| b5d905c7 | 654 | rtc: rtc@01c20d00 { |
| 5fc4bc89 | 655 | compatible = "allwinner,sun4i-a10-rtc"; |
| b5d905c7 CC |
656 | reg = <0x01c20d00 0x20>; |
| 657 | interrupts = <24>; | |
| 658 | }; | |
| 659 | ||
| 4b57a395 AB |
660 | pwm: pwm@01c20e00 { |
| 661 | compatible = "allwinner,sun4i-a10-pwm"; | |
| 662 | reg = <0x01c20e00 0xc>; | |
| 663 | clocks = <&osc24M>; | |
| 664 | #pwm-cells = <3>; | |
| 665 | status = "disabled"; | |
| 666 | }; | |
| 667 | ||
| a4e1099a HG |
668 | ir0: ir@01c21800 { |
| 669 | compatible = "allwinner,sun4i-a10-ir"; | |
| 670 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
| 671 | clock-names = "apb", "ir"; | |
| 672 | interrupts = <5>; | |
| 673 | reg = <0x01c21800 0x40>; | |
| 674 | status = "disabled"; | |
| 675 | }; | |
| 676 | ||
| 677 | ir1: ir@01c21c00 { | |
| 678 | compatible = "allwinner,sun4i-a10-ir"; | |
| 679 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
| 680 | clock-names = "apb", "ir"; | |
| 681 | interrupts = <6>; | |
| 682 | reg = <0x01c21c00 0x40>; | |
| 683 | status = "disabled"; | |
| 684 | }; | |
| 685 | ||
| 2bad969f | 686 | sid: eeprom@01c23800 { |
| 043d56ee | 687 | compatible = "allwinner,sun4i-a10-sid"; |
| 2bad969f OS |
688 | reg = <0x01c23800 0x10>; |
| 689 | }; | |
| 690 | ||
| 57c8839c | 691 | rtp: rtp@01c25000 { |
| 40dd8f3b | 692 | compatible = "allwinner,sun4i-a10-ts"; |
| 57c8839c HG |
693 | reg = <0x01c25000 0x100>; |
| 694 | interrupts = <29>; | |
| 695 | }; | |
| 696 | ||
| 89b3c99f MR |
697 | uart0: serial@01c28000 { |
| 698 | compatible = "snps,dw-apb-uart"; | |
| 699 | reg = <0x01c28000 0x400>; | |
| 700 | interrupts = <1>; | |
| 701 | reg-shift = <2>; | |
| 702 | reg-io-width = <4>; | |
| 9ff49ec7 | 703 | clocks = <&apb1_gates 16>; |
| 89b3c99f MR |
704 | status = "disabled"; |
| 705 | }; | |
| 76f14d0a | 706 | |
| 69144e3b MR |
707 | uart1: serial@01c28400 { |
| 708 | compatible = "snps,dw-apb-uart"; | |
| 709 | reg = <0x01c28400 0x400>; | |
| 710 | interrupts = <2>; | |
| 711 | reg-shift = <2>; | |
| 712 | reg-io-width = <4>; | |
| 713 | clocks = <&apb1_gates 17>; | |
| 714 | status = "disabled"; | |
| 715 | }; | |
| 716 | ||
| 76f14d0a MR |
717 | uart2: serial@01c28800 { |
| 718 | compatible = "snps,dw-apb-uart"; | |
| 719 | reg = <0x01c28800 0x400>; | |
| 720 | interrupts = <3>; | |
| 721 | reg-shift = <2>; | |
| 722 | reg-io-width = <4>; | |
| 9ff49ec7 | 723 | clocks = <&apb1_gates 18>; |
| 76f14d0a MR |
724 | status = "disabled"; |
| 725 | }; | |
| 726 | ||
| 69144e3b MR |
727 | uart3: serial@01c28c00 { |
| 728 | compatible = "snps,dw-apb-uart"; | |
| 729 | reg = <0x01c28c00 0x400>; | |
| 730 | interrupts = <4>; | |
| 731 | reg-shift = <2>; | |
| 732 | reg-io-width = <4>; | |
| 733 | clocks = <&apb1_gates 19>; | |
| 734 | status = "disabled"; | |
| 735 | }; | |
| 736 | ||
| 76f14d0a MR |
737 | uart4: serial@01c29000 { |
| 738 | compatible = "snps,dw-apb-uart"; | |
| 739 | reg = <0x01c29000 0x400>; | |
| 740 | interrupts = <17>; | |
| 741 | reg-shift = <2>; | |
| 742 | reg-io-width = <4>; | |
| 9ff49ec7 | 743 | clocks = <&apb1_gates 20>; |
| 76f14d0a MR |
744 | status = "disabled"; |
| 745 | }; | |
| 746 | ||
| 747 | uart5: serial@01c29400 { | |
| 748 | compatible = "snps,dw-apb-uart"; | |
| 749 | reg = <0x01c29400 0x400>; | |
| 750 | interrupts = <18>; | |
| 751 | reg-shift = <2>; | |
| 752 | reg-io-width = <4>; | |
| 9ff49ec7 | 753 | clocks = <&apb1_gates 21>; |
| 76f14d0a MR |
754 | status = "disabled"; |
| 755 | }; | |
| 756 | ||
| 757 | uart6: serial@01c29800 { | |
| 758 | compatible = "snps,dw-apb-uart"; | |
| 759 | reg = <0x01c29800 0x400>; | |
| 760 | interrupts = <19>; | |
| 761 | reg-shift = <2>; | |
| 762 | reg-io-width = <4>; | |
| 9ff49ec7 | 763 | clocks = <&apb1_gates 22>; |
| 76f14d0a MR |
764 | status = "disabled"; |
| 765 | }; | |
| 766 | ||
| 767 | uart7: serial@01c29c00 { | |
| 768 | compatible = "snps,dw-apb-uart"; | |
| 769 | reg = <0x01c29c00 0x400>; | |
| 770 | interrupts = <20>; | |
| 771 | reg-shift = <2>; | |
| 772 | reg-io-width = <4>; | |
| 9ff49ec7 | 773 | clocks = <&apb1_gates 23>; |
| 76f14d0a MR |
774 | status = "disabled"; |
| 775 | }; | |
| f1741fda MR |
776 | |
| 777 | i2c0: i2c@01c2ac00 { | |
| d275545e | 778 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
779 | reg = <0x01c2ac00 0x400>; |
| 780 | interrupts = <7>; | |
| 781 | clocks = <&apb1_gates 0>; | |
| f1741fda | 782 | status = "disabled"; |
| 60bbe316 HG |
783 | #address-cells = <1>; |
| 784 | #size-cells = <0>; | |
| f1741fda MR |
785 | }; |
| 786 | ||
| 787 | i2c1: i2c@01c2b000 { | |
| d275545e | 788 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
789 | reg = <0x01c2b000 0x400>; |
| 790 | interrupts = <8>; | |
| 791 | clocks = <&apb1_gates 1>; | |
| f1741fda | 792 | status = "disabled"; |
| 60bbe316 HG |
793 | #address-cells = <1>; |
| 794 | #size-cells = <0>; | |
| f1741fda MR |
795 | }; |
| 796 | ||
| 797 | i2c2: i2c@01c2b400 { | |
| d275545e | 798 | compatible = "allwinner,sun4i-a10-i2c"; |
| f1741fda MR |
799 | reg = <0x01c2b400 0x400>; |
| 800 | interrupts = <9>; | |
| 801 | clocks = <&apb1_gates 2>; | |
| f1741fda | 802 | status = "disabled"; |
| 60bbe316 HG |
803 | #address-cells = <1>; |
| 804 | #size-cells = <0>; | |
| f1741fda | 805 | }; |
| 874b4e45 | 806 | }; |
| 7423d2d8 | 807 | }; |