Commit | Line | Data |
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7423d2d8 SR |
1 | /* |
2 | * Copyright 2012 Stefan Roese | |
3 | * Stefan Roese <sr@denx.de> | |
4 | * | |
033ba3d7 MR |
5 | * This file is dual-licensed: you can use it either under the terms |
6 | * of the GPL or the X11 license, at your option. Note that this dual | |
7 | * licensing only applies to this file, and not this project as a | |
8 | * whole. | |
7423d2d8 | 9 | * |
033ba3d7 MR |
10 | * a) This library is free software; you can redistribute it and/or |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of the | |
13 | * License, or (at your option) any later version. | |
14 | * | |
15 | * This library is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
033ba3d7 MR |
20 | * Or, alternatively, |
21 | * | |
22 | * b) Permission is hereby granted, free of charge, to any person | |
23 | * obtaining a copy of this software and associated documentation | |
24 | * files (the "Software"), to deal in the Software without | |
25 | * restriction, including without limitation the rights to use, | |
26 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
27 | * sell copies of the Software, and to permit persons to whom the | |
28 | * Software is furnished to do so, subject to the following | |
29 | * conditions: | |
30 | * | |
31 | * The above copyright notice and this permission notice shall be | |
32 | * included in all copies or substantial portions of the Software. | |
33 | * | |
34 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
35 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
36 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
37 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
38 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
39 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
40 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
41 | * OTHER DEALINGS IN THE SOFTWARE. | |
7423d2d8 SR |
42 | */ |
43 | ||
71455701 | 44 | #include "skeleton.dtsi" |
7423d2d8 | 45 | |
541ce2ca CYT |
46 | #include <dt-bindings/thermal/thermal.h> |
47 | ||
1f9f6a78 | 48 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 49 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
7423d2d8 SR |
50 | |
51 | / { | |
69144e3b MR |
52 | interrupt-parent = <&intc>; |
53 | ||
e751cce9 EL |
54 | aliases { |
55 | ethernet0 = &emac; | |
56 | }; | |
57 | ||
5790d4ee HG |
58 | chosen { |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | ranges; | |
62 | ||
a9f8cda3 | 63 | framebuffer@0 { |
d8cacaa3 MR |
64 | compatible = "allwinner,simple-framebuffer", |
65 | "simple-framebuffer"; | |
a9f8cda3 | 66 | allwinner,pipeline = "de_be0-lcd0-hdmi"; |
678e75d3 HG |
67 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
68 | <&ahb_gates 44>; | |
5790d4ee HG |
69 | status = "disabled"; |
70 | }; | |
8cedd662 HG |
71 | |
72 | framebuffer@1 { | |
d8cacaa3 MR |
73 | compatible = "allwinner,simple-framebuffer", |
74 | "simple-framebuffer"; | |
8cedd662 HG |
75 | allwinner,pipeline = "de_fe0-de_be0-lcd0-hdmi"; |
76 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, | |
77 | <&ahb_gates 44>, <&ahb_gates 46>; | |
78 | status = "disabled"; | |
79 | }; | |
fd18c7ea HG |
80 | |
81 | framebuffer@2 { | |
82 | compatible = "allwinner,simple-framebuffer", | |
83 | "simple-framebuffer"; | |
84 | allwinner,pipeline = "de_fe0-de_be0-lcd0"; | |
85 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>, | |
86 | <&ahb_gates 46>; | |
87 | status = "disabled"; | |
88 | }; | |
89 | ||
90 | framebuffer@3 { | |
91 | compatible = "allwinner,simple-framebuffer", | |
92 | "simple-framebuffer"; | |
93 | allwinner,pipeline = "de_fe0-de_be0-lcd0-tve0"; | |
94 | clocks = <&pll5 1>, <&ahb_gates 34>, <&ahb_gates 36>, | |
95 | <&ahb_gates 44>, <&ahb_gates 46>; | |
96 | status = "disabled"; | |
97 | }; | |
5790d4ee HG |
98 | }; |
99 | ||
69144e3b | 100 | cpus { |
8b2efa89 AB |
101 | #address-cells = <1>; |
102 | #size-cells = <0>; | |
7294be5d | 103 | cpu0: cpu@0 { |
14c44aa5 | 104 | device_type = "cpu"; |
69144e3b | 105 | compatible = "arm,cortex-a8"; |
14c44aa5 | 106 | reg = <0x0>; |
7294be5d CYT |
107 | clocks = <&cpu>; |
108 | clock-latency = <244144>; /* 8 32k periods */ | |
109 | operating-points = < | |
8358aada | 110 | /* kHz uV */ |
7294be5d | 111 | 1008000 1400000 |
8358aada MR |
112 | 912000 1350000 |
113 | 864000 1300000 | |
114 | 624000 1250000 | |
7294be5d CYT |
115 | >; |
116 | #cooling-cells = <2>; | |
117 | cooling-min-level = <0>; | |
370a9b5f | 118 | cooling-max-level = <3>; |
69144e3b MR |
119 | }; |
120 | }; | |
121 | ||
541ce2ca CYT |
122 | thermal-zones { |
123 | cpu_thermal { | |
124 | /* milliseconds */ | |
125 | polling-delay-passive = <250>; | |
126 | polling-delay = <1000>; | |
127 | thermal-sensors = <&rtp>; | |
128 | ||
129 | cooling-maps { | |
130 | map0 { | |
131 | trip = <&cpu_alert0>; | |
132 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
133 | }; | |
134 | }; | |
135 | ||
136 | trips { | |
137 | cpu_alert0: cpu_alert0 { | |
138 | /* milliCelsius */ | |
139 | temperature = <850000>; | |
140 | hysteresis = <2000>; | |
141 | type = "passive"; | |
142 | }; | |
143 | ||
144 | cpu_crit: cpu_crit { | |
145 | /* milliCelsius */ | |
146 | temperature = <100000>; | |
147 | hysteresis = <2000>; | |
148 | type = "critical"; | |
149 | }; | |
150 | }; | |
69144e3b MR |
151 | }; |
152 | }; | |
153 | ||
7423d2d8 SR |
154 | memory { |
155 | reg = <0x40000000 0x80000000>; | |
156 | }; | |
874b4e45 | 157 | |
69144e3b MR |
158 | clocks { |
159 | #address-cells = <1>; | |
160 | #size-cells = <1>; | |
161 | ranges; | |
162 | ||
163 | /* | |
164 | * This is a dummy clock, to be used as placeholder on | |
165 | * other mux clocks when a specific parent clock is not | |
166 | * yet implemented. It should be dropped when the driver | |
167 | * is complete. | |
168 | */ | |
169 | dummy: dummy { | |
170 | #clock-cells = <0>; | |
171 | compatible = "fixed-clock"; | |
172 | clock-frequency = <0>; | |
173 | }; | |
174 | ||
dfb12c0c | 175 | osc24M: clk@01c20050 { |
69144e3b | 176 | #clock-cells = <0>; |
bf6534a1 | 177 | compatible = "allwinner,sun4i-a10-osc-clk"; |
69144e3b | 178 | reg = <0x01c20050 0x4>; |
92fd6e06 | 179 | clock-frequency = <24000000>; |
dfb12c0c | 180 | clock-output-names = "osc24M"; |
69144e3b MR |
181 | }; |
182 | ||
dfb12c0c | 183 | osc32k: clk@0 { |
69144e3b MR |
184 | #clock-cells = <0>; |
185 | compatible = "fixed-clock"; | |
186 | clock-frequency = <32768>; | |
dfb12c0c | 187 | clock-output-names = "osc32k"; |
69144e3b MR |
188 | }; |
189 | ||
dfb12c0c | 190 | pll1: clk@01c20000 { |
69144e3b | 191 | #clock-cells = <0>; |
bf6534a1 | 192 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
69144e3b MR |
193 | reg = <0x01c20000 0x4>; |
194 | clocks = <&osc24M>; | |
dfb12c0c | 195 | clock-output-names = "pll1"; |
69144e3b MR |
196 | }; |
197 | ||
dfb12c0c | 198 | pll4: clk@01c20018 { |
ec5589f7 | 199 | #clock-cells = <0>; |
bf6534a1 | 200 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
201 | reg = <0x01c20018 0x4>; |
202 | clocks = <&osc24M>; | |
dfb12c0c | 203 | clock-output-names = "pll4"; |
ec5589f7 EL |
204 | }; |
205 | ||
dfb12c0c | 206 | pll5: clk@01c20020 { |
c3e5e66b | 207 | #clock-cells = <1>; |
bf6534a1 | 208 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
209 | reg = <0x01c20020 0x4>; |
210 | clocks = <&osc24M>; | |
211 | clock-output-names = "pll5_ddr", "pll5_other"; | |
212 | }; | |
213 | ||
dfb12c0c | 214 | pll6: clk@01c20028 { |
c3e5e66b | 215 | #clock-cells = <1>; |
bf6534a1 | 216 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
217 | reg = <0x01c20028 0x4>; |
218 | clocks = <&osc24M>; | |
219 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
220 | }; | |
221 | ||
69144e3b MR |
222 | /* dummy is 200M */ |
223 | cpu: cpu@01c20054 { | |
224 | #clock-cells = <0>; | |
bf6534a1 | 225 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
69144e3b MR |
226 | reg = <0x01c20054 0x4>; |
227 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
dfb12c0c | 228 | clock-output-names = "cpu"; |
69144e3b MR |
229 | }; |
230 | ||
231 | axi: axi@01c20054 { | |
232 | #clock-cells = <0>; | |
bf6534a1 | 233 | compatible = "allwinner,sun4i-a10-axi-clk"; |
69144e3b MR |
234 | reg = <0x01c20054 0x4>; |
235 | clocks = <&cpu>; | |
dfb12c0c | 236 | clock-output-names = "axi"; |
69144e3b MR |
237 | }; |
238 | ||
dfb12c0c | 239 | axi_gates: clk@01c2005c { |
69144e3b | 240 | #clock-cells = <1>; |
bf6534a1 | 241 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
69144e3b MR |
242 | reg = <0x01c2005c 0x4>; |
243 | clocks = <&axi>; | |
244 | clock-output-names = "axi_dram"; | |
245 | }; | |
246 | ||
247 | ahb: ahb@01c20054 { | |
248 | #clock-cells = <0>; | |
bf6534a1 | 249 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
69144e3b MR |
250 | reg = <0x01c20054 0x4>; |
251 | clocks = <&axi>; | |
dfb12c0c | 252 | clock-output-names = "ahb"; |
69144e3b MR |
253 | }; |
254 | ||
dfb12c0c | 255 | ahb_gates: clk@01c20060 { |
69144e3b | 256 | #clock-cells = <1>; |
bf6534a1 | 257 | compatible = "allwinner,sun4i-a10-ahb-gates-clk"; |
69144e3b MR |
258 | reg = <0x01c20060 0x8>; |
259 | clocks = <&ahb>; | |
260 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
261 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
262 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
263 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
264 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
265 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
266 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
267 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
268 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
269 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
270 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
271 | }; | |
272 | ||
273 | apb0: apb0@01c20054 { | |
274 | #clock-cells = <0>; | |
bf6534a1 | 275 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
69144e3b MR |
276 | reg = <0x01c20054 0x4>; |
277 | clocks = <&ahb>; | |
dfb12c0c | 278 | clock-output-names = "apb0"; |
69144e3b MR |
279 | }; |
280 | ||
dfb12c0c | 281 | apb0_gates: clk@01c20068 { |
69144e3b | 282 | #clock-cells = <1>; |
bf6534a1 | 283 | compatible = "allwinner,sun4i-a10-apb0-gates-clk"; |
69144e3b MR |
284 | reg = <0x01c20068 0x4>; |
285 | clocks = <&apb0>; | |
286 | clock-output-names = "apb0_codec", "apb0_spdif", | |
287 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
288 | "apb0_ir1", "apb0_keypad"; | |
289 | }; | |
290 | ||
acbcc0f0 | 291 | apb1: clk@01c20058 { |
69144e3b | 292 | #clock-cells = <0>; |
bf6534a1 | 293 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
69144e3b | 294 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 295 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
dfb12c0c | 296 | clock-output-names = "apb1"; |
69144e3b MR |
297 | }; |
298 | ||
dfb12c0c | 299 | apb1_gates: clk@01c2006c { |
69144e3b | 300 | #clock-cells = <1>; |
bf6534a1 | 301 | compatible = "allwinner,sun4i-a10-apb1-gates-clk"; |
69144e3b MR |
302 | reg = <0x01c2006c 0x4>; |
303 | clocks = <&apb1>; | |
304 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
305 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
306 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
307 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
308 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
309 | "apb1_uart7"; | |
310 | }; | |
4b756ffb EL |
311 | |
312 | nand_clk: clk@01c20080 { | |
313 | #clock-cells = <0>; | |
bf6534a1 | 314 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
315 | reg = <0x01c20080 0x4>; |
316 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
317 | clock-output-names = "nand"; | |
318 | }; | |
319 | ||
320 | ms_clk: clk@01c20084 { | |
321 | #clock-cells = <0>; | |
bf6534a1 | 322 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
323 | reg = <0x01c20084 0x4>; |
324 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
325 | clock-output-names = "ms"; | |
326 | }; | |
327 | ||
328 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
329 | #clock-cells = <1>; |
330 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
331 | reg = <0x01c20088 0x4>; |
332 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
333 | clock-output-names = "mmc0", |
334 | "mmc0_output", | |
335 | "mmc0_sample"; | |
4b756ffb EL |
336 | }; |
337 | ||
338 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
339 | #clock-cells = <1>; |
340 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
341 | reg = <0x01c2008c 0x4>; |
342 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
343 | clock-output-names = "mmc1", |
344 | "mmc1_output", | |
345 | "mmc1_sample"; | |
4b756ffb EL |
346 | }; |
347 | ||
348 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
349 | #clock-cells = <1>; |
350 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
351 | reg = <0x01c20090 0x4>; |
352 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
353 | clock-output-names = "mmc2", |
354 | "mmc2_output", | |
355 | "mmc2_sample"; | |
4b756ffb EL |
356 | }; |
357 | ||
358 | mmc3_clk: clk@01c20094 { | |
d8c3a392 MR |
359 | #clock-cells = <1>; |
360 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
4b756ffb EL |
361 | reg = <0x01c20094 0x4>; |
362 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
363 | clock-output-names = "mmc3", |
364 | "mmc3_output", | |
365 | "mmc3_sample"; | |
4b756ffb EL |
366 | }; |
367 | ||
368 | ts_clk: clk@01c20098 { | |
369 | #clock-cells = <0>; | |
bf6534a1 | 370 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
371 | reg = <0x01c20098 0x4>; |
372 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
373 | clock-output-names = "ts"; | |
374 | }; | |
375 | ||
376 | ss_clk: clk@01c2009c { | |
377 | #clock-cells = <0>; | |
bf6534a1 | 378 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
379 | reg = <0x01c2009c 0x4>; |
380 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
381 | clock-output-names = "ss"; | |
382 | }; | |
383 | ||
384 | spi0_clk: clk@01c200a0 { | |
385 | #clock-cells = <0>; | |
bf6534a1 | 386 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
387 | reg = <0x01c200a0 0x4>; |
388 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
389 | clock-output-names = "spi0"; | |
390 | }; | |
391 | ||
392 | spi1_clk: clk@01c200a4 { | |
393 | #clock-cells = <0>; | |
bf6534a1 | 394 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
395 | reg = <0x01c200a4 0x4>; |
396 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
397 | clock-output-names = "spi1"; | |
398 | }; | |
399 | ||
400 | spi2_clk: clk@01c200a8 { | |
401 | #clock-cells = <0>; | |
bf6534a1 | 402 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
403 | reg = <0x01c200a8 0x4>; |
404 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
405 | clock-output-names = "spi2"; | |
406 | }; | |
407 | ||
408 | pata_clk: clk@01c200ac { | |
409 | #clock-cells = <0>; | |
bf6534a1 | 410 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
411 | reg = <0x01c200ac 0x4>; |
412 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
413 | clock-output-names = "pata"; | |
414 | }; | |
415 | ||
416 | ir0_clk: clk@01c200b0 { | |
417 | #clock-cells = <0>; | |
bf6534a1 | 418 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
419 | reg = <0x01c200b0 0x4>; |
420 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
421 | clock-output-names = "ir0"; | |
422 | }; | |
423 | ||
424 | ir1_clk: clk@01c200b4 { | |
425 | #clock-cells = <0>; | |
bf6534a1 | 426 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
427 | reg = <0x01c200b4 0x4>; |
428 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
429 | clock-output-names = "ir1"; | |
430 | }; | |
431 | ||
0076c8bd RB |
432 | usb_clk: clk@01c200cc { |
433 | #clock-cells = <1>; | |
8358aada | 434 | #reset-cells = <1>; |
0076c8bd RB |
435 | compatible = "allwinner,sun4i-a10-usb-clk"; |
436 | reg = <0x01c200cc 0x4>; | |
437 | clocks = <&pll6 1>; | |
d8cacaa3 MR |
438 | clock-output-names = "usb_ohci0", "usb_ohci1", |
439 | "usb_phy"; | |
0076c8bd RB |
440 | }; |
441 | ||
4b756ffb EL |
442 | spi3_clk: clk@01c200d4 { |
443 | #clock-cells = <0>; | |
bf6534a1 | 444 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
4b756ffb EL |
445 | reg = <0x01c200d4 0x4>; |
446 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
447 | clock-output-names = "spi3"; | |
448 | }; | |
69144e3b MR |
449 | }; |
450 | ||
6d92b80f HG |
451 | /* |
452 | * Note we use the address where the mmio registers start, not where | |
453 | * the SRAM blocks start, this cannot be changed because that would be | |
454 | * a devicetree ABI change. | |
455 | */ | |
b74aec1a | 456 | soc@01c00000 { |
69144e3b MR |
457 | compatible = "simple-bus"; |
458 | #address-cells = <1>; | |
459 | #size-cells = <1>; | |
69144e3b MR |
460 | ranges; |
461 | ||
6d92b80f HG |
462 | sram@00000000 { |
463 | compatible = "allwinner,sun4i-a10-sram"; | |
464 | reg = <0x00000000 0x4000>; | |
465 | allwinner,sram-name = "A1"; | |
466 | }; | |
467 | ||
468 | sram@00004000 { | |
469 | compatible = "allwinner,sun4i-a10-sram"; | |
470 | reg = <0x00004000 0x4000>; | |
471 | allwinner,sram-name = "A2"; | |
472 | }; | |
473 | ||
474 | sram@00008000 { | |
475 | compatible = "allwinner,sun4i-a10-sram"; | |
476 | reg = <0x00008000 0x4000>; | |
477 | allwinner,sram-name = "A3-A4"; | |
478 | }; | |
479 | ||
480 | sram@00010000 { | |
481 | compatible = "allwinner,sun4i-a10-sram"; | |
482 | reg = <0x00010000 0x1000>; | |
483 | allwinner,sram-name = "D"; | |
484 | }; | |
485 | ||
486 | sram-controller@01c00000 { | |
487 | compatible = "allwinner,sun4i-a10-sram-controller"; | |
488 | reg = <0x01c00000 0x30>; | |
489 | }; | |
490 | ||
1324f532 EL |
491 | dma: dma-controller@01c02000 { |
492 | compatible = "allwinner,sun4i-a10-dma"; | |
493 | reg = <0x01c02000 0x1000>; | |
494 | interrupts = <27>; | |
495 | clocks = <&ahb_gates 6>; | |
496 | #dma-cells = <2>; | |
497 | }; | |
498 | ||
65918e26 MR |
499 | spi0: spi@01c05000 { |
500 | compatible = "allwinner,sun4i-a10-spi"; | |
501 | reg = <0x01c05000 0x1000>; | |
502 | interrupts = <10>; | |
503 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
504 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
505 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
506 | <&dma SUN4I_DMA_DEDICATED 26>; | |
4192ff81 | 507 | dma-names = "rx", "tx"; |
65918e26 MR |
508 | status = "disabled"; |
509 | #address-cells = <1>; | |
510 | #size-cells = <0>; | |
511 | }; | |
512 | ||
513 | spi1: spi@01c06000 { | |
514 | compatible = "allwinner,sun4i-a10-spi"; | |
515 | reg = <0x01c06000 0x1000>; | |
516 | interrupts = <11>; | |
517 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
518 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
519 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
520 | <&dma SUN4I_DMA_DEDICATED 8>; | |
4192ff81 | 521 | dma-names = "rx", "tx"; |
65918e26 MR |
522 | status = "disabled"; |
523 | #address-cells = <1>; | |
524 | #size-cells = <0>; | |
525 | }; | |
526 | ||
e38afcb3 | 527 | emac: ethernet@01c0b000 { |
1c70e099 | 528 | compatible = "allwinner,sun4i-a10-emac"; |
e38afcb3 MR |
529 | reg = <0x01c0b000 0x1000>; |
530 | interrupts = <55>; | |
531 | clocks = <&ahb_gates 17>; | |
532 | status = "disabled"; | |
533 | }; | |
534 | ||
92395f56 | 535 | mdio: mdio@01c0b080 { |
1c70e099 | 536 | compatible = "allwinner,sun4i-a10-mdio"; |
e38afcb3 MR |
537 | reg = <0x01c0b080 0x14>; |
538 | status = "disabled"; | |
539 | #address-cells = <1>; | |
540 | #size-cells = <0>; | |
541 | }; | |
542 | ||
b258b369 DL |
543 | mmc0: mmc@01c0f000 { |
544 | compatible = "allwinner,sun4i-a10-mmc"; | |
545 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
546 | clocks = <&ahb_gates 8>, |
547 | <&mmc0_clk 0>, | |
548 | <&mmc0_clk 1>, | |
549 | <&mmc0_clk 2>; | |
550 | clock-names = "ahb", | |
551 | "mmc", | |
552 | "output", | |
553 | "sample"; | |
b258b369 DL |
554 | interrupts = <32>; |
555 | status = "disabled"; | |
4c1bb9c3 HG |
556 | #address-cells = <1>; |
557 | #size-cells = <0>; | |
b258b369 DL |
558 | }; |
559 | ||
560 | mmc1: mmc@01c10000 { | |
561 | compatible = "allwinner,sun4i-a10-mmc"; | |
562 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
563 | clocks = <&ahb_gates 9>, |
564 | <&mmc1_clk 0>, | |
565 | <&mmc1_clk 1>, | |
566 | <&mmc1_clk 2>; | |
567 | clock-names = "ahb", | |
568 | "mmc", | |
569 | "output", | |
570 | "sample"; | |
b258b369 DL |
571 | interrupts = <33>; |
572 | status = "disabled"; | |
4c1bb9c3 HG |
573 | #address-cells = <1>; |
574 | #size-cells = <0>; | |
b258b369 DL |
575 | }; |
576 | ||
577 | mmc2: mmc@01c11000 { | |
578 | compatible = "allwinner,sun4i-a10-mmc"; | |
579 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
580 | clocks = <&ahb_gates 10>, |
581 | <&mmc2_clk 0>, | |
582 | <&mmc2_clk 1>, | |
583 | <&mmc2_clk 2>; | |
584 | clock-names = "ahb", | |
585 | "mmc", | |
586 | "output", | |
587 | "sample"; | |
b258b369 DL |
588 | interrupts = <34>; |
589 | status = "disabled"; | |
4c1bb9c3 HG |
590 | #address-cells = <1>; |
591 | #size-cells = <0>; | |
b258b369 DL |
592 | }; |
593 | ||
594 | mmc3: mmc@01c12000 { | |
595 | compatible = "allwinner,sun4i-a10-mmc"; | |
596 | reg = <0x01c12000 0x1000>; | |
d8c3a392 MR |
597 | clocks = <&ahb_gates 11>, |
598 | <&mmc3_clk 0>, | |
599 | <&mmc3_clk 1>, | |
600 | <&mmc3_clk 2>; | |
601 | clock-names = "ahb", | |
602 | "mmc", | |
603 | "output", | |
604 | "sample"; | |
b258b369 DL |
605 | interrupts = <35>; |
606 | status = "disabled"; | |
4c1bb9c3 HG |
607 | #address-cells = <1>; |
608 | #size-cells = <0>; | |
b258b369 DL |
609 | }; |
610 | ||
6ab1ce24 RB |
611 | usbphy: phy@01c13400 { |
612 | #phy-cells = <1>; | |
613 | compatible = "allwinner,sun4i-a10-usb-phy"; | |
614 | reg = <0x01c13400 0x10 0x01c14800 0x4 0x01c1c800 0x4>; | |
615 | reg-names = "phy_ctrl", "pmu1", "pmu2"; | |
616 | clocks = <&usb_clk 8>; | |
617 | clock-names = "usb_phy"; | |
4dba4185 CYT |
618 | resets = <&usb_clk 0>, <&usb_clk 1>, <&usb_clk 2>; |
619 | reset-names = "usb0_reset", "usb1_reset", "usb2_reset"; | |
6ab1ce24 RB |
620 | status = "disabled"; |
621 | }; | |
622 | ||
623 | ehci0: usb@01c14000 { | |
624 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
625 | reg = <0x01c14000 0x100>; | |
626 | interrupts = <39>; | |
627 | clocks = <&ahb_gates 1>; | |
628 | phys = <&usbphy 1>; | |
629 | phy-names = "usb"; | |
630 | status = "disabled"; | |
631 | }; | |
632 | ||
633 | ohci0: usb@01c14400 { | |
634 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
635 | reg = <0x01c14400 0x100>; | |
636 | interrupts = <64>; | |
637 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
638 | phys = <&usbphy 1>; | |
639 | phy-names = "usb"; | |
640 | status = "disabled"; | |
641 | }; | |
642 | ||
65918e26 MR |
643 | spi2: spi@01c17000 { |
644 | compatible = "allwinner,sun4i-a10-spi"; | |
645 | reg = <0x01c17000 0x1000>; | |
646 | interrupts = <12>; | |
647 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
648 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
649 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
650 | <&dma SUN4I_DMA_DEDICATED 28>; | |
4192ff81 | 651 | dma-names = "rx", "tx"; |
65918e26 MR |
652 | status = "disabled"; |
653 | #address-cells = <1>; | |
654 | #size-cells = <0>; | |
655 | }; | |
656 | ||
248bd1e2 OS |
657 | ahci: sata@01c18000 { |
658 | compatible = "allwinner,sun4i-a10-ahci"; | |
659 | reg = <0x01c18000 0x1000>; | |
660 | interrupts = <56>; | |
661 | clocks = <&pll6 0>, <&ahb_gates 25>; | |
662 | status = "disabled"; | |
663 | }; | |
664 | ||
6ab1ce24 RB |
665 | ehci1: usb@01c1c000 { |
666 | compatible = "allwinner,sun4i-a10-ehci", "generic-ehci"; | |
667 | reg = <0x01c1c000 0x100>; | |
668 | interrupts = <40>; | |
669 | clocks = <&ahb_gates 3>; | |
670 | phys = <&usbphy 2>; | |
671 | phy-names = "usb"; | |
672 | status = "disabled"; | |
673 | }; | |
674 | ||
675 | ohci1: usb@01c1c400 { | |
676 | compatible = "allwinner,sun4i-a10-ohci", "generic-ohci"; | |
677 | reg = <0x01c1c400 0x100>; | |
678 | interrupts = <65>; | |
679 | clocks = <&usb_clk 7>, <&ahb_gates 4>; | |
680 | phys = <&usbphy 2>; | |
681 | phy-names = "usb"; | |
682 | status = "disabled"; | |
683 | }; | |
684 | ||
65918e26 MR |
685 | spi3: spi@01c1f000 { |
686 | compatible = "allwinner,sun4i-a10-spi"; | |
687 | reg = <0x01c1f000 0x1000>; | |
688 | interrupts = <50>; | |
689 | clocks = <&ahb_gates 23>, <&spi3_clk>; | |
690 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
691 | dmas = <&dma SUN4I_DMA_DEDICATED 31>, |
692 | <&dma SUN4I_DMA_DEDICATED 30>; | |
4192ff81 | 693 | dma-names = "rx", "tx"; |
65918e26 MR |
694 | status = "disabled"; |
695 | #address-cells = <1>; | |
696 | #size-cells = <0>; | |
697 | }; | |
698 | ||
69144e3b | 699 | intc: interrupt-controller@01c20400 { |
09504a7d | 700 | compatible = "allwinner,sun4i-a10-ic"; |
69144e3b MR |
701 | reg = <0x01c20400 0x400>; |
702 | interrupt-controller; | |
703 | #interrupt-cells = <1>; | |
704 | }; | |
705 | ||
e10911e1 | 706 | pio: pinctrl@01c20800 { |
874b4e45 MR |
707 | compatible = "allwinner,sun4i-a10-pinctrl"; |
708 | reg = <0x01c20800 0x400>; | |
39138bc6 | 709 | interrupts = <28>; |
36386d6e | 710 | clocks = <&apb0_gates 5>; |
e10911e1 | 711 | gpio-controller; |
39138bc6 | 712 | interrupt-controller; |
7d4ff96d | 713 | #interrupt-cells = <2>; |
874b4e45 | 714 | #size-cells = <0>; |
e10911e1 | 715 | #gpio-cells = <3>; |
581981be | 716 | |
1d5726e9 AB |
717 | pwm0_pins_a: pwm0@0 { |
718 | allwinner,pins = "PB2"; | |
719 | allwinner,function = "pwm"; | |
092a0c3b MR |
720 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
721 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
722 | }; |
723 | ||
724 | pwm1_pins_a: pwm1@0 { | |
725 | allwinner,pins = "PI3"; | |
726 | allwinner,function = "pwm"; | |
092a0c3b MR |
727 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
728 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
1d5726e9 AB |
729 | }; |
730 | ||
581981be MR |
731 | uart0_pins_a: uart0@0 { |
732 | allwinner,pins = "PB22", "PB23"; | |
733 | allwinner,function = "uart0"; | |
092a0c3b MR |
734 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
735 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
736 | }; |
737 | ||
738 | uart0_pins_b: uart0@1 { | |
739 | allwinner,pins = "PF2", "PF4"; | |
740 | allwinner,function = "uart0"; | |
092a0c3b MR |
741 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
742 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be MR |
743 | }; |
744 | ||
745 | uart1_pins_a: uart1@0 { | |
746 | allwinner,pins = "PA10", "PA11"; | |
747 | allwinner,function = "uart1"; | |
092a0c3b MR |
748 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
749 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
581981be | 750 | }; |
27cce4ff MR |
751 | |
752 | i2c0_pins_a: i2c0@0 { | |
753 | allwinner,pins = "PB0", "PB1"; | |
754 | allwinner,function = "i2c0"; | |
092a0c3b MR |
755 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
756 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
757 | }; |
758 | ||
759 | i2c1_pins_a: i2c1@0 { | |
760 | allwinner,pins = "PB18", "PB19"; | |
761 | allwinner,function = "i2c1"; | |
092a0c3b MR |
762 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
763 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff MR |
764 | }; |
765 | ||
766 | i2c2_pins_a: i2c2@0 { | |
767 | allwinner,pins = "PB20", "PB21"; | |
768 | allwinner,function = "i2c2"; | |
092a0c3b MR |
769 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
770 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
27cce4ff | 771 | }; |
496322bc | 772 | |
b21da664 MR |
773 | emac_pins_a: emac0@0 { |
774 | allwinner,pins = "PA0", "PA1", "PA2", | |
775 | "PA3", "PA4", "PA5", "PA6", | |
776 | "PA7", "PA8", "PA9", "PA10", | |
777 | "PA11", "PA12", "PA13", "PA14", | |
778 | "PA15", "PA16"; | |
779 | allwinner,function = "emac"; | |
092a0c3b MR |
780 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
781 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b21da664 | 782 | }; |
b5f86a3a HG |
783 | |
784 | mmc0_pins_a: mmc0@0 { | |
d8cacaa3 MR |
785 | allwinner,pins = "PF0", "PF1", "PF2", |
786 | "PF3", "PF4", "PF5"; | |
b5f86a3a | 787 | allwinner,function = "mmc0"; |
092a0c3b MR |
788 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
789 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
b5f86a3a HG |
790 | }; |
791 | ||
792 | mmc0_cd_pin_reference_design: mmc0_cd_pin@0 { | |
793 | allwinner,pins = "PH1"; | |
794 | allwinner,function = "gpio_in"; | |
092a0c3b MR |
795 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
796 | allwinner,pull = <SUN4I_PINCTRL_PULL_UP>; | |
b5f86a3a | 797 | }; |
a4e1099a | 798 | |
469a22e6 MC |
799 | ir0_rx_pins_a: ir0@0 { |
800 | allwinner,pins = "PB4"; | |
a4e1099a | 801 | allwinner,function = "ir0"; |
092a0c3b MR |
802 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
803 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a HG |
804 | }; |
805 | ||
469a22e6 MC |
806 | ir0_tx_pins_a: ir0@1 { |
807 | allwinner,pins = "PB3"; | |
808 | allwinner,function = "ir0"; | |
809 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
810 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
811 | }; | |
812 | ||
813 | ir1_rx_pins_a: ir1@0 { | |
814 | allwinner,pins = "PB23"; | |
815 | allwinner,function = "ir1"; | |
816 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
817 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
818 | }; | |
819 | ||
820 | ir1_tx_pins_a: ir1@1 { | |
821 | allwinner,pins = "PB22"; | |
a4e1099a | 822 | allwinner,function = "ir1"; |
092a0c3b MR |
823 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
824 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 825 | }; |
ec66d0bb AG |
826 | |
827 | spi0_pins_a: spi0@0 { | |
f3022c6c MR |
828 | allwinner,pins = "PI11", "PI12", "PI13"; |
829 | allwinner,function = "spi0"; | |
830 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
831 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
832 | }; | |
833 | ||
834 | spi0_cs0_pins_a: spi0_cs0@0 { | |
835 | allwinner,pins = "PI10"; | |
ec66d0bb | 836 | allwinner,function = "spi0"; |
092a0c3b MR |
837 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
838 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
839 | }; |
840 | ||
841 | spi1_pins_a: spi1@0 { | |
f3022c6c MR |
842 | allwinner,pins = "PI17", "PI18", "PI19"; |
843 | allwinner,function = "spi1"; | |
844 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
845 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
846 | }; | |
847 | ||
848 | spi1_cs0_pins_a: spi1_cs0@0 { | |
849 | allwinner,pins = "PI16"; | |
ec66d0bb | 850 | allwinner,function = "spi1"; |
092a0c3b MR |
851 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
852 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
853 | }; |
854 | ||
855 | spi2_pins_a: spi2@0 { | |
f3022c6c | 856 | allwinner,pins = "PC20", "PC21", "PC22"; |
ec66d0bb | 857 | allwinner,function = "spi2"; |
092a0c3b MR |
858 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
859 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb AG |
860 | }; |
861 | ||
862 | spi2_pins_b: spi2@1 { | |
f3022c6c MR |
863 | allwinner,pins = "PB15", "PB16", "PB17"; |
864 | allwinner,function = "spi2"; | |
865 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
866 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
867 | }; | |
868 | ||
869 | spi2_cs0_pins_a: spi2_cs0@0 { | |
870 | allwinner,pins = "PC19"; | |
871 | allwinner,function = "spi2"; | |
872 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
873 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
874 | }; | |
875 | ||
876 | spi2_cs0_pins_b: spi2_cs0@1 { | |
877 | allwinner,pins = "PB14"; | |
ec66d0bb | 878 | allwinner,function = "spi2"; |
092a0c3b MR |
879 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
880 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
ec66d0bb | 881 | }; |
1e8d1567 VP |
882 | |
883 | ps20_pins_a: ps20@0 { | |
884 | allwinner,pins = "PI20", "PI21"; | |
885 | allwinner,function = "ps2"; | |
886 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
887 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
888 | }; | |
889 | ||
890 | ps21_pins_a: ps21@0 { | |
891 | allwinner,pins = "PH12", "PH13"; | |
892 | allwinner,function = "ps2"; | |
893 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
894 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
a4e1099a | 895 | }; |
874b4e45 | 896 | }; |
89b3c99f | 897 | |
69144e3b | 898 | timer@01c20c00 { |
b4f26440 | 899 | compatible = "allwinner,sun4i-a10-timer"; |
69144e3b MR |
900 | reg = <0x01c20c00 0x90>; |
901 | interrupts = <22>; | |
902 | clocks = <&osc24M>; | |
903 | }; | |
904 | ||
905 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 906 | compatible = "allwinner,sun4i-a10-wdt"; |
69144e3b MR |
907 | reg = <0x01c20c90 0x10>; |
908 | }; | |
909 | ||
b5d905c7 | 910 | rtc: rtc@01c20d00 { |
5fc4bc89 | 911 | compatible = "allwinner,sun4i-a10-rtc"; |
b5d905c7 CC |
912 | reg = <0x01c20d00 0x20>; |
913 | interrupts = <24>; | |
914 | }; | |
915 | ||
4b57a395 AB |
916 | pwm: pwm@01c20e00 { |
917 | compatible = "allwinner,sun4i-a10-pwm"; | |
918 | reg = <0x01c20e00 0xc>; | |
919 | clocks = <&osc24M>; | |
920 | #pwm-cells = <3>; | |
921 | status = "disabled"; | |
922 | }; | |
923 | ||
a4e1099a HG |
924 | ir0: ir@01c21800 { |
925 | compatible = "allwinner,sun4i-a10-ir"; | |
926 | clocks = <&apb0_gates 6>, <&ir0_clk>; | |
927 | clock-names = "apb", "ir"; | |
928 | interrupts = <5>; | |
929 | reg = <0x01c21800 0x40>; | |
930 | status = "disabled"; | |
931 | }; | |
932 | ||
933 | ir1: ir@01c21c00 { | |
934 | compatible = "allwinner,sun4i-a10-ir"; | |
935 | clocks = <&apb0_gates 7>, <&ir1_clk>; | |
936 | clock-names = "apb", "ir"; | |
937 | interrupts = <6>; | |
938 | reg = <0x01c21c00 0x40>; | |
939 | status = "disabled"; | |
940 | }; | |
941 | ||
b0512e15 HG |
942 | lradc: lradc@01c22800 { |
943 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
944 | reg = <0x01c22800 0x100>; | |
945 | interrupts = <31>; | |
946 | status = "disabled"; | |
947 | }; | |
948 | ||
2bad969f | 949 | sid: eeprom@01c23800 { |
043d56ee | 950 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
951 | reg = <0x01c23800 0x10>; |
952 | }; | |
953 | ||
57c8839c | 954 | rtp: rtp@01c25000 { |
40dd8f3b | 955 | compatible = "allwinner,sun4i-a10-ts"; |
57c8839c HG |
956 | reg = <0x01c25000 0x100>; |
957 | interrupts = <29>; | |
41e7afb1 | 958 | #thermal-sensor-cells = <0>; |
57c8839c HG |
959 | }; |
960 | ||
89b3c99f MR |
961 | uart0: serial@01c28000 { |
962 | compatible = "snps,dw-apb-uart"; | |
963 | reg = <0x01c28000 0x400>; | |
964 | interrupts = <1>; | |
965 | reg-shift = <2>; | |
966 | reg-io-width = <4>; | |
9ff49ec7 | 967 | clocks = <&apb1_gates 16>; |
89b3c99f MR |
968 | status = "disabled"; |
969 | }; | |
76f14d0a | 970 | |
69144e3b MR |
971 | uart1: serial@01c28400 { |
972 | compatible = "snps,dw-apb-uart"; | |
973 | reg = <0x01c28400 0x400>; | |
974 | interrupts = <2>; | |
975 | reg-shift = <2>; | |
976 | reg-io-width = <4>; | |
977 | clocks = <&apb1_gates 17>; | |
978 | status = "disabled"; | |
979 | }; | |
980 | ||
76f14d0a MR |
981 | uart2: serial@01c28800 { |
982 | compatible = "snps,dw-apb-uart"; | |
983 | reg = <0x01c28800 0x400>; | |
984 | interrupts = <3>; | |
985 | reg-shift = <2>; | |
986 | reg-io-width = <4>; | |
9ff49ec7 | 987 | clocks = <&apb1_gates 18>; |
76f14d0a MR |
988 | status = "disabled"; |
989 | }; | |
990 | ||
69144e3b MR |
991 | uart3: serial@01c28c00 { |
992 | compatible = "snps,dw-apb-uart"; | |
993 | reg = <0x01c28c00 0x400>; | |
994 | interrupts = <4>; | |
995 | reg-shift = <2>; | |
996 | reg-io-width = <4>; | |
997 | clocks = <&apb1_gates 19>; | |
998 | status = "disabled"; | |
999 | }; | |
1000 | ||
76f14d0a MR |
1001 | uart4: serial@01c29000 { |
1002 | compatible = "snps,dw-apb-uart"; | |
1003 | reg = <0x01c29000 0x400>; | |
1004 | interrupts = <17>; | |
1005 | reg-shift = <2>; | |
1006 | reg-io-width = <4>; | |
9ff49ec7 | 1007 | clocks = <&apb1_gates 20>; |
76f14d0a MR |
1008 | status = "disabled"; |
1009 | }; | |
1010 | ||
1011 | uart5: serial@01c29400 { | |
1012 | compatible = "snps,dw-apb-uart"; | |
1013 | reg = <0x01c29400 0x400>; | |
1014 | interrupts = <18>; | |
1015 | reg-shift = <2>; | |
1016 | reg-io-width = <4>; | |
9ff49ec7 | 1017 | clocks = <&apb1_gates 21>; |
76f14d0a MR |
1018 | status = "disabled"; |
1019 | }; | |
1020 | ||
1021 | uart6: serial@01c29800 { | |
1022 | compatible = "snps,dw-apb-uart"; | |
1023 | reg = <0x01c29800 0x400>; | |
1024 | interrupts = <19>; | |
1025 | reg-shift = <2>; | |
1026 | reg-io-width = <4>; | |
9ff49ec7 | 1027 | clocks = <&apb1_gates 22>; |
76f14d0a MR |
1028 | status = "disabled"; |
1029 | }; | |
1030 | ||
1031 | uart7: serial@01c29c00 { | |
1032 | compatible = "snps,dw-apb-uart"; | |
1033 | reg = <0x01c29c00 0x400>; | |
1034 | interrupts = <20>; | |
1035 | reg-shift = <2>; | |
1036 | reg-io-width = <4>; | |
9ff49ec7 | 1037 | clocks = <&apb1_gates 23>; |
76f14d0a MR |
1038 | status = "disabled"; |
1039 | }; | |
f1741fda MR |
1040 | |
1041 | i2c0: i2c@01c2ac00 { | |
d275545e | 1042 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1043 | reg = <0x01c2ac00 0x400>; |
1044 | interrupts = <7>; | |
1045 | clocks = <&apb1_gates 0>; | |
f1741fda | 1046 | status = "disabled"; |
60bbe316 HG |
1047 | #address-cells = <1>; |
1048 | #size-cells = <0>; | |
f1741fda MR |
1049 | }; |
1050 | ||
1051 | i2c1: i2c@01c2b000 { | |
d275545e | 1052 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1053 | reg = <0x01c2b000 0x400>; |
1054 | interrupts = <8>; | |
1055 | clocks = <&apb1_gates 1>; | |
f1741fda | 1056 | status = "disabled"; |
60bbe316 HG |
1057 | #address-cells = <1>; |
1058 | #size-cells = <0>; | |
f1741fda MR |
1059 | }; |
1060 | ||
1061 | i2c2: i2c@01c2b400 { | |
d275545e | 1062 | compatible = "allwinner,sun4i-a10-i2c"; |
f1741fda MR |
1063 | reg = <0x01c2b400 0x400>; |
1064 | interrupts = <9>; | |
1065 | clocks = <&apb1_gates 2>; | |
f1741fda | 1066 | status = "disabled"; |
60bbe316 HG |
1067 | #address-cells = <1>; |
1068 | #size-cells = <0>; | |
f1741fda | 1069 | }; |
196654ae VP |
1070 | |
1071 | ps20: ps2@01c2a000 { | |
1072 | compatible = "allwinner,sun4i-a10-ps2"; | |
1073 | reg = <0x01c2a000 0x400>; | |
1074 | interrupts = <62>; | |
1075 | clocks = <&apb1_gates 6>; | |
1076 | status = "disabled"; | |
1077 | }; | |
1078 | ||
1079 | ps21: ps2@01c2a400 { | |
1080 | compatible = "allwinner,sun4i-a10-ps2"; | |
1081 | reg = <0x01c2a400 0x400>; | |
1082 | interrupts = <63>; | |
1083 | clocks = <&apb1_gates 7>; | |
1084 | status = "disabled"; | |
1085 | }; | |
874b4e45 | 1086 | }; |
7423d2d8 | 1087 | }; |