Commit | Line | Data |
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d3ae078e MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
71455701 | 14 | #include "skeleton.dtsi" |
d3ae078e | 15 | |
1f9f6a78 | 16 | #include <dt-bindings/dma/sun4i-a10.h> |
092a0c3b | 17 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
d3ae078e MR |
18 | |
19 | / { | |
20 | interrupt-parent = <&intc>; | |
21 | ||
e751cce9 EL |
22 | aliases { |
23 | ethernet0 = &emac; | |
24 | }; | |
25 | ||
d501841f HG |
26 | chosen { |
27 | #address-cells = <1>; | |
28 | #size-cells = <1>; | |
29 | ranges; | |
30 | ||
a9f8cda3 HG |
31 | framebuffer@0 { |
32 | compatible = "allwinner,simple-framebuffer", "simple-framebuffer"; | |
33 | allwinner,pipeline = "de_be0-lcd0-hdmi"; | |
678e75d3 HG |
34 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>, |
35 | <&ahb_gates 44>; | |
d501841f HG |
36 | status = "disabled"; |
37 | }; | |
fd18c7ea HG |
38 | |
39 | framebuffer@1 { | |
40 | compatible = "allwinner,simple-framebuffer", | |
41 | "simple-framebuffer"; | |
42 | allwinner,pipeline = "de_be0-lcd0"; | |
43 | clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>; | |
44 | status = "disabled"; | |
45 | }; | |
d501841f HG |
46 | }; |
47 | ||
d3ae078e MR |
48 | cpus { |
49 | cpu@0 { | |
50 | compatible = "arm,cortex-a8"; | |
51 | }; | |
52 | }; | |
53 | ||
54 | memory { | |
55 | reg = <0x40000000 0x20000000>; | |
56 | }; | |
57 | ||
58 | clocks { | |
59 | #address-cells = <1>; | |
60 | #size-cells = <1>; | |
61 | ranges; | |
62 | ||
63 | /* | |
64 | * This is a dummy clock, to be used as placeholder on | |
65 | * other mux clocks when a specific parent clock is not | |
66 | * yet implemented. It should be dropped when the driver | |
67 | * is complete. | |
68 | */ | |
69 | dummy: dummy { | |
70 | #clock-cells = <0>; | |
71 | compatible = "fixed-clock"; | |
72 | clock-frequency = <0>; | |
73 | }; | |
74 | ||
3dce8324 | 75 | osc24M: clk@01c20050 { |
d3ae078e | 76 | #clock-cells = <0>; |
bf6534a1 | 77 | compatible = "allwinner,sun4i-a10-osc-clk"; |
d3ae078e MR |
78 | reg = <0x01c20050 0x4>; |
79 | clock-frequency = <24000000>; | |
3dce8324 | 80 | clock-output-names = "osc24M"; |
d3ae078e MR |
81 | }; |
82 | ||
3dce8324 | 83 | osc32k: clk@0 { |
d3ae078e MR |
84 | #clock-cells = <0>; |
85 | compatible = "fixed-clock"; | |
86 | clock-frequency = <32768>; | |
3dce8324 | 87 | clock-output-names = "osc32k"; |
d3ae078e MR |
88 | }; |
89 | ||
3dce8324 | 90 | pll1: clk@01c20000 { |
d3ae078e | 91 | #clock-cells = <0>; |
bf6534a1 | 92 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
d3ae078e MR |
93 | reg = <0x01c20000 0x4>; |
94 | clocks = <&osc24M>; | |
3dce8324 | 95 | clock-output-names = "pll1"; |
d3ae078e MR |
96 | }; |
97 | ||
3dce8324 | 98 | pll4: clk@01c20018 { |
ec5589f7 | 99 | #clock-cells = <0>; |
bf6534a1 | 100 | compatible = "allwinner,sun4i-a10-pll1-clk"; |
ec5589f7 EL |
101 | reg = <0x01c20018 0x4>; |
102 | clocks = <&osc24M>; | |
3dce8324 | 103 | clock-output-names = "pll4"; |
ec5589f7 EL |
104 | }; |
105 | ||
3dce8324 | 106 | pll5: clk@01c20020 { |
c3e5e66b | 107 | #clock-cells = <1>; |
bf6534a1 | 108 | compatible = "allwinner,sun4i-a10-pll5-clk"; |
c3e5e66b EL |
109 | reg = <0x01c20020 0x4>; |
110 | clocks = <&osc24M>; | |
111 | clock-output-names = "pll5_ddr", "pll5_other"; | |
112 | }; | |
113 | ||
3dce8324 | 114 | pll6: clk@01c20028 { |
c3e5e66b | 115 | #clock-cells = <1>; |
bf6534a1 | 116 | compatible = "allwinner,sun4i-a10-pll6-clk"; |
c3e5e66b EL |
117 | reg = <0x01c20028 0x4>; |
118 | clocks = <&osc24M>; | |
119 | clock-output-names = "pll6_sata", "pll6_other", "pll6"; | |
120 | }; | |
121 | ||
d3ae078e MR |
122 | /* dummy is 200M */ |
123 | cpu: cpu@01c20054 { | |
124 | #clock-cells = <0>; | |
bf6534a1 | 125 | compatible = "allwinner,sun4i-a10-cpu-clk"; |
d3ae078e MR |
126 | reg = <0x01c20054 0x4>; |
127 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
3dce8324 | 128 | clock-output-names = "cpu"; |
d3ae078e MR |
129 | }; |
130 | ||
131 | axi: axi@01c20054 { | |
132 | #clock-cells = <0>; | |
bf6534a1 | 133 | compatible = "allwinner,sun4i-a10-axi-clk"; |
d3ae078e MR |
134 | reg = <0x01c20054 0x4>; |
135 | clocks = <&cpu>; | |
3dce8324 | 136 | clock-output-names = "axi"; |
d3ae078e MR |
137 | }; |
138 | ||
3dce8324 | 139 | axi_gates: clk@01c2005c { |
d3ae078e | 140 | #clock-cells = <1>; |
bf6534a1 | 141 | compatible = "allwinner,sun4i-a10-axi-gates-clk"; |
d3ae078e MR |
142 | reg = <0x01c2005c 0x4>; |
143 | clocks = <&axi>; | |
144 | clock-output-names = "axi_dram"; | |
145 | }; | |
146 | ||
147 | ahb: ahb@01c20054 { | |
148 | #clock-cells = <0>; | |
bf6534a1 | 149 | compatible = "allwinner,sun4i-a10-ahb-clk"; |
d3ae078e MR |
150 | reg = <0x01c20054 0x4>; |
151 | clocks = <&axi>; | |
3dce8324 | 152 | clock-output-names = "ahb"; |
d3ae078e MR |
153 | }; |
154 | ||
3dce8324 | 155 | ahb_gates: clk@01c20060 { |
d3ae078e | 156 | #clock-cells = <1>; |
29bb8054 | 157 | compatible = "allwinner,sun5i-a10s-ahb-gates-clk"; |
d3ae078e MR |
158 | reg = <0x01c20060 0x8>; |
159 | clocks = <&ahb>; | |
29bb8054 MR |
160 | clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci", |
161 | "ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0", | |
162 | "ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram", | |
163 | "ahb_emac", "ahb_ts", "ahb_spi0", "ahb_spi1", | |
164 | "ahb_spi2", "ahb_gps", "ahb_stimer", "ahb_ve", | |
165 | "ahb_tve", "ahb_lcd", "ahb_csi", "ahb_hdmi", | |
166 | "ahb_de_be", "ahb_de_fe", "ahb_iep", "ahb_mali400"; | |
d3ae078e MR |
167 | }; |
168 | ||
169 | apb0: apb0@01c20054 { | |
170 | #clock-cells = <0>; | |
bf6534a1 | 171 | compatible = "allwinner,sun4i-a10-apb0-clk"; |
d3ae078e MR |
172 | reg = <0x01c20054 0x4>; |
173 | clocks = <&ahb>; | |
3dce8324 | 174 | clock-output-names = "apb0"; |
d3ae078e MR |
175 | }; |
176 | ||
3dce8324 | 177 | apb0_gates: clk@01c20068 { |
d3ae078e | 178 | #clock-cells = <1>; |
29bb8054 | 179 | compatible = "allwinner,sun5i-a10s-apb0-gates-clk"; |
d3ae078e MR |
180 | reg = <0x01c20068 0x4>; |
181 | clocks = <&apb0>; | |
29bb8054 MR |
182 | clock-output-names = "apb0_codec", "apb0_iis", "apb0_pio", |
183 | "apb0_ir", "apb0_keypad"; | |
d3ae078e MR |
184 | }; |
185 | ||
acbcc0f0 | 186 | apb1: clk@01c20058 { |
d3ae078e | 187 | #clock-cells = <0>; |
bf6534a1 | 188 | compatible = "allwinner,sun4i-a10-apb1-clk"; |
d3ae078e | 189 | reg = <0x01c20058 0x4>; |
acbcc0f0 | 190 | clocks = <&osc24M>, <&pll6 1>, <&osc32k>; |
3dce8324 | 191 | clock-output-names = "apb1"; |
d3ae078e MR |
192 | }; |
193 | ||
3dce8324 | 194 | apb1_gates: clk@01c2006c { |
d3ae078e | 195 | #clock-cells = <1>; |
29bb8054 | 196 | compatible = "allwinner,sun5i-a10s-apb1-gates-clk"; |
d3ae078e MR |
197 | reg = <0x01c2006c 0x4>; |
198 | clocks = <&apb1>; | |
199 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
29bb8054 MR |
200 | "apb1_i2c2", "apb1_uart0", "apb1_uart1", |
201 | "apb1_uart2", "apb1_uart3"; | |
d3ae078e | 202 | }; |
8dc36bff EL |
203 | |
204 | nand_clk: clk@01c20080 { | |
205 | #clock-cells = <0>; | |
bf6534a1 | 206 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
207 | reg = <0x01c20080 0x4>; |
208 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
209 | clock-output-names = "nand"; | |
210 | }; | |
211 | ||
212 | ms_clk: clk@01c20084 { | |
213 | #clock-cells = <0>; | |
bf6534a1 | 214 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
215 | reg = <0x01c20084 0x4>; |
216 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
217 | clock-output-names = "ms"; | |
218 | }; | |
219 | ||
220 | mmc0_clk: clk@01c20088 { | |
d8c3a392 MR |
221 | #clock-cells = <1>; |
222 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
8dc36bff EL |
223 | reg = <0x01c20088 0x4>; |
224 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
225 | clock-output-names = "mmc0", |
226 | "mmc0_output", | |
227 | "mmc0_sample"; | |
8dc36bff EL |
228 | }; |
229 | ||
230 | mmc1_clk: clk@01c2008c { | |
d8c3a392 MR |
231 | #clock-cells = <1>; |
232 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
8dc36bff EL |
233 | reg = <0x01c2008c 0x4>; |
234 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
235 | clock-output-names = "mmc1", |
236 | "mmc1_output", | |
237 | "mmc1_sample"; | |
8dc36bff EL |
238 | }; |
239 | ||
240 | mmc2_clk: clk@01c20090 { | |
d8c3a392 MR |
241 | #clock-cells = <1>; |
242 | compatible = "allwinner,sun4i-a10-mmc-clk"; | |
8dc36bff EL |
243 | reg = <0x01c20090 0x4>; |
244 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
d8c3a392 MR |
245 | clock-output-names = "mmc2", |
246 | "mmc2_output", | |
247 | "mmc2_sample"; | |
8dc36bff EL |
248 | }; |
249 | ||
250 | ts_clk: clk@01c20098 { | |
251 | #clock-cells = <0>; | |
bf6534a1 | 252 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
253 | reg = <0x01c20098 0x4>; |
254 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
255 | clock-output-names = "ts"; | |
256 | }; | |
257 | ||
258 | ss_clk: clk@01c2009c { | |
259 | #clock-cells = <0>; | |
bf6534a1 | 260 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
261 | reg = <0x01c2009c 0x4>; |
262 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
263 | clock-output-names = "ss"; | |
264 | }; | |
265 | ||
266 | spi0_clk: clk@01c200a0 { | |
267 | #clock-cells = <0>; | |
bf6534a1 | 268 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
269 | reg = <0x01c200a0 0x4>; |
270 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
271 | clock-output-names = "spi0"; | |
272 | }; | |
273 | ||
274 | spi1_clk: clk@01c200a4 { | |
275 | #clock-cells = <0>; | |
bf6534a1 | 276 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
277 | reg = <0x01c200a4 0x4>; |
278 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
279 | clock-output-names = "spi1"; | |
280 | }; | |
281 | ||
282 | spi2_clk: clk@01c200a8 { | |
283 | #clock-cells = <0>; | |
bf6534a1 | 284 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
285 | reg = <0x01c200a8 0x4>; |
286 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
287 | clock-output-names = "spi2"; | |
288 | }; | |
289 | ||
290 | ir0_clk: clk@01c200b0 { | |
291 | #clock-cells = <0>; | |
bf6534a1 | 292 | compatible = "allwinner,sun4i-a10-mod0-clk"; |
8dc36bff EL |
293 | reg = <0x01c200b0 0x4>; |
294 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
295 | clock-output-names = "ir0"; | |
296 | }; | |
118c07ae | 297 | |
4c5d72f8 RB |
298 | usb_clk: clk@01c200cc { |
299 | #clock-cells = <1>; | |
300 | #reset-cells = <1>; | |
301 | compatible = "allwinner,sun5i-a13-usb-clk"; | |
302 | reg = <0x01c200cc 0x4>; | |
303 | clocks = <&pll6 1>; | |
304 | clock-output-names = "usb_ohci0", "usb_phy"; | |
305 | }; | |
306 | ||
118c07ae EL |
307 | mbus_clk: clk@01c2015c { |
308 | #clock-cells = <0>; | |
7868c5eb | 309 | compatible = "allwinner,sun5i-a13-mbus-clk"; |
118c07ae EL |
310 | reg = <0x01c2015c 0x4>; |
311 | clocks = <&osc24M>, <&pll6 1>, <&pll5 1>; | |
312 | clock-output-names = "mbus"; | |
313 | }; | |
d3ae078e MR |
314 | }; |
315 | ||
9e199292 | 316 | soc@01c00000 { |
d3ae078e MR |
317 | compatible = "simple-bus"; |
318 | #address-cells = <1>; | |
319 | #size-cells = <1>; | |
d3ae078e MR |
320 | ranges; |
321 | ||
6a5775e4 EL |
322 | dma: dma-controller@01c02000 { |
323 | compatible = "allwinner,sun4i-a10-dma"; | |
324 | reg = <0x01c02000 0x1000>; | |
325 | interrupts = <27>; | |
326 | clocks = <&ahb_gates 6>; | |
327 | #dma-cells = <2>; | |
328 | }; | |
329 | ||
8a689569 MR |
330 | spi0: spi@01c05000 { |
331 | compatible = "allwinner,sun4i-a10-spi"; | |
332 | reg = <0x01c05000 0x1000>; | |
333 | interrupts = <10>; | |
334 | clocks = <&ahb_gates 20>, <&spi0_clk>; | |
335 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
336 | dmas = <&dma SUN4I_DMA_DEDICATED 27>, |
337 | <&dma SUN4I_DMA_DEDICATED 26>; | |
fed4c5c6 | 338 | dma-names = "rx", "tx"; |
8a689569 MR |
339 | status = "disabled"; |
340 | #address-cells = <1>; | |
341 | #size-cells = <0>; | |
342 | }; | |
343 | ||
344 | spi1: spi@01c06000 { | |
345 | compatible = "allwinner,sun4i-a10-spi"; | |
346 | reg = <0x01c06000 0x1000>; | |
347 | interrupts = <11>; | |
348 | clocks = <&ahb_gates 21>, <&spi1_clk>; | |
349 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
350 | dmas = <&dma SUN4I_DMA_DEDICATED 9>, |
351 | <&dma SUN4I_DMA_DEDICATED 8>; | |
fed4c5c6 | 352 | dma-names = "rx", "tx"; |
8a689569 MR |
353 | status = "disabled"; |
354 | #address-cells = <1>; | |
355 | #size-cells = <0>; | |
356 | }; | |
357 | ||
d3ae078e | 358 | emac: ethernet@01c0b000 { |
1c70e099 | 359 | compatible = "allwinner,sun4i-a10-emac"; |
d3ae078e MR |
360 | reg = <0x01c0b000 0x1000>; |
361 | interrupts = <55>; | |
362 | clocks = <&ahb_gates 17>; | |
363 | status = "disabled"; | |
364 | }; | |
365 | ||
92395f56 | 366 | mdio: mdio@01c0b080 { |
1c70e099 | 367 | compatible = "allwinner,sun4i-a10-mdio"; |
d3ae078e MR |
368 | reg = <0x01c0b080 0x14>; |
369 | status = "disabled"; | |
370 | #address-cells = <1>; | |
371 | #size-cells = <0>; | |
372 | }; | |
373 | ||
d3aed1df DL |
374 | mmc0: mmc@01c0f000 { |
375 | compatible = "allwinner,sun5i-a13-mmc"; | |
376 | reg = <0x01c0f000 0x1000>; | |
d8c3a392 MR |
377 | clocks = <&ahb_gates 8>, |
378 | <&mmc0_clk 0>, | |
379 | <&mmc0_clk 1>, | |
380 | <&mmc0_clk 2>; | |
381 | clock-names = "ahb", | |
382 | "mmc", | |
383 | "output", | |
384 | "sample"; | |
d3aed1df DL |
385 | interrupts = <32>; |
386 | status = "disabled"; | |
387 | }; | |
388 | ||
389 | mmc1: mmc@01c10000 { | |
390 | compatible = "allwinner,sun5i-a13-mmc"; | |
391 | reg = <0x01c10000 0x1000>; | |
d8c3a392 MR |
392 | clocks = <&ahb_gates 9>, |
393 | <&mmc1_clk 0>, | |
394 | <&mmc1_clk 1>, | |
395 | <&mmc1_clk 2>; | |
396 | clock-names = "ahb", | |
397 | "mmc", | |
398 | "output", | |
399 | "sample"; | |
d3aed1df DL |
400 | interrupts = <33>; |
401 | status = "disabled"; | |
402 | }; | |
403 | ||
404 | mmc2: mmc@01c11000 { | |
405 | compatible = "allwinner,sun5i-a13-mmc"; | |
406 | reg = <0x01c11000 0x1000>; | |
d8c3a392 MR |
407 | clocks = <&ahb_gates 10>, |
408 | <&mmc2_clk 0>, | |
409 | <&mmc2_clk 1>, | |
410 | <&mmc2_clk 2>; | |
411 | clock-names = "ahb", | |
412 | "mmc", | |
413 | "output", | |
414 | "sample"; | |
d3aed1df DL |
415 | interrupts = <34>; |
416 | status = "disabled"; | |
417 | }; | |
418 | ||
06c7d52f RB |
419 | usbphy: phy@01c13400 { |
420 | #phy-cells = <1>; | |
421 | compatible = "allwinner,sun5i-a13-usb-phy"; | |
422 | reg = <0x01c13400 0x10 0x01c14800 0x4>; | |
423 | reg-names = "phy_ctrl", "pmu1"; | |
424 | clocks = <&usb_clk 8>; | |
425 | clock-names = "usb_phy"; | |
4dba4185 CYT |
426 | resets = <&usb_clk 0>, <&usb_clk 1>; |
427 | reset-names = "usb0_reset", "usb1_reset"; | |
06c7d52f RB |
428 | status = "disabled"; |
429 | }; | |
430 | ||
431 | ehci0: usb@01c14000 { | |
432 | compatible = "allwinner,sun5i-a10s-ehci", "generic-ehci"; | |
433 | reg = <0x01c14000 0x100>; | |
434 | interrupts = <39>; | |
435 | clocks = <&ahb_gates 1>; | |
436 | phys = <&usbphy 1>; | |
437 | phy-names = "usb"; | |
438 | status = "disabled"; | |
439 | }; | |
440 | ||
441 | ohci0: usb@01c14400 { | |
442 | compatible = "allwinner,sun5i-a10s-ohci", "generic-ohci"; | |
443 | reg = <0x01c14400 0x100>; | |
444 | interrupts = <40>; | |
445 | clocks = <&usb_clk 6>, <&ahb_gates 2>; | |
446 | phys = <&usbphy 1>; | |
447 | phy-names = "usb"; | |
448 | status = "disabled"; | |
449 | }; | |
450 | ||
8a689569 MR |
451 | spi2: spi@01c17000 { |
452 | compatible = "allwinner,sun4i-a10-spi"; | |
453 | reg = <0x01c17000 0x1000>; | |
454 | interrupts = <12>; | |
455 | clocks = <&ahb_gates 22>, <&spi2_clk>; | |
456 | clock-names = "ahb", "mod"; | |
1f9f6a78 MR |
457 | dmas = <&dma SUN4I_DMA_DEDICATED 29>, |
458 | <&dma SUN4I_DMA_DEDICATED 28>; | |
fed4c5c6 | 459 | dma-names = "rx", "tx"; |
8a689569 MR |
460 | status = "disabled"; |
461 | #address-cells = <1>; | |
462 | #size-cells = <0>; | |
463 | }; | |
464 | ||
d3ae078e | 465 | intc: interrupt-controller@01c20400 { |
09504a7d | 466 | compatible = "allwinner,sun4i-a10-ic"; |
d3ae078e MR |
467 | reg = <0x01c20400 0x400>; |
468 | interrupt-controller; | |
469 | #interrupt-cells = <1>; | |
470 | }; | |
471 | ||
472 | pio: pinctrl@01c20800 { | |
473 | compatible = "allwinner,sun5i-a10s-pinctrl"; | |
474 | reg = <0x01c20800 0x400>; | |
475 | interrupts = <28>; | |
476 | clocks = <&apb0_gates 5>; | |
477 | gpio-controller; | |
478 | interrupt-controller; | |
7d4ff96d | 479 | #interrupt-cells = <2>; |
d3ae078e MR |
480 | #size-cells = <0>; |
481 | #gpio-cells = <3>; | |
482 | ||
483 | uart0_pins_a: uart0@0 { | |
484 | allwinner,pins = "PB19", "PB20"; | |
485 | allwinner,function = "uart0"; | |
092a0c3b MR |
486 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
487 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
d3ae078e MR |
488 | }; |
489 | ||
490 | uart2_pins_a: uart2@0 { | |
491 | allwinner,pins = "PC18", "PC19"; | |
492 | allwinner,function = "uart2"; | |
092a0c3b MR |
493 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
494 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
d3ae078e MR |
495 | }; |
496 | ||
497 | uart3_pins_a: uart3@0 { | |
498 | allwinner,pins = "PG9", "PG10"; | |
499 | allwinner,function = "uart3"; | |
092a0c3b MR |
500 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
501 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
d3ae078e MR |
502 | }; |
503 | ||
504 | emac_pins_a: emac0@0 { | |
505 | allwinner,pins = "PA0", "PA1", "PA2", | |
506 | "PA3", "PA4", "PA5", "PA6", | |
507 | "PA7", "PA8", "PA9", "PA10", | |
508 | "PA11", "PA12", "PA13", "PA14", | |
509 | "PA15", "PA16"; | |
510 | allwinner,function = "emac"; | |
092a0c3b MR |
511 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
512 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
d3ae078e | 513 | }; |
170ab436 EL |
514 | |
515 | i2c0_pins_a: i2c0@0 { | |
516 | allwinner,pins = "PB0", "PB1"; | |
517 | allwinner,function = "i2c0"; | |
092a0c3b MR |
518 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
519 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
170ab436 EL |
520 | }; |
521 | ||
522 | i2c1_pins_a: i2c1@0 { | |
523 | allwinner,pins = "PB15", "PB16"; | |
524 | allwinner,function = "i2c1"; | |
092a0c3b MR |
525 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
526 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
170ab436 EL |
527 | }; |
528 | ||
529 | i2c2_pins_a: i2c2@0 { | |
530 | allwinner,pins = "PB17", "PB18"; | |
531 | allwinner,function = "i2c2"; | |
092a0c3b MR |
532 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; |
533 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
170ab436 | 534 | }; |
6da50f13 HG |
535 | |
536 | mmc0_pins_a: mmc0@0 { | |
537 | allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5"; | |
538 | allwinner,function = "mmc0"; | |
092a0c3b MR |
539 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
540 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
6da50f13 HG |
541 | }; |
542 | ||
543 | mmc1_pins_a: mmc1@0 { | |
544 | allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8"; | |
545 | allwinner,function = "mmc1"; | |
092a0c3b MR |
546 | allwinner,drive = <SUN4I_PINCTRL_30_MA>; |
547 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
6da50f13 | 548 | }; |
d3ae078e MR |
549 | }; |
550 | ||
551 | timer@01c20c00 { | |
b4f26440 | 552 | compatible = "allwinner,sun4i-a10-timer"; |
d3ae078e MR |
553 | reg = <0x01c20c00 0x90>; |
554 | interrupts = <22>; | |
555 | clocks = <&osc24M>; | |
556 | }; | |
557 | ||
558 | wdt: watchdog@01c20c90 { | |
ca5d04d9 | 559 | compatible = "allwinner,sun4i-a10-wdt"; |
d3ae078e MR |
560 | reg = <0x01c20c90 0x10>; |
561 | }; | |
562 | ||
ec011af5 HG |
563 | lradc: lradc@01c22800 { |
564 | compatible = "allwinner,sun4i-a10-lradc-keys"; | |
565 | reg = <0x01c22800 0x100>; | |
566 | interrupts = <31>; | |
567 | status = "disabled"; | |
568 | }; | |
569 | ||
2bad969f | 570 | sid: eeprom@01c23800 { |
043d56ee | 571 | compatible = "allwinner,sun4i-a10-sid"; |
2bad969f OS |
572 | reg = <0x01c23800 0x10>; |
573 | }; | |
574 | ||
f65c93a0 | 575 | rtp: rtp@01c25000 { |
40dd8f3b | 576 | compatible = "allwinner,sun4i-a10-ts"; |
f65c93a0 HG |
577 | reg = <0x01c25000 0x100>; |
578 | interrupts = <29>; | |
41e7afb1 | 579 | #thermal-sensor-cells = <0>; |
f65c93a0 HG |
580 | }; |
581 | ||
d3ae078e MR |
582 | uart0: serial@01c28000 { |
583 | compatible = "snps,dw-apb-uart"; | |
584 | reg = <0x01c28000 0x400>; | |
585 | interrupts = <1>; | |
586 | reg-shift = <2>; | |
587 | reg-io-width = <4>; | |
588 | clocks = <&apb1_gates 16>; | |
589 | status = "disabled"; | |
590 | }; | |
591 | ||
592 | uart1: serial@01c28400 { | |
593 | compatible = "snps,dw-apb-uart"; | |
594 | reg = <0x01c28400 0x400>; | |
595 | interrupts = <2>; | |
596 | reg-shift = <2>; | |
597 | reg-io-width = <4>; | |
598 | clocks = <&apb1_gates 17>; | |
599 | status = "disabled"; | |
600 | }; | |
601 | ||
602 | uart2: serial@01c28800 { | |
603 | compatible = "snps,dw-apb-uart"; | |
604 | reg = <0x01c28800 0x400>; | |
605 | interrupts = <3>; | |
606 | reg-shift = <2>; | |
607 | reg-io-width = <4>; | |
608 | clocks = <&apb1_gates 18>; | |
609 | status = "disabled"; | |
610 | }; | |
611 | ||
612 | uart3: serial@01c28c00 { | |
613 | compatible = "snps,dw-apb-uart"; | |
614 | reg = <0x01c28c00 0x400>; | |
615 | interrupts = <4>; | |
616 | reg-shift = <2>; | |
617 | reg-io-width = <4>; | |
618 | clocks = <&apb1_gates 19>; | |
619 | status = "disabled"; | |
620 | }; | |
ca3d4ed5 EL |
621 | |
622 | i2c0: i2c@01c2ac00 { | |
623 | #address-cells = <1>; | |
624 | #size-cells = <0>; | |
d275545e | 625 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
626 | reg = <0x01c2ac00 0x400>; |
627 | interrupts = <7>; | |
628 | clocks = <&apb1_gates 0>; | |
ca3d4ed5 EL |
629 | status = "disabled"; |
630 | }; | |
631 | ||
632 | i2c1: i2c@01c2b000 { | |
633 | #address-cells = <1>; | |
634 | #size-cells = <0>; | |
d275545e | 635 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
636 | reg = <0x01c2b000 0x400>; |
637 | interrupts = <8>; | |
638 | clocks = <&apb1_gates 1>; | |
ca3d4ed5 EL |
639 | status = "disabled"; |
640 | }; | |
641 | ||
642 | i2c2: i2c@01c2b400 { | |
643 | #address-cells = <1>; | |
644 | #size-cells = <0>; | |
d275545e | 645 | compatible = "allwinner,sun5i-a10s-i2c", "allwinner,sun4i-a10-i2c"; |
ca3d4ed5 EL |
646 | reg = <0x01c2b400 0x400>; |
647 | interrupts = <9>; | |
648 | clocks = <&apb1_gates 2>; | |
ca3d4ed5 EL |
649 | status = "disabled"; |
650 | }; | |
f2b50028 MR |
651 | |
652 | timer@01c60000 { | |
653 | compatible = "allwinner,sun5i-a13-hstimer"; | |
654 | reg = <0x01c60000 0x1000>; | |
655 | interrupts = <82>, <83>; | |
656 | clocks = <&ahb_gates 28>; | |
657 | }; | |
d3ae078e MR |
658 | }; |
659 | }; |