[deliverable/linux.git] / arch / arm / boot / dts / sun5i-a10s.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This library is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This library is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"

#include "sun5i.dtsi"

#include <dt-bindings/dma/sun4i-a10.h>
#include <dt-bindings/pinctrl/sun4i-a10.h>

/ {
	interrupt-parent = <&intc>;

	aliases {
		ethernet0 = &emac;
	};

	chosen {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		framebuffer@0 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0-hdmi";
			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
				 <&ahb_gates 44>;
			status = "disabled";
		};

		framebuffer@1 {
			compatible = "allwinner,simple-framebuffer",
				     "simple-framebuffer";
			allwinner,pipeline = "de_be0-lcd0";
			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
			status = "disabled";
		};
	};

	clocks {
		ahb_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb>;
			clock-output-names = "ahb_usbotg", "ahb_ehci",
					     "ahb_ohci", "ahb_ss", "ahb_dma",
					     "ahb_bist", "ahb_mmc0", "ahb_mmc1",
					     "ahb_mmc2", "ahb_nand",
					     "ahb_sdram", "ahb_emac", "ahb_ts",
					     "ahb_spi0", "ahb_spi1", "ahb_spi2",
					     "ahb_gps", "ahb_stimer", "ahb_ve",
					     "ahb_tve", "ahb_lcd", "ahb_csi",
					     "ahb_hdmi", "ahb_de_be",
					     "ahb_de_fe", "ahb_iep",
					     "ahb_mali400";
		};

		apb0_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb0>;
			clock-output-names = "apb0_codec", "apb0_iis",
					     "apb0_pio", "apb0_ir",
					     "apb0_keypad";
		};

		apb1_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_i2c0", "apb1_i2c1",
				"apb1_i2c2", "apb1_uart0", "apb1_uart1",
				"apb1_uart2", "apb1_uart3";
		};
	};

	soc@01c00000 {
		emac: ethernet@01c0b000 {
			compatible = "allwinner,sun4i-a10-emac";
			reg = <0x01c0b000 0x1000>;
			interrupts = <55>;
			clocks = <&ahb_gates 17>;
			allwinner,sram = <&emac_sram 1>;
			status = "disabled";
		};

		mdio: mdio@01c0b080 {
			compatible = "allwinner,sun4i-a10-mdio";
			reg = <0x01c0b080 0x14>;
			status = "disabled";
			#address-cells = <1>;
			#size-cells = <0>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 16>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <3>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb1_gates 18>;
			status = "disabled";
		};
	};
};

&pio {
	compatible = "allwinner,sun5i-a10s-pinctrl";

	uart0_pins_a: uart0@0 {
		allwinner,pins = "PB19", "PB20";
		allwinner,function = "uart0";
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};

	uart2_pins_a: uart2@0 {
		allwinner,pins = "PC18", "PC19";
		allwinner,function = "uart2";
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};

	uart3_pins_a: uart3@0 {
		allwinner,pins = "PG9", "PG10";
		allwinner,function = "uart3";
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};

	emac_pins_a: emac0@0 {
		allwinner,pins = "PA0", "PA1", "PA2",
				"PA3", "PA4", "PA5", "PA6",
				"PA7", "PA8", "PA9", "PA10",
				"PA11", "PA12", "PA13", "PA14",
				"PA15", "PA16";
		allwinner,function = "emac";
		allwinner,drive = <SUN4I_PINCTRL_10_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};

	mmc1_pins_a: mmc1@0 {
		allwinner,pins = "PG3", "PG4", "PG5",
				 "PG6", "PG7", "PG8";
		allwinner,function = "mmc1";
		allwinner,drive = <SUN4I_PINCTRL_30_MA>;
		allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	};
};

&sram_a {
	emac_sram: sram-section@8000 {
		compatible = "allwinner,sun4i-a10-sram-a3-a4";
		reg = <0x8000 0x4000>;
		status = "disabled";
	};
};
Commit	Line	Data
d3ae078e MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
1d86b4b5 MR	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
d3ae078e	10	*
1d86b4b5 MR	11	* a) This library is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This library is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
1d86b4b5 MR	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
d3ae078e MR	43	*/
d3ae078e MR	44
71455701	45	#include "skeleton.dtsi"
d3ae078e	46
903b2d75 MR	47	#include "sun5i.dtsi"
903b2d75 MR	48
1f9f6a78	49	#include <dt-bindings/dma/sun4i-a10.h>
092a0c3b	50	#include <dt-bindings/pinctrl/sun4i-a10.h>
d3ae078e MR	51
	52	/ {
	53	interrupt-parent = <&intc>;
	54
e751cce9 EL	55	aliases {
	56	ethernet0 = &emac;
	57	};
	58
d501841f HG	59	chosen {
	60	#address-cells = <1>;
	61	#size-cells = <1>;
	62	ranges;
	63
a9f8cda3	64	framebuffer@0 {
d8cacaa3 MR	65	compatible = "allwinner,simple-framebuffer",
d8cacaa3 MR	66	"simple-framebuffer";
a9f8cda3	67	allwinner,pipeline = "de_be0-lcd0-hdmi";
678e75d3 HG	68	clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 43>,
678e75d3 HG	69	<&ahb_gates 44>;
d501841f HG	70	status = "disabled";
d501841f HG	71	};
fd18c7ea HG	72
	73	framebuffer@1 {
	74	compatible = "allwinner,simple-framebuffer",
	75	"simple-framebuffer";
	76	allwinner,pipeline = "de_be0-lcd0";
	77	clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
	78	status = "disabled";
	79	};
d501841f HG	80	};
d501841f HG	81
d3ae078e	82	clocks {
3dce8324	83	ahb_gates: clk@01c20060 {
d3ae078e	84	#clock-cells = <1>;
29bb8054	85	compatible = "allwinner,sun5i-a10s-ahb-gates-clk";
d3ae078e MR	86	reg = <0x01c20060 0x8>;
d3ae078e MR	87	clocks = <&ahb>;
d8cacaa3 MR	88	clock-output-names = "ahb_usbotg", "ahb_ehci",
	89	"ahb_ohci", "ahb_ss", "ahb_dma",
	90	"ahb_bist", "ahb_mmc0", "ahb_mmc1",
	91	"ahb_mmc2", "ahb_nand",
	92	"ahb_sdram", "ahb_emac", "ahb_ts",
	93	"ahb_spi0", "ahb_spi1", "ahb_spi2",
	94	"ahb_gps", "ahb_stimer", "ahb_ve",
	95	"ahb_tve", "ahb_lcd", "ahb_csi",
	96	"ahb_hdmi", "ahb_de_be",
	97	"ahb_de_fe", "ahb_iep",
	98	"ahb_mali400";
d3ae078e MR	99	};
d3ae078e MR	100
3dce8324	101	apb0_gates: clk@01c20068 {
d3ae078e	102	#clock-cells = <1>;
29bb8054	103	compatible = "allwinner,sun5i-a10s-apb0-gates-clk";
d3ae078e MR	104	reg = <0x01c20068 0x4>;
d3ae078e MR	105	clocks = <&apb0>;
d8cacaa3 MR	106	clock-output-names = "apb0_codec", "apb0_iis",
	107	"apb0_pio", "apb0_ir",
	108	"apb0_keypad";
d3ae078e MR	109	};
d3ae078e MR	110
3dce8324	111	apb1_gates: clk@01c2006c {
d3ae078e	112	#clock-cells = <1>;
29bb8054	113	compatible = "allwinner,sun5i-a10s-apb1-gates-clk";
d3ae078e MR	114	reg = <0x01c2006c 0x4>;
	115	clocks = <&apb1>;
	116	clock-output-names = "apb1_i2c0", "apb1_i2c1",
29bb8054 MR	117	"apb1_i2c2", "apb1_uart0", "apb1_uart1",
29bb8054 MR	118	"apb1_uart2", "apb1_uart3";
d3ae078e MR	119	};
	120	};
	121
9e199292	122	soc@01c00000 {
d3ae078e	123	emac: ethernet@01c0b000 {
1c70e099	124	compatible = "allwinner,sun4i-a10-emac";
d3ae078e MR	125	reg = <0x01c0b000 0x1000>;
	126	interrupts = <55>;
	127	clocks = <&ahb_gates 17>;
00f69ba9	128	allwinner,sram = <&emac_sram 1>;
d3ae078e MR	129	status = "disabled";
	130	};
	131
92395f56	132	mdio: mdio@01c0b080 {
1c70e099	133	compatible = "allwinner,sun4i-a10-mdio";
d3ae078e MR	134	reg = <0x01c0b080 0x14>;
	135	status = "disabled";
	136	#address-cells = <1>;
	137	#size-cells = <0>;
	138	};
	139
d3ae078e MR	140	uart0: serial@01c28000 {
	141	compatible = "snps,dw-apb-uart";
	142	reg = <0x01c28000 0x400>;
	143	interrupts = <1>;
	144	reg-shift = <2>;
	145	reg-io-width = <4>;
	146	clocks = <&apb1_gates 16>;
	147	status = "disabled";
	148	};
	149
d3ae078e MR	150	uart2: serial@01c28800 {
	151	compatible = "snps,dw-apb-uart";
	152	reg = <0x01c28800 0x400>;
	153	interrupts = <3>;
	154	reg-shift = <2>;
	155	reg-io-width = <4>;
	156	clocks = <&apb1_gates 18>;
	157	status = "disabled";
	158	};
903b2d75 MR	159	};
903b2d75 MR	160	};
d3ae078e	161
903b2d75 MR	162	&pio {
903b2d75 MR	163	compatible = "allwinner,sun5i-a10s-pinctrl";
ca3d4ed5	164
903b2d75 MR	165	uart0_pins_a: uart0@0 {
	166	allwinner,pins = "PB19", "PB20";
	167	allwinner,function = "uart0";
	168	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	169	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	170	};
f2b50028	171
903b2d75 MR	172	uart2_pins_a: uart2@0 {
	173	allwinner,pins = "PC18", "PC19";
	174	allwinner,function = "uart2";
	175	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	176	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	177	};
	178
	179	uart3_pins_a: uart3@0 {
	180	allwinner,pins = "PG9", "PG10";
	181	allwinner,function = "uart3";
	182	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	183	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	184	};
	185
	186	emac_pins_a: emac0@0 {
	187	allwinner,pins = "PA0", "PA1", "PA2",
	188	"PA3", "PA4", "PA5", "PA6",
	189	"PA7", "PA8", "PA9", "PA10",
	190	"PA11", "PA12", "PA13", "PA14",
	191	"PA15", "PA16";
	192	allwinner,function = "emac";
	193	allwinner,drive = <SUN4I_PINCTRL_10_MA>;
	194	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
	195	};
	196
	197	mmc1_pins_a: mmc1@0 {
d8cacaa3 MR	198	allwinner,pins = "PG3", "PG4", "PG5",
d8cacaa3 MR	199	"PG6", "PG7", "PG8";
903b2d75 MR	200	allwinner,function = "mmc1";
	201	allwinner,drive = <SUN4I_PINCTRL_30_MA>;
	202	allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
d3ae078e MR	203	};
d3ae078e MR	204	};
00f69ba9 MR	205
	206	&sram_a {
	207	emac_sram: sram-section@8000 {
	208	compatible = "allwinner,sun4i-a10-sram-a3-a4";
	209	reg = <0x8000 0x4000>;
	210	status = "disabled";
	211	};
	212	};