Commit | Line | Data |
---|---|---|
d3ae078e MR |
1 | /* |
2 | * Copyright 2013 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
6 | * The code contained herein is licensed under the GNU General Public | |
7 | * License. You may obtain a copy of the GNU General Public License | |
8 | * Version 2 or later at the following locations: | |
9 | * | |
10 | * http://www.opensource.org/licenses/gpl-license.html | |
11 | * http://www.gnu.org/copyleft/gpl.html | |
12 | */ | |
13 | ||
14 | /include/ "skeleton.dtsi" | |
15 | ||
16 | / { | |
17 | interrupt-parent = <&intc>; | |
18 | ||
19 | cpus { | |
20 | cpu@0 { | |
21 | compatible = "arm,cortex-a8"; | |
22 | }; | |
23 | }; | |
24 | ||
25 | memory { | |
26 | reg = <0x40000000 0x20000000>; | |
27 | }; | |
28 | ||
29 | clocks { | |
30 | #address-cells = <1>; | |
31 | #size-cells = <1>; | |
32 | ranges; | |
33 | ||
34 | /* | |
35 | * This is a dummy clock, to be used as placeholder on | |
36 | * other mux clocks when a specific parent clock is not | |
37 | * yet implemented. It should be dropped when the driver | |
38 | * is complete. | |
39 | */ | |
40 | dummy: dummy { | |
41 | #clock-cells = <0>; | |
42 | compatible = "fixed-clock"; | |
43 | clock-frequency = <0>; | |
44 | }; | |
45 | ||
46 | osc24M: osc24M@01c20050 { | |
47 | #clock-cells = <0>; | |
48 | compatible = "allwinner,sun4i-osc-clk"; | |
49 | reg = <0x01c20050 0x4>; | |
50 | clock-frequency = <24000000>; | |
51 | }; | |
52 | ||
53 | osc32k: osc32k { | |
54 | #clock-cells = <0>; | |
55 | compatible = "fixed-clock"; | |
56 | clock-frequency = <32768>; | |
57 | }; | |
58 | ||
59 | pll1: pll1@01c20000 { | |
60 | #clock-cells = <0>; | |
61 | compatible = "allwinner,sun4i-pll1-clk"; | |
62 | reg = <0x01c20000 0x4>; | |
63 | clocks = <&osc24M>; | |
64 | }; | |
65 | ||
66 | /* dummy is 200M */ | |
67 | cpu: cpu@01c20054 { | |
68 | #clock-cells = <0>; | |
69 | compatible = "allwinner,sun4i-cpu-clk"; | |
70 | reg = <0x01c20054 0x4>; | |
71 | clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>; | |
72 | }; | |
73 | ||
74 | axi: axi@01c20054 { | |
75 | #clock-cells = <0>; | |
76 | compatible = "allwinner,sun4i-axi-clk"; | |
77 | reg = <0x01c20054 0x4>; | |
78 | clocks = <&cpu>; | |
79 | }; | |
80 | ||
81 | axi_gates: axi_gates@01c2005c { | |
82 | #clock-cells = <1>; | |
83 | compatible = "allwinner,sun4i-axi-gates-clk"; | |
84 | reg = <0x01c2005c 0x4>; | |
85 | clocks = <&axi>; | |
86 | clock-output-names = "axi_dram"; | |
87 | }; | |
88 | ||
89 | ahb: ahb@01c20054 { | |
90 | #clock-cells = <0>; | |
91 | compatible = "allwinner,sun4i-ahb-clk"; | |
92 | reg = <0x01c20054 0x4>; | |
93 | clocks = <&axi>; | |
94 | }; | |
95 | ||
96 | ahb_gates: ahb_gates@01c20060 { | |
97 | #clock-cells = <1>; | |
98 | compatible = "allwinner,sun4i-ahb-gates-clk"; | |
99 | reg = <0x01c20060 0x8>; | |
100 | clocks = <&ahb>; | |
101 | clock-output-names = "ahb_usb0", "ahb_ehci0", | |
102 | "ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss", | |
103 | "ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
104 | "ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand", | |
105 | "ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts", | |
106 | "ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3", | |
107 | "ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve", | |
108 | "ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0", | |
109 | "ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi", | |
110 | "ahb_de_be0", "ahb_de_be1", "ahb_de_fe0", | |
111 | "ahb_de_fe1", "ahb_mp", "ahb_mali400"; | |
112 | }; | |
113 | ||
114 | apb0: apb0@01c20054 { | |
115 | #clock-cells = <0>; | |
116 | compatible = "allwinner,sun4i-apb0-clk"; | |
117 | reg = <0x01c20054 0x4>; | |
118 | clocks = <&ahb>; | |
119 | }; | |
120 | ||
121 | apb0_gates: apb0_gates@01c20068 { | |
122 | #clock-cells = <1>; | |
123 | compatible = "allwinner,sun4i-apb0-gates-clk"; | |
124 | reg = <0x01c20068 0x4>; | |
125 | clocks = <&apb0>; | |
126 | clock-output-names = "apb0_codec", "apb0_spdif", | |
127 | "apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0", | |
128 | "apb0_ir1", "apb0_keypad"; | |
129 | }; | |
130 | ||
131 | /* dummy is pll62 */ | |
132 | apb1_mux: apb1_mux@01c20058 { | |
133 | #clock-cells = <0>; | |
134 | compatible = "allwinner,sun4i-apb1-mux-clk"; | |
135 | reg = <0x01c20058 0x4>; | |
136 | clocks = <&osc24M>, <&dummy>, <&osc32k>; | |
137 | }; | |
138 | ||
139 | apb1: apb1@01c20058 { | |
140 | #clock-cells = <0>; | |
141 | compatible = "allwinner,sun4i-apb1-clk"; | |
142 | reg = <0x01c20058 0x4>; | |
143 | clocks = <&apb1_mux>; | |
144 | }; | |
145 | ||
146 | apb1_gates: apb1_gates@01c2006c { | |
147 | #clock-cells = <1>; | |
148 | compatible = "allwinner,sun4i-apb1-gates-clk"; | |
149 | reg = <0x01c2006c 0x4>; | |
150 | clocks = <&apb1>; | |
151 | clock-output-names = "apb1_i2c0", "apb1_i2c1", | |
152 | "apb1_i2c2", "apb1_can", "apb1_scr", | |
153 | "apb1_ps20", "apb1_ps21", "apb1_uart0", | |
154 | "apb1_uart1", "apb1_uart2", "apb1_uart3", | |
155 | "apb1_uart4", "apb1_uart5", "apb1_uart6", | |
156 | "apb1_uart7"; | |
157 | }; | |
158 | }; | |
159 | ||
160 | soc@01c20000 { | |
161 | compatible = "simple-bus"; | |
162 | #address-cells = <1>; | |
163 | #size-cells = <1>; | |
164 | reg = <0x01c20000 0x300000>; | |
165 | ranges; | |
166 | ||
167 | emac: ethernet@01c0b000 { | |
168 | compatible = "allwinner,sun4i-emac"; | |
169 | reg = <0x01c0b000 0x1000>; | |
170 | interrupts = <55>; | |
171 | clocks = <&ahb_gates 17>; | |
172 | status = "disabled"; | |
173 | }; | |
174 | ||
175 | mdio@01c0b080 { | |
176 | compatible = "allwinner,sun4i-mdio"; | |
177 | reg = <0x01c0b080 0x14>; | |
178 | status = "disabled"; | |
179 | #address-cells = <1>; | |
180 | #size-cells = <0>; | |
181 | }; | |
182 | ||
183 | intc: interrupt-controller@01c20400 { | |
184 | compatible = "allwinner,sun4i-ic"; | |
185 | reg = <0x01c20400 0x400>; | |
186 | interrupt-controller; | |
187 | #interrupt-cells = <1>; | |
188 | }; | |
189 | ||
190 | pio: pinctrl@01c20800 { | |
191 | compatible = "allwinner,sun5i-a10s-pinctrl"; | |
192 | reg = <0x01c20800 0x400>; | |
193 | interrupts = <28>; | |
194 | clocks = <&apb0_gates 5>; | |
195 | gpio-controller; | |
196 | interrupt-controller; | |
197 | #address-cells = <1>; | |
198 | #size-cells = <0>; | |
199 | #gpio-cells = <3>; | |
200 | ||
201 | uart0_pins_a: uart0@0 { | |
202 | allwinner,pins = "PB19", "PB20"; | |
203 | allwinner,function = "uart0"; | |
204 | allwinner,drive = <0>; | |
205 | allwinner,pull = <0>; | |
206 | }; | |
207 | ||
208 | uart2_pins_a: uart2@0 { | |
209 | allwinner,pins = "PC18", "PC19"; | |
210 | allwinner,function = "uart2"; | |
211 | allwinner,drive = <0>; | |
212 | allwinner,pull = <0>; | |
213 | }; | |
214 | ||
215 | uart3_pins_a: uart3@0 { | |
216 | allwinner,pins = "PG9", "PG10"; | |
217 | allwinner,function = "uart3"; | |
218 | allwinner,drive = <0>; | |
219 | allwinner,pull = <0>; | |
220 | }; | |
221 | ||
222 | emac_pins_a: emac0@0 { | |
223 | allwinner,pins = "PA0", "PA1", "PA2", | |
224 | "PA3", "PA4", "PA5", "PA6", | |
225 | "PA7", "PA8", "PA9", "PA10", | |
226 | "PA11", "PA12", "PA13", "PA14", | |
227 | "PA15", "PA16"; | |
228 | allwinner,function = "emac"; | |
229 | allwinner,drive = <0>; | |
230 | allwinner,pull = <0>; | |
231 | }; | |
232 | }; | |
233 | ||
234 | timer@01c20c00 { | |
235 | compatible = "allwinner,sun4i-timer"; | |
236 | reg = <0x01c20c00 0x90>; | |
237 | interrupts = <22>; | |
238 | clocks = <&osc24M>; | |
239 | }; | |
240 | ||
241 | wdt: watchdog@01c20c90 { | |
242 | compatible = "allwinner,sun4i-wdt"; | |
243 | reg = <0x01c20c90 0x10>; | |
244 | }; | |
245 | ||
246 | uart0: serial@01c28000 { | |
247 | compatible = "snps,dw-apb-uart"; | |
248 | reg = <0x01c28000 0x400>; | |
249 | interrupts = <1>; | |
250 | reg-shift = <2>; | |
251 | reg-io-width = <4>; | |
252 | clocks = <&apb1_gates 16>; | |
253 | status = "disabled"; | |
254 | }; | |
255 | ||
256 | uart1: serial@01c28400 { | |
257 | compatible = "snps,dw-apb-uart"; | |
258 | reg = <0x01c28400 0x400>; | |
259 | interrupts = <2>; | |
260 | reg-shift = <2>; | |
261 | reg-io-width = <4>; | |
262 | clocks = <&apb1_gates 17>; | |
263 | status = "disabled"; | |
264 | }; | |
265 | ||
266 | uart2: serial@01c28800 { | |
267 | compatible = "snps,dw-apb-uart"; | |
268 | reg = <0x01c28800 0x400>; | |
269 | interrupts = <3>; | |
270 | reg-shift = <2>; | |
271 | reg-io-width = <4>; | |
272 | clocks = <&apb1_gates 18>; | |
273 | status = "disabled"; | |
274 | }; | |
275 | ||
276 | uart3: serial@01c28c00 { | |
277 | compatible = "snps,dw-apb-uart"; | |
278 | reg = <0x01c28c00 0x400>; | |
279 | interrupts = <4>; | |
280 | reg-shift = <2>; | |
281 | reg-io-width = <4>; | |
282 | clocks = <&apb1_gates 19>; | |
283 | status = "disabled"; | |
284 | }; | |
285 | }; | |
286 | }; |