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d4da2ebb MR |
1 | /* |
2 | * Copyright 2012 Maxime Ripard | |
3 | * | |
4 | * Maxime Ripard <maxime.ripard@free-electrons.com> | |
5 | * | |
1d86b4b5 MR |
6 | * This file is dual-licensed: you can use it either under the terms |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
d4da2ebb | 10 | * |
1d86b4b5 MR |
11 | * a) This library is free software; you can redistribute it and/or |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
16 | * This library is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
1d86b4b5 MR |
21 | * Or, alternatively, |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
d4da2ebb MR |
43 | */ |
44 | ||
71455701 | 45 | #include "skeleton.dtsi" |
d4da2ebb | 46 | |
51fbba42 | 47 | #include "sun5i.dtsi" |
32a5d2d1 | 48 | |
092a0c3b | 49 | #include <dt-bindings/pinctrl/sun4i-a10.h> |
51fbba42 | 50 | #include <dt-bindings/thermal/thermal.h> |
d4da2ebb MR |
51 | |
52 | / { | |
69144e3b MR |
53 | interrupt-parent = <&intc>; |
54 | ||
fd18c7ea HG |
55 | chosen { |
56 | #address-cells = <1>; | |
57 | #size-cells = <1>; | |
58 | ranges; | |
59 | ||
60 | framebuffer@0 { | |
61 | compatible = "allwinner,simple-framebuffer", | |
62 | "simple-framebuffer"; | |
63 | allwinner,pipeline = "de_be0-lcd0"; | |
6b709910 MR |
64 | clocks = <&ahb_gates 36>, <&ahb_gates 44>, <&de_be_clk>, |
65 | <&tcon_ch0_clk>, <&dram_gates 26>; | |
fd18c7ea HG |
66 | status = "disabled"; |
67 | }; | |
68 | }; | |
69 | ||
32a5d2d1 CYT |
70 | thermal-zones { |
71 | cpu_thermal { | |
72 | /* milliseconds */ | |
73 | polling-delay-passive = <250>; | |
74 | polling-delay = <1000>; | |
75 | thermal-sensors = <&rtp>; | |
76 | ||
77 | cooling-maps { | |
78 | map0 { | |
79 | trip = <&cpu_alert0>; | |
80 | cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; | |
81 | }; | |
82 | }; | |
83 | ||
84 | trips { | |
85 | cpu_alert0: cpu_alert0 { | |
86 | /* milliCelsius */ | |
87 | temperature = <850000>; | |
88 | hysteresis = <2000>; | |
89 | type = "passive"; | |
90 | }; | |
91 | ||
92 | cpu_crit: cpu_crit { | |
93 | /* milliCelsius */ | |
94 | temperature = <100000>; | |
95 | hysteresis = <2000>; | |
96 | type = "critical"; | |
97 | }; | |
98 | }; | |
69144e3b MR |
99 | }; |
100 | }; | |
101 | ||
69144e3b | 102 | clocks { |
3dce8324 | 103 | ahb_gates: clk@01c20060 { |
69144e3b | 104 | #clock-cells = <1>; |
70be4ee6 | 105 | compatible = "allwinner,sun5i-a13-ahb-gates-clk"; |
69144e3b MR |
106 | reg = <0x01c20060 0x8>; |
107 | clocks = <&ahb>; | |
dd4de433 MR |
108 | clock-indices = <0>, <1>, |
109 | <2>, <5>, <6>, | |
110 | <7>, <8>, <9>, | |
111 | <10>, <13>, | |
112 | <14>, <20>, | |
113 | <21>, <22>, | |
15bd920f MR |
114 | <28>, <32>, <34>, |
115 | <36>, <40>, <44>, | |
dd4de433 MR |
116 | <46>, <51>, |
117 | <52>; | |
d8cacaa3 MR |
118 | clock-output-names = "ahb_usbotg", "ahb_ehci", |
119 | "ahb_ohci", "ahb_ss", "ahb_dma", | |
120 | "ahb_bist", "ahb_mmc0", "ahb_mmc1", | |
121 | "ahb_mmc2", "ahb_nand", | |
122 | "ahb_sdram", "ahb_spi0", | |
123 | "ahb_spi1", "ahb_spi2", | |
15bd920f MR |
124 | "ahb_stimer", "ahb_ve", "ahb_tve", |
125 | "ahb_lcd", "ahb_csi", "ahb_de_be", | |
d8cacaa3 MR |
126 | "ahb_de_fe", "ahb_iep", |
127 | "ahb_mali400"; | |
69144e3b MR |
128 | }; |
129 | ||
3dce8324 | 130 | apb0_gates: clk@01c20068 { |
69144e3b | 131 | #clock-cells = <1>; |
70be4ee6 | 132 | compatible = "allwinner,sun5i-a13-apb0-gates-clk"; |
69144e3b MR |
133 | reg = <0x01c20068 0x4>; |
134 | clocks = <&apb0>; | |
dd4de433 MR |
135 | clock-indices = <0>, <5>, |
136 | <6>; | |
d8cacaa3 MR |
137 | clock-output-names = "apb0_codec", "apb0_pio", |
138 | "apb0_ir"; | |
69144e3b MR |
139 | }; |
140 | ||
3dce8324 | 141 | apb1_gates: clk@01c2006c { |
69144e3b | 142 | #clock-cells = <1>; |
70be4ee6 | 143 | compatible = "allwinner,sun5i-a13-apb1-gates-clk"; |
69144e3b MR |
144 | reg = <0x01c2006c 0x4>; |
145 | clocks = <&apb1>; | |
dd4de433 MR |
146 | clock-indices = <0>, <1>, |
147 | <2>, <17>, | |
148 | <19>; | |
69144e3b | 149 | clock-output-names = "apb1_i2c0", "apb1_i2c1", |
dd4de433 MR |
150 | "apb1_i2c2", "apb1_uart1", |
151 | "apb1_uart3"; | |
69144e3b | 152 | }; |
541ac155 MR |
153 | |
154 | dram_gates: clk@01c20100 { | |
155 | #clock-cells = <1>; | |
156 | compatible = "allwinner,sun5i-a13-dram-gates-clk", | |
157 | "allwinner,sun4i-a10-gates-clk"; | |
158 | reg = <0x01c20100 0x4>; | |
159 | clocks = <&pll5 0>; | |
160 | clock-indices = <0>, | |
161 | <1>, | |
162 | <25>, | |
163 | <26>, | |
164 | <29>, | |
165 | <31>; | |
166 | clock-output-names = "dram_ve", | |
167 | "dram_csi", | |
168 | "dram_de_fe", | |
169 | "dram_de_be", | |
170 | "dram_ace", | |
171 | "dram_iep"; | |
172 | }; | |
6b709910 MR |
173 | |
174 | de_be_clk: clk@01c20104 { | |
175 | #clock-cells = <0>; | |
176 | #reset-cells = <0>; | |
177 | compatible = "allwinner,sun4i-a10-display-clk"; | |
178 | reg = <0x01c20104 0x4>; | |
179 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
180 | clock-output-names = "de-be"; | |
181 | }; | |
182 | ||
183 | de_fe_clk: clk@01c2010c { | |
184 | #clock-cells = <0>; | |
185 | #reset-cells = <0>; | |
186 | compatible = "allwinner,sun4i-a10-display-clk"; | |
187 | reg = <0x01c2010c 0x4>; | |
188 | clocks = <&pll3>, <&pll7>, <&pll5 1>; | |
189 | clock-output-names = "de-fe"; | |
190 | }; | |
191 | ||
192 | tcon_ch0_clk: clk@01c20118 { | |
193 | #clock-cells = <0>; | |
194 | #reset-cells = <1>; | |
195 | compatible = "allwinner,sun4i-a10-tcon-ch0-clk"; | |
196 | reg = <0x01c20118 0x4>; | |
197 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
198 | clock-output-names = "tcon-ch0-sclk"; | |
199 | }; | |
200 | ||
201 | tcon_ch1_clk: clk@01c2012c { | |
202 | #clock-cells = <0>; | |
203 | compatible = "allwinner,sun4i-a10-tcon-ch1-clk"; | |
204 | reg = <0x01c2012c 0x4>; | |
205 | clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; | |
206 | clock-output-names = "tcon-ch1-sclk"; | |
207 | }; | |
69144e3b | 208 | }; |
51763bd7 | 209 | |
2cbc7295 MR |
210 | display-engine { |
211 | compatible = "allwinner,sun5i-a13-display-engine"; | |
212 | allwinner,pipelines = <&fe0>; | |
213 | }; | |
214 | ||
51763bd7 | 215 | soc@01c00000 { |
2cbc7295 MR |
216 | tcon0: lcd-controller@01c0c000 { |
217 | compatible = "allwinner,sun5i-a13-tcon"; | |
218 | reg = <0x01c0c000 0x1000>; | |
219 | interrupts = <44>; | |
220 | resets = <&tcon_ch0_clk 1>; | |
221 | reset-names = "lcd"; | |
222 | clocks = <&ahb_gates 36>, | |
223 | <&tcon_ch0_clk>, | |
224 | <&tcon_ch1_clk>; | |
225 | clock-names = "ahb", | |
226 | "tcon-ch0", | |
227 | "tcon-ch1"; | |
228 | clock-output-names = "tcon-pixel-clock"; | |
229 | status = "disabled"; | |
230 | ||
231 | ports { | |
232 | #address-cells = <1>; | |
233 | #size-cells = <0>; | |
234 | ||
235 | tcon0_in: port@0 { | |
236 | #address-cells = <1>; | |
237 | #size-cells = <0>; | |
238 | reg = <0>; | |
239 | ||
240 | tcon0_in_be0: endpoint@0 { | |
241 | reg = <0>; | |
242 | remote-endpoint = <&be0_out_tcon0>; | |
243 | }; | |
244 | }; | |
245 | ||
246 | tcon0_out: port@1 { | |
247 | #address-cells = <1>; | |
248 | #size-cells = <0>; | |
249 | reg = <1>; | |
250 | }; | |
251 | }; | |
252 | }; | |
253 | ||
51763bd7 HG |
254 | pwm: pwm@01c20e00 { |
255 | compatible = "allwinner,sun5i-a13-pwm"; | |
256 | reg = <0x01c20e00 0xc>; | |
257 | clocks = <&osc24M>; | |
258 | #pwm-cells = <3>; | |
259 | status = "disabled"; | |
260 | }; | |
2cbc7295 MR |
261 | |
262 | fe0: display-frontend@01e00000 { | |
263 | compatible = "allwinner,sun5i-a13-display-frontend"; | |
264 | reg = <0x01e00000 0x20000>; | |
265 | interrupts = <47>; | |
266 | clocks = <&ahb_gates 46>, <&de_fe_clk>, | |
267 | <&dram_gates 25>; | |
268 | clock-names = "ahb", "mod", | |
269 | "ram"; | |
270 | resets = <&de_fe_clk>; | |
271 | status = "disabled"; | |
272 | ||
273 | ports { | |
274 | #address-cells = <1>; | |
275 | #size-cells = <0>; | |
276 | ||
277 | fe0_out: port@1 { | |
278 | #address-cells = <1>; | |
279 | #size-cells = <0>; | |
280 | reg = <1>; | |
281 | ||
282 | fe0_out_be0: endpoint@0 { | |
283 | reg = <0>; | |
284 | remote-endpoint = <&be0_in_fe0>; | |
285 | }; | |
286 | }; | |
287 | }; | |
288 | }; | |
289 | ||
290 | be0: display-backend@01e60000 { | |
291 | compatible = "allwinner,sun5i-a13-display-backend"; | |
292 | reg = <0x01e60000 0x10000>; | |
293 | clocks = <&ahb_gates 44>, <&de_be_clk>, | |
294 | <&dram_gates 26>; | |
295 | clock-names = "ahb", "mod", | |
296 | "ram"; | |
297 | resets = <&de_be_clk>; | |
298 | status = "disabled"; | |
299 | ||
300 | assigned-clocks = <&de_be_clk>; | |
301 | assigned-clock-rates = <300000000>; | |
302 | ||
303 | ports { | |
304 | #address-cells = <1>; | |
305 | #size-cells = <0>; | |
306 | ||
307 | be0_in: port@0 { | |
308 | #address-cells = <1>; | |
309 | #size-cells = <0>; | |
310 | reg = <0>; | |
311 | ||
312 | be0_in_fe0: endpoint@0 { | |
313 | reg = <0>; | |
314 | remote-endpoint = <&fe0_out_be0>; | |
315 | }; | |
316 | }; | |
317 | ||
318 | be0_out: port@1 { | |
319 | #address-cells = <1>; | |
320 | #size-cells = <0>; | |
321 | reg = <1>; | |
322 | ||
323 | be0_out_tcon0: endpoint@0 { | |
324 | reg = <0>; | |
325 | remote-endpoint = <&tcon0_in_be0>; | |
326 | }; | |
327 | }; | |
328 | }; | |
329 | }; | |
51763bd7 | 330 | }; |
51fbba42 | 331 | }; |
69144e3b | 332 | |
51fbba42 MR |
333 | &cpu0 { |
334 | clock-latency = <244144>; /* 8 32k periods */ | |
335 | operating-points = < | |
8358aada | 336 | /* kHz uV */ |
51fbba42 | 337 | 1008000 1400000 |
8358aada MR |
338 | 912000 1350000 |
339 | 864000 1300000 | |
340 | 624000 1200000 | |
341 | 576000 1200000 | |
342 | 432000 1200000 | |
51fbba42 MR |
343 | >; |
344 | #cooling-cells = <2>; | |
345 | cooling-min-level = <0>; | |
346 | cooling-max-level = <5>; | |
347 | }; | |
69144e3b | 348 | |
51fbba42 MR |
349 | &pio { |
350 | compatible = "allwinner,sun5i-a13-pinctrl"; | |
f1741fda | 351 | |
0090dc5f MR |
352 | lcd_rgb666_pins: lcd_rgb666@0 { |
353 | allwinner,pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7", | |
354 | "PD10", "PD11", "PD12", "PD13", "PD14", "PD15", | |
355 | "PD18", "PD19", "PD20", "PD21", "PD22", "PD23", | |
356 | "PD24", "PD25", "PD26", "PD27"; | |
357 | allwinner,function = "lcd0"; | |
358 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
359 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
360 | }; | |
361 | ||
51fbba42 MR |
362 | uart1_pins_a: uart1@0 { |
363 | allwinner,pins = "PE10", "PE11"; | |
364 | allwinner,function = "uart1"; | |
365 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
366 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
367 | }; | |
4411902a | 368 | |
51fbba42 MR |
369 | uart1_pins_b: uart1@1 { |
370 | allwinner,pins = "PG3", "PG4"; | |
371 | allwinner,function = "uart1"; | |
372 | allwinner,drive = <SUN4I_PINCTRL_10_MA>; | |
373 | allwinner,pull = <SUN4I_PINCTRL_NO_PULL>; | |
9e2dcb2f | 374 | }; |
d4da2ebb | 375 | }; |