[deliverable/linux.git] / arch / arm / boot / dts / sun6i-a31.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		osc32k: osc32k {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		pll1: pll1@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
		};

		/*
		 * This is a dummy clock, to be used as placeholder on
		 * other mux clocks when a specific parent clock is not
		 * yet implemented. It should be dropped when the driver
		 * is complete.
		 */
		pll6: pll6 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		cpu: cpu@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-cpu-clk";
			reg = <0x01c20050 0x4>;

			/*
			 * PLL1 is listed twice here.
			 * While it looks suspicious, it's actually documented
			 * that way both in the datasheet and in the code from
			 * Allwinner.
			 */
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
		};

		axi: axi@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-axi-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&cpu>;
		};

		ahb1_mux: ahb1_mux@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
		};

		ahb1: ahb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1_mux>;
		};

		ahb1_gates: ahb1_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb1>;
			clock-output-names = "ahb1_mipidsi", "ahb1_ss",
					"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
					"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
					"ahb1_nand0", "ahb1_sdram",
					"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
					"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
					"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
					"ahb1_ehci1", "ahb1_ohci0",
					"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
					"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
					"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
					"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
					"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
					"ahb1_drc0", "ahb1_drc1";
		};

		apb1: apb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
		};

		apb1_gates: apb1_gates@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb1-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_codec", "apb1_digital_mic",
					"apb1_pio", "apb1_daudio0",
					"apb1_daudio1";
		};

		apb2_mux: apb2_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
		};

		apb2: apb2@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-apb2-div-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb2_mux>;
		};

		apb2_gates: apb2_gates@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb2-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb2>;
			clock-output-names = "apb2_i2c0", "apb2_i2c1",
					"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
					"apb2_uart1", "apb2_uart2", "apb2_uart3",
					"apb2_uart4", "apb2_uart5";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun6i-a31-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
			clocks = <&apb1_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PH20", "PH21";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <0 18 1>,
				     <0 19 1>,
				     <0 20 1>,
				     <0 21 1>,
				     <0 22 1>;
			clocks = <&osc24M>;
		};

		wdt1: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-wdt";
			reg = <0x01c20ca0 0x20>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 0 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 16>;
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 1 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 17>;
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 2 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 18>;
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 3 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 19>;
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 4 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 20>;
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 5 1>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 21>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};
	};
};
Commit	Line	Data
8aed3b31 MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
	19	cpus {
	20	#address-cells = <1>;
	21	#size-cells = <0>;
	22
	23	cpu@0 {
	24	compatible = "arm,cortex-a7";
	25	device_type = "cpu";
	26	reg = <0>;
	27	};
	28
	29	cpu@1 {
	30	compatible = "arm,cortex-a7";
	31	device_type = "cpu";
	32	reg = <1>;
	33	};
	34
	35	cpu@2 {
	36	compatible = "arm,cortex-a7";
	37	device_type = "cpu";
	38	reg = <2>;
	39	};
	40
	41	cpu@3 {
	42	compatible = "arm,cortex-a7";
	43	device_type = "cpu";
	44	reg = <3>;
	45	};
	46	};
	47
	48	memory {
	49	reg = <0x40000000 0x80000000>;
	50	};
	51
	52	clocks {
	53	#address-cells = <1>;
98096560 MR	54	#size-cells = <1>;
98096560 MR	55	ranges;
8aed3b31	56
98096560	57	osc24M: osc24M {
8aed3b31 MR	58	#clock-cells = <0>;
	59	compatible = "fixed-clock";
	60	clock-frequency = <24000000>;
	61	};
98096560 MR	62
	63	osc32k: osc32k {
	64	#clock-cells = <0>;
	65	compatible = "fixed-clock";
	66	clock-frequency = <32768>;
	67	};
	68
	69	pll1: pll1@01c20000 {
	70	#clock-cells = <0>;
	71	compatible = "allwinner,sun6i-a31-pll1-clk";
	72	reg = <0x01c20000 0x4>;
	73	clocks = <&osc24M>;
	74	};
	75
	76	/*
	77	* This is a dummy clock, to be used as placeholder on
	78	* other mux clocks when a specific parent clock is not
	79	* yet implemented. It should be dropped when the driver
	80	* is complete.
	81	*/
	82	pll6: pll6 {
	83	#clock-cells = <0>;
	84	compatible = "fixed-clock";
	85	clock-frequency = <0>;
	86	};
	87
	88	cpu: cpu@01c20050 {
	89	#clock-cells = <0>;
	90	compatible = "allwinner,sun4i-cpu-clk";
	91	reg = <0x01c20050 0x4>;
	92
	93	/*
	94	* PLL1 is listed twice here.
	95	* While it looks suspicious, it's actually documented
	96	* that way both in the datasheet and in the code from
	97	* Allwinner.
	98	*/
	99	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
	100	};
	101
	102	axi: axi@01c20050 {
	103	#clock-cells = <0>;
	104	compatible = "allwinner,sun4i-axi-clk";
	105	reg = <0x01c20050 0x4>;
	106	clocks = <&cpu>;
	107	};
	108
	109	ahb1_mux: ahb1_mux@01c20054 {
	110	#clock-cells = <0>;
	111	compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
	112	reg = <0x01c20054 0x4>;
	113	clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
	114	};
	115
	116	ahb1: ahb1@01c20054 {
	117	#clock-cells = <0>;
	118	compatible = "allwinner,sun4i-ahb-clk";
	119	reg = <0x01c20054 0x4>;
	120	clocks = <&ahb1_mux>;
	121	};
	122
	123	ahb1_gates: ahb1_gates@01c20060 {
	124	#clock-cells = <1>;
	125	compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
126	reg = <0x01c20060 0x8>;
127	clocks = <&ahb1>;
128	clock-output-names = "ahb1_mipidsi", "ahb1_ss",
129	"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
130	"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
131	"ahb1_nand0", "ahb1_sdram",
132	"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
133	"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
134	"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
135	"ahb1_ehci1", "ahb1_ohci0",
136	"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
137	"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
138	"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
139	"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
140	"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
141	"ahb1_drc0", "ahb1_drc1";
142	};
143
144	apb1: apb1@01c20054 {
145	#clock-cells = <0>;
146	compatible = "allwinner,sun4i-apb0-clk";
147	reg = <0x01c20054 0x4>;
148	clocks = <&ahb1>;
149	};
150
151	apb1_gates: apb1_gates@01c20060 {
152	#clock-cells = <1>;
153	compatible = "allwinner,sun6i-a31-apb1-gates-clk";
154	reg = <0x01c20068 0x4>;
155	clocks = <&apb1>;
156	clock-output-names = "apb1_codec", "apb1_digital_mic",
157	"apb1_pio", "apb1_daudio0",
158	"apb1_daudio1";
159	};
160
161	apb2_mux: apb2_mux@01c20058 {
162	#clock-cells = <0>;
163	compatible = "allwinner,sun4i-apb1-mux-clk";
164	reg = <0x01c20058 0x4>;
165	clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
166	};
167
168	apb2: apb2@01c20058 {
169	#clock-cells = <0>;
170	compatible = "allwinner,sun6i-a31-apb2-div-clk";
171	reg = <0x01c20058 0x4>;
172	clocks = <&apb2_mux>;
173	};
174
175	apb2_gates: apb2_gates@01c2006c {
176	#clock-cells = <1>;
177	compatible = "allwinner,sun6i-a31-apb2-gates-clk";
439d9f58	178	reg = <0x01c2006c 0x4>;
98096560 MR	179	clocks = <&apb2>;
	180	clock-output-names = "apb2_i2c0", "apb2_i2c1",
	181	"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
	182	"apb2_uart1", "apb2_uart2", "apb2_uart3",
	183	"apb2_uart4", "apb2_uart5";
	184	};
8aed3b31 MR	185	};
	186
	187	soc@01c00000 {
	188	compatible = "simple-bus";
	189	#address-cells = <1>;
	190	#size-cells = <1>;
	191	ranges;
	192
140e1721 MR	193	pio: pinctrl@01c20800 {
	194	compatible = "allwinner,sun6i-a31-pinctrl";
	195	reg = <0x01c20800 0x400>;
	196	interrupts = <0 11 1>, <0 15 1>, <0 16 1>, <0 17 1>;
98096560	197	clocks = <&apb1_gates 5>;
140e1721 MR	198	gpio-controller;
	199	interrupt-controller;
	200	#address-cells = <1>;
	201	#size-cells = <0>;
	202	#gpio-cells = <3>;
ab4238cd MR	203
	204	uart0_pins_a: uart0@0 {
	205	allwinner,pins = "PH20", "PH21";
	206	allwinner,function = "uart0";
	207	allwinner,drive = <0>;
	208	allwinner,pull = <0>;
	209	};
140e1721 MR	210	};
140e1721 MR	211
8aed3b31 MR	212	timer@01c20c00 {
	213	compatible = "allwinner,sun4i-timer";
	214	reg = <0x01c20c00 0xa0>;
	215	interrupts = <0 18 1>,
	216	<0 19 1>,
	217	<0 20 1>,
	218	<0 21 1>,
	219	<0 22 1>;
98096560	220	clocks = <&osc24M>;
8aed3b31 MR	221	};
	222
	223	wdt1: watchdog@01c20ca0 {
	224	compatible = "allwinner,sun6i-wdt";
	225	reg = <0x01c20ca0 0x20>;
	226	};
	227
	228	uart0: serial@01c28000 {
	229	compatible = "snps,dw-apb-uart";
	230	reg = <0x01c28000 0x400>;
	231	interrupts = <0 0 1>;
	232	reg-shift = <2>;
	233	reg-io-width = <4>;
98096560	234	clocks = <&apb2_gates 16>;
8aed3b31 MR	235	status = "disabled";
	236	};
	237
	238	uart1: serial@01c28400 {
	239	compatible = "snps,dw-apb-uart";
	240	reg = <0x01c28400 0x400>;
	241	interrupts = <0 1 1>;
	242	reg-shift = <2>;
	243	reg-io-width = <4>;
98096560	244	clocks = <&apb2_gates 17>;
8aed3b31 MR	245	status = "disabled";
	246	};
	247
	248	uart2: serial@01c28800 {
	249	compatible = "snps,dw-apb-uart";
	250	reg = <0x01c28800 0x400>;
	251	interrupts = <0 2 1>;
	252	reg-shift = <2>;
	253	reg-io-width = <4>;
98096560	254	clocks = <&apb2_gates 18>;
8aed3b31 MR	255	status = "disabled";
	256	};
	257
	258	uart3: serial@01c28c00 {
	259	compatible = "snps,dw-apb-uart";
	260	reg = <0x01c28c00 0x400>;
	261	interrupts = <0 3 1>;
	262	reg-shift = <2>;
	263	reg-io-width = <4>;
98096560	264	clocks = <&apb2_gates 19>;
8aed3b31 MR	265	status = "disabled";
	266	};
	267
	268	uart4: serial@01c29000 {
	269	compatible = "snps,dw-apb-uart";
	270	reg = <0x01c29000 0x400>;
	271	interrupts = <0 4 1>;
	272	reg-shift = <2>;
	273	reg-io-width = <4>;
98096560	274	clocks = <&apb2_gates 20>;
8aed3b31 MR	275	status = "disabled";
	276	};
	277
	278	uart5: serial@01c29400 {
	279	compatible = "snps,dw-apb-uart";
	280	reg = <0x01c29400 0x400>;
	281	interrupts = <0 5 1>;
	282	reg-shift = <2>;
	283	reg-io-width = <4>;
98096560	284	clocks = <&apb2_gates 21>;
8aed3b31 MR	285	status = "disabled";
	286	};
	287
	288	gic: interrupt-controller@01c81000 {
	289	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	290	reg = <0x01c81000 0x1000>,
	291	<0x01c82000 0x1000>,
	292	<0x01c84000 0x2000>,
	293	<0x01c86000 0x2000>;
	294	interrupt-controller;
	295	#interrupt-cells = <3>;
	296	interrupts = <1 9 0xf04>;
	297	};
	298	};
	299	};