[deliverable/linux.git] / arch / arm / boot / dts / sun6i-a31.dtsi

/*
 * Copyright 2013 Maxime Ripard
 *
 * Maxime Ripard <maxime.ripard@free-electrons.com>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/include/ "skeleton.dtsi"

/ {
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
	};


	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <0>;
		};

		cpu@1 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <1>;
		};

		cpu@2 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <2>;
		};

		cpu@3 {
			compatible = "arm,cortex-a7";
			device_type = "cpu";
			reg = <3>;
		};
	};

	memory {
		reg = <0x40000000 0x80000000>;
	};

	pmu {
		compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
		interrupts = <0 120 4>,
			     <0 121 4>,
			     <0 122 4>,
			     <0 123 4>;
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		osc24M: osc24M {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		osc32k: clk@0 {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
			clock-output-names = "osc32k";
		};

		pll1: clk@01c20000 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll1-clk";
			reg = <0x01c20000 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll1";
		};

		pll6: clk@01c20028 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-pll6-clk";
			reg = <0x01c20028 0x4>;
			clocks = <&osc24M>;
			clock-output-names = "pll6";
		};

		cpu: cpu@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-cpu-clk";
			reg = <0x01c20050 0x4>;

			/*
			 * PLL1 is listed twice here.
			 * While it looks suspicious, it's actually documented
			 * that way both in the datasheet and in the code from
			 * Allwinner.
			 */
			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
			clock-output-names = "cpu";
		};

		axi: axi@01c20050 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-axi-clk";
			reg = <0x01c20050 0x4>;
			clocks = <&cpu>;
			clock-output-names = "axi";
		};

		ahb1_mux: ahb1_mux@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
			clock-output-names = "ahb1_mux";
		};

		ahb1: ahb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-ahb-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1_mux>;
			clock-output-names = "ahb1";
		};

		ahb1_gates: clk@01c20060 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
			reg = <0x01c20060 0x8>;
			clocks = <&ahb1>;
			clock-output-names = "ahb1_mipidsi", "ahb1_ss",
					"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
					"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
					"ahb1_nand0", "ahb1_sdram",
					"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
					"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
					"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
					"ahb1_ehci1", "ahb1_ohci0",
					"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
					"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
					"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
					"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
					"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
					"ahb1_drc0", "ahb1_drc1";
		};

		apb1: apb1@01c20054 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb0-clk";
			reg = <0x01c20054 0x4>;
			clocks = <&ahb1>;
			clock-output-names = "apb1";
		};

		apb1_gates: clk@01c20068 {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb1-gates-clk";
			reg = <0x01c20068 0x4>;
			clocks = <&apb1>;
			clock-output-names = "apb1_codec", "apb1_digital_mic",
					"apb1_pio", "apb1_daudio0",
					"apb1_daudio1";
		};

		apb2_mux: apb2_mux@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-apb1-mux-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
			clock-output-names = "apb2_mux";
		};

		apb2: apb2@01c20058 {
			#clock-cells = <0>;
			compatible = "allwinner,sun6i-a31-apb2-div-clk";
			reg = <0x01c20058 0x4>;
			clocks = <&apb2_mux>;
			clock-output-names = "apb2";
		};

		apb2_gates: clk@01c2006c {
			#clock-cells = <1>;
			compatible = "allwinner,sun6i-a31-apb2-gates-clk";
			reg = <0x01c2006c 0x4>;
			clocks = <&apb2>;
			clock-output-names = "apb2_i2c0", "apb2_i2c1",
					"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
					"apb2_uart1", "apb2_uart2", "apb2_uart3",
					"apb2_uart4", "apb2_uart5";
		};

		spi0_clk: clk@01c200a0 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a0 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi0";
		};

		spi1_clk: clk@01c200a4 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a4 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi1";
		};

		spi2_clk: clk@01c200a8 {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200a8 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi2";
		};

		spi3_clk: clk@01c200ac {
			#clock-cells = <0>;
			compatible = "allwinner,sun4i-a10-mod0-clk";
			reg = <0x01c200ac 0x4>;
			clocks = <&osc24M>, <&pll6>;
			clock-output-names = "spi3";
		};
	};

	soc@01c00000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		dma: dma-controller@01c02000 {
			compatible = "allwinner,sun6i-a31-dma";
			reg = <0x01c02000 0x1000>;
			interrupts = <0 50 4>;
			clocks = <&ahb1_gates 6>;
			resets = <&ahb1_rst 6>;
			#dma-cells = <1>;
		};

		pio: pinctrl@01c20800 {
			compatible = "allwinner,sun6i-a31-pinctrl";
			reg = <0x01c20800 0x400>;
			interrupts = <0 11 4>,
				     <0 15 4>,
				     <0 16 4>,
				     <0 17 4>;
			clocks = <&apb1_gates 5>;
			gpio-controller;
			interrupt-controller;
			#address-cells = <1>;
			#size-cells = <0>;
			#gpio-cells = <3>;

			uart0_pins_a: uart0@0 {
				allwinner,pins = "PH20", "PH21";
				allwinner,function = "uart0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c0_pins_a: i2c0@0 {
				allwinner,pins = "PH14", "PH15";
				allwinner,function = "i2c0";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c1_pins_a: i2c1@0 {
				allwinner,pins = "PH16", "PH17";
				allwinner,function = "i2c1";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			i2c2_pins_a: i2c2@0 {
				allwinner,pins = "PH18", "PH19";
				allwinner,function = "i2c2";
				allwinner,drive = <0>;
				allwinner,pull = <0>;
			};

			mmc0_pins_a: mmc0@0 {
				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
				allwinner,function = "mmc0";
				allwinner,drive = <2>;
				allwinner,pull = <0>;
			};
		};

		ahb1_rst: reset@01c202c0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-ahb1-reset";
			reg = <0x01c202c0 0xc>;
		};

		apb1_rst: reset@01c202d0 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d0 0x4>;
		};

		apb2_rst: reset@01c202d8 {
			#reset-cells = <1>;
			compatible = "allwinner,sun6i-a31-clock-reset";
			reg = <0x01c202d8 0x4>;
		};

		timer@01c20c00 {
			compatible = "allwinner,sun4i-a10-timer";
			reg = <0x01c20c00 0xa0>;
			interrupts = <0 18 4>,
				     <0 19 4>,
				     <0 20 4>,
				     <0 21 4>,
				     <0 22 4>;
			clocks = <&osc24M>;
		};

		wdt1: watchdog@01c20ca0 {
			compatible = "allwinner,sun6i-a31-wdt";
			reg = <0x01c20ca0 0x20>;
		};

		uart0: serial@01c28000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28000 0x400>;
			interrupts = <0 0 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 16>;
			resets = <&apb2_rst 16>;
			dmas = <&dma 6>, <&dma 6>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart1: serial@01c28400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28400 0x400>;
			interrupts = <0 1 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 17>;
			resets = <&apb2_rst 17>;
			dmas = <&dma 7>, <&dma 7>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart2: serial@01c28800 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28800 0x400>;
			interrupts = <0 2 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 18>;
			resets = <&apb2_rst 18>;
			dmas = <&dma 8>, <&dma 8>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart3: serial@01c28c00 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c28c00 0x400>;
			interrupts = <0 3 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 19>;
			resets = <&apb2_rst 19>;
			dmas = <&dma 9>, <&dma 9>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart4: serial@01c29000 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29000 0x400>;
			interrupts = <0 4 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 20>;
			resets = <&apb2_rst 20>;
			dmas = <&dma 10>, <&dma 10>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		uart5: serial@01c29400 {
			compatible = "snps,dw-apb-uart";
			reg = <0x01c29400 0x400>;
			interrupts = <0 5 4>;
			reg-shift = <2>;
			reg-io-width = <4>;
			clocks = <&apb2_gates 21>;
			resets = <&apb2_rst 21>;
			dmas = <&dma 22>, <&dma 22>;
			dma-names = "rx", "tx";
			status = "disabled";
		};

		i2c0: i2c@01c2ac00 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2ac00 0x400>;
			interrupts = <0 6 4>;
			clocks = <&apb2_gates 0>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 0>;
			status = "disabled";
		};

		i2c1: i2c@01c2b000 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b000 0x400>;
			interrupts = <0 7 4>;
			clocks = <&apb2_gates 1>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 1>;
			status = "disabled";
		};

		i2c2: i2c@01c2b400 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b400 0x400>;
			interrupts = <0 8 4>;
			clocks = <&apb2_gates 2>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 2>;
			status = "disabled";
		};

		i2c3: i2c@01c2b800 {
			compatible = "allwinner,sun6i-a31-i2c";
			reg = <0x01c2b800 0x400>;
			interrupts = <0 9 4>;
			clocks = <&apb2_gates 3>;
			clock-frequency = <100000>;
			resets = <&apb2_rst 3>;
			status = "disabled";
		};

		spi0: spi@01c68000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c68000 0x1000>;
			interrupts = <0 65 4>;
			clocks = <&ahb1_gates 20>, <&spi0_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma 23>, <&dma 23>;
			dma-names = "rx", "tx";
			resets = <&ahb1_rst 20>;
			status = "disabled";
		};

		spi1: spi@01c69000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c69000 0x1000>;
			interrupts = <0 66 4>;
			clocks = <&ahb1_gates 21>, <&spi1_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma 24>, <&dma 24>;
			dma-names = "rx", "tx";
			resets = <&ahb1_rst 21>;
			status = "disabled";
		};

		spi2: spi@01c6a000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c6a000 0x1000>;
			interrupts = <0 67 4>;
			clocks = <&ahb1_gates 22>, <&spi2_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma 25>, <&dma 25>;
			dma-names = "rx", "tx";
			resets = <&ahb1_rst 22>;
			status = "disabled";
		};

		spi3: spi@01c6b000 {
			compatible = "allwinner,sun6i-a31-spi";
			reg = <0x01c6b000 0x1000>;
			interrupts = <0 68 4>;
			clocks = <&ahb1_gates 23>, <&spi3_clk>;
			clock-names = "ahb", "mod";
			dmas = <&dma 26>, <&dma 26>;
			dma-names = "rx", "tx";
			resets = <&ahb1_rst 23>;
			status = "disabled";
		};

		gic: interrupt-controller@01c81000 {
			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
			reg = <0x01c81000 0x1000>,
			      <0x01c82000 0x1000>,
			      <0x01c84000 0x2000>,
			      <0x01c86000 0x2000>;
			interrupt-controller;
			#interrupt-cells = <3>;
			interrupts = <1 9 0xf04>;
		};

		nmi_intc: interrupt-controller@01f00c0c {
			compatible = "allwinner,sun6i-a31-sc-nmi";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x01f00c0c 0x38>;
			interrupts = <0 32 4>;
		};

		prcm@01f01400 {
			compatible = "allwinner,sun6i-a31-prcm";
			reg = <0x01f01400 0x200>;
		};

		cpucfg@01f01c00 {
			compatible = "allwinner,sun6i-a31-cpuconfig";
			reg = <0x01f01c00 0x300>;
		};
	};
};
Commit	Line	Data
8aed3b31 MR	1	/*
	2	* Copyright 2013 Maxime Ripard
	3	*
	4	* Maxime Ripard <maxime.ripard@free-electrons.com>
	5	*
	6	* The code contained herein is licensed under the GNU General Public
	7	* License. You may obtain a copy of the GNU General Public License
	8	* Version 2 or later at the following locations:
	9	*
	10	* http://www.opensource.org/licenses/gpl-license.html
	11	* http://www.gnu.org/copyleft/gpl.html
	12	*/
	13
	14	/include/ "skeleton.dtsi"
	15
	16	/ {
	17	interrupt-parent = <&gic>;
	18
54428d40 MR	19	aliases {
	20	serial0 = &uart0;
	21	serial1 = &uart1;
	22	serial2 = &uart2;
	23	serial3 = &uart3;
	24	serial4 = &uart4;
	25	serial5 = &uart5;
	26	};
	27
	28
8aed3b31 MR	29	cpus {
	30	#address-cells = <1>;
	31	#size-cells = <0>;
	32
	33	cpu@0 {
	34	compatible = "arm,cortex-a7";
	35	device_type = "cpu";
	36	reg = <0>;
	37	};
	38
	39	cpu@1 {
	40	compatible = "arm,cortex-a7";
	41	device_type = "cpu";
	42	reg = <1>;
	43	};
	44
	45	cpu@2 {
	46	compatible = "arm,cortex-a7";
	47	device_type = "cpu";
	48	reg = <2>;
	49	};
	50
	51	cpu@3 {
	52	compatible = "arm,cortex-a7";
	53	device_type = "cpu";
	54	reg = <3>;
	55	};
	56	};
	57
	58	memory {
	59	reg = <0x40000000 0x80000000>;
	60	};
	61
b5a10b76 MR	62	pmu {
	63	compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
	64	interrupts = <0 120 4>,
	65	<0 121 4>,
	66	<0 122 4>,
	67	<0 123 4>;
	68	};
	69
8aed3b31 MR	70	clocks {
8aed3b31 MR	71	#address-cells = <1>;
98096560 MR	72	#size-cells = <1>;
98096560 MR	73	ranges;
8aed3b31	74
98096560	75	osc24M: osc24M {
8aed3b31 MR	76	#clock-cells = <0>;
	77	compatible = "fixed-clock";
	78	clock-frequency = <24000000>;
	79	};
98096560	80
7b5b2909	81	osc32k: clk@0 {
98096560 MR	82	#clock-cells = <0>;
	83	compatible = "fixed-clock";
	84	clock-frequency = <32768>;
7b5b2909	85	clock-output-names = "osc32k";
98096560 MR	86	};
98096560 MR	87
7b5b2909	88	pll1: clk@01c20000 {
98096560 MR	89	#clock-cells = <0>;
	90	compatible = "allwinner,sun6i-a31-pll1-clk";
	91	reg = <0x01c20000 0x4>;
	92	clocks = <&osc24M>;
7b5b2909	93	clock-output-names = "pll1";
98096560 MR	94	};
98096560 MR	95
b0a09c75	96	pll6: clk@01c20028 {
98096560	97	#clock-cells = <0>;
b0a09c75 MR	98	compatible = "allwinner,sun6i-a31-pll6-clk";
	99	reg = <0x01c20028 0x4>;
	100	clocks = <&osc24M>;
	101	clock-output-names = "pll6";
98096560 MR	102	};
	103
	104	cpu: cpu@01c20050 {
	105	#clock-cells = <0>;
bf6534a1	106	compatible = "allwinner,sun4i-a10-cpu-clk";
98096560 MR	107	reg = <0x01c20050 0x4>;
	108
	109	/*
	110	* PLL1 is listed twice here.
	111	* While it looks suspicious, it's actually documented
	112	* that way both in the datasheet and in the code from
	113	* Allwinner.
	114	*/
	115	clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
7b5b2909	116	clock-output-names = "cpu";
98096560 MR	117	};
	118
	119	axi: axi@01c20050 {
	120	#clock-cells = <0>;
bf6534a1	121	compatible = "allwinner,sun4i-a10-axi-clk";
98096560 MR	122	reg = <0x01c20050 0x4>;
98096560 MR	123	clocks = <&cpu>;
7b5b2909	124	clock-output-names = "axi";
98096560 MR	125	};
	126
	127	ahb1_mux: ahb1_mux@01c20054 {
	128	#clock-cells = <0>;
	129	compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
	130	reg = <0x01c20054 0x4>;
	131	clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
7b5b2909	132	clock-output-names = "ahb1_mux";
98096560 MR	133	};
	134
	135	ahb1: ahb1@01c20054 {
	136	#clock-cells = <0>;
bf6534a1	137	compatible = "allwinner,sun4i-a10-ahb-clk";
98096560 MR	138	reg = <0x01c20054 0x4>;
98096560 MR	139	clocks = <&ahb1_mux>;
7b5b2909	140	clock-output-names = "ahb1";
98096560 MR	141	};
98096560 MR	142
7b5b2909	143	ahb1_gates: clk@01c20060 {
98096560 MR	144	#clock-cells = <1>;
	145	compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
	146	reg = <0x01c20060 0x8>;
	147	clocks = <&ahb1>;
	148	clock-output-names = "ahb1_mipidsi", "ahb1_ss",
	149	"ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
	150	"ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
	151	"ahb1_nand0", "ahb1_sdram",
	152	"ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
	153	"ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
	154	"ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
	155	"ahb1_ehci1", "ahb1_ohci0",
	156	"ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
	157	"ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
	158	"ahb1_hdmi", "ahb1_de0", "ahb1_de1",
	159	"ahb1_fe0", "ahb1_fe1", "ahb1_mp",
	160	"ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
	161	"ahb1_drc0", "ahb1_drc1";
	162	};
	163
	164	apb1: apb1@01c20054 {
	165	#clock-cells = <0>;
bf6534a1	166	compatible = "allwinner,sun4i-a10-apb0-clk";
98096560 MR	167	reg = <0x01c20054 0x4>;
98096560 MR	168	clocks = <&ahb1>;
7b5b2909	169	clock-output-names = "apb1";
98096560 MR	170	};
98096560 MR	171
7b5b2909	172	apb1_gates: clk@01c20068 {
98096560 MR	173	#clock-cells = <1>;
	174	compatible = "allwinner,sun6i-a31-apb1-gates-clk";
	175	reg = <0x01c20068 0x4>;
	176	clocks = <&apb1>;
	177	clock-output-names = "apb1_codec", "apb1_digital_mic",
	178	"apb1_pio", "apb1_daudio0",
	179	"apb1_daudio1";
	180	};
	181
	182	apb2_mux: apb2_mux@01c20058 {
	183	#clock-cells = <0>;
bf6534a1	184	compatible = "allwinner,sun4i-a10-apb1-mux-clk";
98096560 MR	185	reg = <0x01c20058 0x4>;
98096560 MR	186	clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
7b5b2909	187	clock-output-names = "apb2_mux";
98096560 MR	188	};
	189
	190	apb2: apb2@01c20058 {
	191	#clock-cells = <0>;
	192	compatible = "allwinner,sun6i-a31-apb2-div-clk";
	193	reg = <0x01c20058 0x4>;
	194	clocks = <&apb2_mux>;
7b5b2909	195	clock-output-names = "apb2";
98096560 MR	196	};
98096560 MR	197
7b5b2909	198	apb2_gates: clk@01c2006c {
98096560 MR	199	#clock-cells = <1>;
98096560 MR	200	compatible = "allwinner,sun6i-a31-apb2-gates-clk";
439d9f58	201	reg = <0x01c2006c 0x4>;
98096560 MR	202	clocks = <&apb2>;
	203	clock-output-names = "apb2_i2c0", "apb2_i2c1",
	204	"apb2_i2c2", "apb2_i2c3", "apb2_uart0",
	205	"apb2_uart1", "apb2_uart2", "apb2_uart3",
	206	"apb2_uart4", "apb2_uart5";
	207	};
b0a09c75 MR	208
	209	spi0_clk: clk@01c200a0 {
	210	#clock-cells = <0>;
225b0216	211	compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 MR	212	reg = <0x01c200a0 0x4>;
	213	clocks = <&osc24M>, <&pll6>;
	214	clock-output-names = "spi0";
	215	};
	216
	217	spi1_clk: clk@01c200a4 {
	218	#clock-cells = <0>;
225b0216	219	compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 MR	220	reg = <0x01c200a4 0x4>;
	221	clocks = <&osc24M>, <&pll6>;
	222	clock-output-names = "spi1";
	223	};
	224
	225	spi2_clk: clk@01c200a8 {
	226	#clock-cells = <0>;
225b0216	227	compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 MR	228	reg = <0x01c200a8 0x4>;
	229	clocks = <&osc24M>, <&pll6>;
	230	clock-output-names = "spi2";
	231	};
	232
	233	spi3_clk: clk@01c200ac {
	234	#clock-cells = <0>;
225b0216	235	compatible = "allwinner,sun4i-a10-mod0-clk";
b0a09c75 MR	236	reg = <0x01c200ac 0x4>;
	237	clocks = <&osc24M>, <&pll6>;
	238	clock-output-names = "spi3";
	239	};
8aed3b31 MR	240	};
	241
	242	soc@01c00000 {
	243	compatible = "simple-bus";
	244	#address-cells = <1>;
	245	#size-cells = <1>;
	246	ranges;
	247
d2d878c4 MR	248	dma: dma-controller@01c02000 {
	249	compatible = "allwinner,sun6i-a31-dma";
	250	reg = <0x01c02000 0x1000>;
	251	interrupts = <0 50 4>;
	252	clocks = <&ahb1_gates 6>;
	253	resets = <&ahb1_rst 6>;
	254	#dma-cells = <1>;
	255	};
	256
140e1721 MR	257	pio: pinctrl@01c20800 {
	258	compatible = "allwinner,sun6i-a31-pinctrl";
	259	reg = <0x01c20800 0x400>;
6f97dc8d MR	260	interrupts = <0 11 4>,
	261	<0 15 4>,
	262	<0 16 4>,
	263	<0 17 4>;
98096560	264	clocks = <&apb1_gates 5>;
140e1721 MR	265	gpio-controller;
	266	interrupt-controller;
	267	#address-cells = <1>;
	268	#size-cells = <0>;
	269	#gpio-cells = <3>;
ab4238cd MR	270
	271	uart0_pins_a: uart0@0 {
	272	allwinner,pins = "PH20", "PH21";
	273	allwinner,function = "uart0";
	274	allwinner,drive = <0>;
	275	allwinner,pull = <0>;
	276	};
8be188b8 MR	277
	278	i2c0_pins_a: i2c0@0 {
	279	allwinner,pins = "PH14", "PH15";
	280	allwinner,function = "i2c0";
	281	allwinner,drive = <0>;
	282	allwinner,pull = <0>;
	283	};
	284
	285	i2c1_pins_a: i2c1@0 {
	286	allwinner,pins = "PH16", "PH17";
	287	allwinner,function = "i2c1";
	288	allwinner,drive = <0>;
	289	allwinner,pull = <0>;
	290	};
	291
	292	i2c2_pins_a: i2c2@0 {
	293	allwinner,pins = "PH18", "PH19";
	294	allwinner,function = "i2c2";
	295	allwinner,drive = <0>;
	296	allwinner,pull = <0>;
	297	};
9797eb83 HG	298
	299	mmc0_pins_a: mmc0@0 {
	300	allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
	301	allwinner,function = "mmc0";
	302	allwinner,drive = <2>;
	303	allwinner,pull = <0>;
	304	};
140e1721 MR	305	};
140e1721 MR	306
24a661e9 MR	307	ahb1_rst: reset@01c202c0 {
	308	#reset-cells = <1>;
	309	compatible = "allwinner,sun6i-a31-ahb1-reset";
	310	reg = <0x01c202c0 0xc>;
	311	};
	312
	313	apb1_rst: reset@01c202d0 {
	314	#reset-cells = <1>;
	315	compatible = "allwinner,sun6i-a31-clock-reset";
	316	reg = <0x01c202d0 0x4>;
	317	};
	318
	319	apb2_rst: reset@01c202d8 {
	320	#reset-cells = <1>;
	321	compatible = "allwinner,sun6i-a31-clock-reset";
	322	reg = <0x01c202d8 0x4>;
	323	};
	324
8aed3b31	325	timer@01c20c00 {
b4f26440	326	compatible = "allwinner,sun4i-a10-timer";
8aed3b31	327	reg = <0x01c20c00 0xa0>;
6f97dc8d MR	328	interrupts = <0 18 4>,
	329	<0 19 4>,
	330	<0 20 4>,
	331	<0 21 4>,
	332	<0 22 4>;
98096560	333	clocks = <&osc24M>;
8aed3b31 MR	334	};
	335
	336	wdt1: watchdog@01c20ca0 {
ca5d04d9	337	compatible = "allwinner,sun6i-a31-wdt";
8aed3b31 MR	338	reg = <0x01c20ca0 0x20>;
	339	};
	340
	341	uart0: serial@01c28000 {
	342	compatible = "snps,dw-apb-uart";
	343	reg = <0x01c28000 0x400>;
6f97dc8d	344	interrupts = <0 0 4>;
8aed3b31 MR	345	reg-shift = <2>;
8aed3b31 MR	346	reg-io-width = <4>;
98096560	347	clocks = <&apb2_gates 16>;
24a661e9	348	resets = <&apb2_rst 16>;
d2d878c4 MR	349	dmas = <&dma 6>, <&dma 6>;
d2d878c4 MR	350	dma-names = "rx", "tx";
8aed3b31 MR	351	status = "disabled";
	352	};
	353
	354	uart1: serial@01c28400 {
	355	compatible = "snps,dw-apb-uart";
	356	reg = <0x01c28400 0x400>;
6f97dc8d	357	interrupts = <0 1 4>;
8aed3b31 MR	358	reg-shift = <2>;
8aed3b31 MR	359	reg-io-width = <4>;
98096560	360	clocks = <&apb2_gates 17>;
24a661e9	361	resets = <&apb2_rst 17>;
d2d878c4 MR	362	dmas = <&dma 7>, <&dma 7>;
d2d878c4 MR	363	dma-names = "rx", "tx";
8aed3b31 MR	364	status = "disabled";
	365	};
	366
	367	uart2: serial@01c28800 {
	368	compatible = "snps,dw-apb-uart";
	369	reg = <0x01c28800 0x400>;
6f97dc8d	370	interrupts = <0 2 4>;
8aed3b31 MR	371	reg-shift = <2>;
8aed3b31 MR	372	reg-io-width = <4>;
98096560	373	clocks = <&apb2_gates 18>;
24a661e9	374	resets = <&apb2_rst 18>;
d2d878c4 MR	375	dmas = <&dma 8>, <&dma 8>;
d2d878c4 MR	376	dma-names = "rx", "tx";
8aed3b31 MR	377	status = "disabled";
	378	};
	379
	380	uart3: serial@01c28c00 {
	381	compatible = "snps,dw-apb-uart";
	382	reg = <0x01c28c00 0x400>;
6f97dc8d	383	interrupts = <0 3 4>;
8aed3b31 MR	384	reg-shift = <2>;
8aed3b31 MR	385	reg-io-width = <4>;
98096560	386	clocks = <&apb2_gates 19>;
24a661e9	387	resets = <&apb2_rst 19>;
d2d878c4 MR	388	dmas = <&dma 9>, <&dma 9>;
d2d878c4 MR	389	dma-names = "rx", "tx";
8aed3b31 MR	390	status = "disabled";
	391	};
	392
	393	uart4: serial@01c29000 {
	394	compatible = "snps,dw-apb-uart";
	395	reg = <0x01c29000 0x400>;
6f97dc8d	396	interrupts = <0 4 4>;
8aed3b31 MR	397	reg-shift = <2>;
8aed3b31 MR	398	reg-io-width = <4>;
98096560	399	clocks = <&apb2_gates 20>;
24a661e9	400	resets = <&apb2_rst 20>;
d2d878c4 MR	401	dmas = <&dma 10>, <&dma 10>;
d2d878c4 MR	402	dma-names = "rx", "tx";
8aed3b31 MR	403	status = "disabled";
	404	};
	405
	406	uart5: serial@01c29400 {
	407	compatible = "snps,dw-apb-uart";
	408	reg = <0x01c29400 0x400>;
6f97dc8d	409	interrupts = <0 5 4>;
8aed3b31 MR	410	reg-shift = <2>;
8aed3b31 MR	411	reg-io-width = <4>;
98096560	412	clocks = <&apb2_gates 21>;
24a661e9	413	resets = <&apb2_rst 21>;
d2d878c4 MR	414	dmas = <&dma 22>, <&dma 22>;
d2d878c4 MR	415	dma-names = "rx", "tx";
8aed3b31 MR	416	status = "disabled";
	417	};
	418
96c7cc9b MR	419	i2c0: i2c@01c2ac00 {
	420	compatible = "allwinner,sun6i-a31-i2c";
	421	reg = <0x01c2ac00 0x400>;
	422	interrupts = <0 6 4>;
	423	clocks = <&apb2_gates 0>;
	424	clock-frequency = <100000>;
	425	resets = <&apb2_rst 0>;
	426	status = "disabled";
	427	};
	428
	429	i2c1: i2c@01c2b000 {
	430	compatible = "allwinner,sun6i-a31-i2c";
	431	reg = <0x01c2b000 0x400>;
	432	interrupts = <0 7 4>;
	433	clocks = <&apb2_gates 1>;
	434	clock-frequency = <100000>;
	435	resets = <&apb2_rst 1>;
	436	status = "disabled";
	437	};
	438
	439	i2c2: i2c@01c2b400 {
	440	compatible = "allwinner,sun6i-a31-i2c";
	441	reg = <0x01c2b400 0x400>;
	442	interrupts = <0 8 4>;
	443	clocks = <&apb2_gates 2>;
	444	clock-frequency = <100000>;
	445	resets = <&apb2_rst 2>;
	446	status = "disabled";
	447	};
	448
	449	i2c3: i2c@01c2b800 {
	450	compatible = "allwinner,sun6i-a31-i2c";
	451	reg = <0x01c2b800 0x400>;
	452	interrupts = <0 9 4>;
	453	clocks = <&apb2_gates 3>;
	454	clock-frequency = <100000>;
	455	resets = <&apb2_rst 3>;
	456	status = "disabled";
	457	};
	458
0d6efe33 MR	459	spi0: spi@01c68000 {
	460	compatible = "allwinner,sun6i-a31-spi";
	461	reg = <0x01c68000 0x1000>;
	462	interrupts = <0 65 4>;
	463	clocks = <&ahb1_gates 20>, <&spi0_clk>;
	464	clock-names = "ahb", "mod";
d2d878c4 MR	465	dmas = <&dma 23>, <&dma 23>;
d2d878c4 MR	466	dma-names = "rx", "tx";
0d6efe33 MR	467	resets = <&ahb1_rst 20>;
	468	status = "disabled";
	469	};
	470
	471	spi1: spi@01c69000 {
	472	compatible = "allwinner,sun6i-a31-spi";
	473	reg = <0x01c69000 0x1000>;
	474	interrupts = <0 66 4>;
	475	clocks = <&ahb1_gates 21>, <&spi1_clk>;
	476	clock-names = "ahb", "mod";
d2d878c4 MR	477	dmas = <&dma 24>, <&dma 24>;
d2d878c4 MR	478	dma-names = "rx", "tx";
0d6efe33 MR	479	resets = <&ahb1_rst 21>;
	480	status = "disabled";
	481	};
	482
	483	spi2: spi@01c6a000 {
	484	compatible = "allwinner,sun6i-a31-spi";
	485	reg = <0x01c6a000 0x1000>;
	486	interrupts = <0 67 4>;
	487	clocks = <&ahb1_gates 22>, <&spi2_clk>;
	488	clock-names = "ahb", "mod";
d2d878c4 MR	489	dmas = <&dma 25>, <&dma 25>;
d2d878c4 MR	490	dma-names = "rx", "tx";
0d6efe33 MR	491	resets = <&ahb1_rst 22>;
	492	status = "disabled";
	493	};
	494
	495	spi3: spi@01c6b000 {
	496	compatible = "allwinner,sun6i-a31-spi";
	497	reg = <0x01c6b000 0x1000>;
	498	interrupts = <0 68 4>;
	499	clocks = <&ahb1_gates 23>, <&spi3_clk>;
	500	clock-names = "ahb", "mod";
d2d878c4 MR	501	dmas = <&dma 26>, <&dma 26>;
d2d878c4 MR	502	dma-names = "rx", "tx";
0d6efe33 MR	503	resets = <&ahb1_rst 23>;
	504	status = "disabled";
	505	};
	506
8aed3b31 MR	507	gic: interrupt-controller@01c81000 {
	508	compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
	509	reg = <0x01c81000 0x1000>,
	510	<0x01c82000 0x1000>,
	511	<0x01c84000 0x2000>,
	512	<0x01c86000 0x2000>;
	513	interrupt-controller;
	514	#interrupt-cells = <3>;
	515	interrupts = <1 9 0xf04>;
	516	};
81ee429f	517
28240d27 MR	518	nmi_intc: interrupt-controller@01f00c0c {
	519	compatible = "allwinner,sun6i-a31-sc-nmi";
	520	interrupt-controller;
	521	#interrupt-cells = <2>;
	522	reg = <0x01f00c0c 0x38>;
	523	interrupts = <0 32 4>;
	524	};
	525
a42ea603 HG	526	prcm@01f01400 {
	527	compatible = "allwinner,sun6i-a31-prcm";
	528	reg = <0x01f01400 0x200>;
	529	};
	530
81ee429f MR	531	cpucfg@01f01c00 {
	532	compatible = "allwinner,sun6i-a31-cpuconfig";
	533	reg = <0x01f01c00 0x300>;
	534	};
8aed3b31 MR	535	};
8aed3b31 MR	536	};