ARM: sunxi: dt: Update the watchdog compatibles
[deliverable/linux.git] / arch / arm / boot / dts / sun6i-a31.dtsi
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1/*
2 * Copyright 2013 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "skeleton.dtsi"
15
16/ {
17 interrupt-parent = <&gic>;
18
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19 aliases {
20 serial0 = &uart0;
21 serial1 = &uart1;
22 serial2 = &uart2;
23 serial3 = &uart3;
24 serial4 = &uart4;
25 serial5 = &uart5;
26 };
27
28
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29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
32
33 cpu@0 {
34 compatible = "arm,cortex-a7";
35 device_type = "cpu";
36 reg = <0>;
37 };
38
39 cpu@1 {
40 compatible = "arm,cortex-a7";
41 device_type = "cpu";
42 reg = <1>;
43 };
44
45 cpu@2 {
46 compatible = "arm,cortex-a7";
47 device_type = "cpu";
48 reg = <2>;
49 };
50
51 cpu@3 {
52 compatible = "arm,cortex-a7";
53 device_type = "cpu";
54 reg = <3>;
55 };
56 };
57
58 memory {
59 reg = <0x40000000 0x80000000>;
60 };
61
62 clocks {
63 #address-cells = <1>;
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64 #size-cells = <1>;
65 ranges;
8aed3b31 66
98096560 67 osc24M: osc24M {
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68 #clock-cells = <0>;
69 compatible = "fixed-clock";
70 clock-frequency = <24000000>;
71 };
98096560 72
7b5b2909 73 osc32k: clk@0 {
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74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <32768>;
7b5b2909 77 clock-output-names = "osc32k";
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78 };
79
7b5b2909 80 pll1: clk@01c20000 {
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81 #clock-cells = <0>;
82 compatible = "allwinner,sun6i-a31-pll1-clk";
83 reg = <0x01c20000 0x4>;
84 clocks = <&osc24M>;
7b5b2909 85 clock-output-names = "pll1";
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86 };
87
b0a09c75 88 pll6: clk@01c20028 {
98096560 89 #clock-cells = <0>;
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90 compatible = "allwinner,sun6i-a31-pll6-clk";
91 reg = <0x01c20028 0x4>;
92 clocks = <&osc24M>;
93 clock-output-names = "pll6";
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94 };
95
96 cpu: cpu@01c20050 {
97 #clock-cells = <0>;
bf6534a1 98 compatible = "allwinner,sun4i-a10-cpu-clk";
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99 reg = <0x01c20050 0x4>;
100
101 /*
102 * PLL1 is listed twice here.
103 * While it looks suspicious, it's actually documented
104 * that way both in the datasheet and in the code from
105 * Allwinner.
106 */
107 clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
7b5b2909 108 clock-output-names = "cpu";
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109 };
110
111 axi: axi@01c20050 {
112 #clock-cells = <0>;
bf6534a1 113 compatible = "allwinner,sun4i-a10-axi-clk";
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114 reg = <0x01c20050 0x4>;
115 clocks = <&cpu>;
7b5b2909 116 clock-output-names = "axi";
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117 };
118
119 ahb1_mux: ahb1_mux@01c20054 {
120 #clock-cells = <0>;
121 compatible = "allwinner,sun6i-a31-ahb1-mux-clk";
122 reg = <0x01c20054 0x4>;
123 clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6>;
7b5b2909 124 clock-output-names = "ahb1_mux";
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125 };
126
127 ahb1: ahb1@01c20054 {
128 #clock-cells = <0>;
bf6534a1 129 compatible = "allwinner,sun4i-a10-ahb-clk";
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130 reg = <0x01c20054 0x4>;
131 clocks = <&ahb1_mux>;
7b5b2909 132 clock-output-names = "ahb1";
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133 };
134
7b5b2909 135 ahb1_gates: clk@01c20060 {
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136 #clock-cells = <1>;
137 compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
138 reg = <0x01c20060 0x8>;
139 clocks = <&ahb1>;
140 clock-output-names = "ahb1_mipidsi", "ahb1_ss",
141 "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
142 "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
143 "ahb1_nand0", "ahb1_sdram",
144 "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
145 "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
146 "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
147 "ahb1_ehci1", "ahb1_ohci0",
148 "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
149 "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
150 "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
151 "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
152 "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
153 "ahb1_drc0", "ahb1_drc1";
154 };
155
156 apb1: apb1@01c20054 {
157 #clock-cells = <0>;
bf6534a1 158 compatible = "allwinner,sun4i-a10-apb0-clk";
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159 reg = <0x01c20054 0x4>;
160 clocks = <&ahb1>;
7b5b2909 161 clock-output-names = "apb1";
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162 };
163
7b5b2909 164 apb1_gates: clk@01c20068 {
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165 #clock-cells = <1>;
166 compatible = "allwinner,sun6i-a31-apb1-gates-clk";
167 reg = <0x01c20068 0x4>;
168 clocks = <&apb1>;
169 clock-output-names = "apb1_codec", "apb1_digital_mic",
170 "apb1_pio", "apb1_daudio0",
171 "apb1_daudio1";
172 };
173
174 apb2_mux: apb2_mux@01c20058 {
175 #clock-cells = <0>;
bf6534a1 176 compatible = "allwinner,sun4i-a10-apb1-mux-clk";
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177 reg = <0x01c20058 0x4>;
178 clocks = <&osc32k>, <&osc24M>, <&pll6>, <&pll6>;
7b5b2909 179 clock-output-names = "apb2_mux";
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180 };
181
182 apb2: apb2@01c20058 {
183 #clock-cells = <0>;
184 compatible = "allwinner,sun6i-a31-apb2-div-clk";
185 reg = <0x01c20058 0x4>;
186 clocks = <&apb2_mux>;
7b5b2909 187 clock-output-names = "apb2";
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188 };
189
7b5b2909 190 apb2_gates: clk@01c2006c {
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191 #clock-cells = <1>;
192 compatible = "allwinner,sun6i-a31-apb2-gates-clk";
439d9f58 193 reg = <0x01c2006c 0x4>;
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194 clocks = <&apb2>;
195 clock-output-names = "apb2_i2c0", "apb2_i2c1",
196 "apb2_i2c2", "apb2_i2c3", "apb2_uart0",
197 "apb2_uart1", "apb2_uart2", "apb2_uart3",
198 "apb2_uart4", "apb2_uart5";
199 };
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200
201 spi0_clk: clk@01c200a0 {
202 #clock-cells = <0>;
225b0216 203 compatible = "allwinner,sun4i-a10-mod0-clk";
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204 reg = <0x01c200a0 0x4>;
205 clocks = <&osc24M>, <&pll6>;
206 clock-output-names = "spi0";
207 };
208
209 spi1_clk: clk@01c200a4 {
210 #clock-cells = <0>;
225b0216 211 compatible = "allwinner,sun4i-a10-mod0-clk";
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212 reg = <0x01c200a4 0x4>;
213 clocks = <&osc24M>, <&pll6>;
214 clock-output-names = "spi1";
215 };
216
217 spi2_clk: clk@01c200a8 {
218 #clock-cells = <0>;
225b0216 219 compatible = "allwinner,sun4i-a10-mod0-clk";
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220 reg = <0x01c200a8 0x4>;
221 clocks = <&osc24M>, <&pll6>;
222 clock-output-names = "spi2";
223 };
224
225 spi3_clk: clk@01c200ac {
226 #clock-cells = <0>;
225b0216 227 compatible = "allwinner,sun4i-a10-mod0-clk";
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228 reg = <0x01c200ac 0x4>;
229 clocks = <&osc24M>, <&pll6>;
230 clock-output-names = "spi3";
231 };
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232 };
233
234 soc@01c00000 {
235 compatible = "simple-bus";
236 #address-cells = <1>;
237 #size-cells = <1>;
238 ranges;
239
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240 pio: pinctrl@01c20800 {
241 compatible = "allwinner,sun6i-a31-pinctrl";
242 reg = <0x01c20800 0x400>;
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243 interrupts = <0 11 4>,
244 <0 15 4>,
245 <0 16 4>,
246 <0 17 4>;
98096560 247 clocks = <&apb1_gates 5>;
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248 gpio-controller;
249 interrupt-controller;
250 #address-cells = <1>;
251 #size-cells = <0>;
252 #gpio-cells = <3>;
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253
254 uart0_pins_a: uart0@0 {
255 allwinner,pins = "PH20", "PH21";
256 allwinner,function = "uart0";
257 allwinner,drive = <0>;
258 allwinner,pull = <0>;
259 };
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260
261 i2c0_pins_a: i2c0@0 {
262 allwinner,pins = "PH14", "PH15";
263 allwinner,function = "i2c0";
264 allwinner,drive = <0>;
265 allwinner,pull = <0>;
266 };
267
268 i2c1_pins_a: i2c1@0 {
269 allwinner,pins = "PH16", "PH17";
270 allwinner,function = "i2c1";
271 allwinner,drive = <0>;
272 allwinner,pull = <0>;
273 };
274
275 i2c2_pins_a: i2c2@0 {
276 allwinner,pins = "PH18", "PH19";
277 allwinner,function = "i2c2";
278 allwinner,drive = <0>;
279 allwinner,pull = <0>;
280 };
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281 };
282
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283 ahb1_rst: reset@01c202c0 {
284 #reset-cells = <1>;
285 compatible = "allwinner,sun6i-a31-ahb1-reset";
286 reg = <0x01c202c0 0xc>;
287 };
288
289 apb1_rst: reset@01c202d0 {
290 #reset-cells = <1>;
291 compatible = "allwinner,sun6i-a31-clock-reset";
292 reg = <0x01c202d0 0x4>;
293 };
294
295 apb2_rst: reset@01c202d8 {
296 #reset-cells = <1>;
297 compatible = "allwinner,sun6i-a31-clock-reset";
298 reg = <0x01c202d8 0x4>;
299 };
300
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301 timer@01c20c00 {
302 compatible = "allwinner,sun4i-timer";
303 reg = <0x01c20c00 0xa0>;
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304 interrupts = <0 18 4>,
305 <0 19 4>,
306 <0 20 4>,
307 <0 21 4>,
308 <0 22 4>;
98096560 309 clocks = <&osc24M>;
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310 };
311
312 wdt1: watchdog@01c20ca0 {
ca5d04d9 313 compatible = "allwinner,sun6i-a31-wdt";
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314 reg = <0x01c20ca0 0x20>;
315 };
316
317 uart0: serial@01c28000 {
318 compatible = "snps,dw-apb-uart";
319 reg = <0x01c28000 0x400>;
6f97dc8d 320 interrupts = <0 0 4>;
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321 reg-shift = <2>;
322 reg-io-width = <4>;
98096560 323 clocks = <&apb2_gates 16>;
24a661e9 324 resets = <&apb2_rst 16>;
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325 status = "disabled";
326 };
327
328 uart1: serial@01c28400 {
329 compatible = "snps,dw-apb-uart";
330 reg = <0x01c28400 0x400>;
6f97dc8d 331 interrupts = <0 1 4>;
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332 reg-shift = <2>;
333 reg-io-width = <4>;
98096560 334 clocks = <&apb2_gates 17>;
24a661e9 335 resets = <&apb2_rst 17>;
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336 status = "disabled";
337 };
338
339 uart2: serial@01c28800 {
340 compatible = "snps,dw-apb-uart";
341 reg = <0x01c28800 0x400>;
6f97dc8d 342 interrupts = <0 2 4>;
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343 reg-shift = <2>;
344 reg-io-width = <4>;
98096560 345 clocks = <&apb2_gates 18>;
24a661e9 346 resets = <&apb2_rst 18>;
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347 status = "disabled";
348 };
349
350 uart3: serial@01c28c00 {
351 compatible = "snps,dw-apb-uart";
352 reg = <0x01c28c00 0x400>;
6f97dc8d 353 interrupts = <0 3 4>;
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354 reg-shift = <2>;
355 reg-io-width = <4>;
98096560 356 clocks = <&apb2_gates 19>;
24a661e9 357 resets = <&apb2_rst 19>;
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358 status = "disabled";
359 };
360
361 uart4: serial@01c29000 {
362 compatible = "snps,dw-apb-uart";
363 reg = <0x01c29000 0x400>;
6f97dc8d 364 interrupts = <0 4 4>;
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365 reg-shift = <2>;
366 reg-io-width = <4>;
98096560 367 clocks = <&apb2_gates 20>;
24a661e9 368 resets = <&apb2_rst 20>;
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369 status = "disabled";
370 };
371
372 uart5: serial@01c29400 {
373 compatible = "snps,dw-apb-uart";
374 reg = <0x01c29400 0x400>;
6f97dc8d 375 interrupts = <0 5 4>;
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376 reg-shift = <2>;
377 reg-io-width = <4>;
98096560 378 clocks = <&apb2_gates 21>;
24a661e9 379 resets = <&apb2_rst 21>;
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380 status = "disabled";
381 };
382
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383 i2c0: i2c@01c2ac00 {
384 compatible = "allwinner,sun6i-a31-i2c";
385 reg = <0x01c2ac00 0x400>;
386 interrupts = <0 6 4>;
387 clocks = <&apb2_gates 0>;
388 clock-frequency = <100000>;
389 resets = <&apb2_rst 0>;
390 status = "disabled";
391 };
392
393 i2c1: i2c@01c2b000 {
394 compatible = "allwinner,sun6i-a31-i2c";
395 reg = <0x01c2b000 0x400>;
396 interrupts = <0 7 4>;
397 clocks = <&apb2_gates 1>;
398 clock-frequency = <100000>;
399 resets = <&apb2_rst 1>;
400 status = "disabled";
401 };
402
403 i2c2: i2c@01c2b400 {
404 compatible = "allwinner,sun6i-a31-i2c";
405 reg = <0x01c2b400 0x400>;
406 interrupts = <0 8 4>;
407 clocks = <&apb2_gates 2>;
408 clock-frequency = <100000>;
409 resets = <&apb2_rst 2>;
410 status = "disabled";
411 };
412
413 i2c3: i2c@01c2b800 {
414 compatible = "allwinner,sun6i-a31-i2c";
415 reg = <0x01c2b800 0x400>;
416 interrupts = <0 9 4>;
417 clocks = <&apb2_gates 3>;
418 clock-frequency = <100000>;
419 resets = <&apb2_rst 3>;
420 status = "disabled";
421 };
422
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423 spi0: spi@01c68000 {
424 compatible = "allwinner,sun6i-a31-spi";
425 reg = <0x01c68000 0x1000>;
426 interrupts = <0 65 4>;
427 clocks = <&ahb1_gates 20>, <&spi0_clk>;
428 clock-names = "ahb", "mod";
429 resets = <&ahb1_rst 20>;
430 status = "disabled";
431 };
432
433 spi1: spi@01c69000 {
434 compatible = "allwinner,sun6i-a31-spi";
435 reg = <0x01c69000 0x1000>;
436 interrupts = <0 66 4>;
437 clocks = <&ahb1_gates 21>, <&spi1_clk>;
438 clock-names = "ahb", "mod";
439 resets = <&ahb1_rst 21>;
440 status = "disabled";
441 };
442
443 spi2: spi@01c6a000 {
444 compatible = "allwinner,sun6i-a31-spi";
445 reg = <0x01c6a000 0x1000>;
446 interrupts = <0 67 4>;
447 clocks = <&ahb1_gates 22>, <&spi2_clk>;
448 clock-names = "ahb", "mod";
449 resets = <&ahb1_rst 22>;
450 status = "disabled";
451 };
452
453 spi3: spi@01c6b000 {
454 compatible = "allwinner,sun6i-a31-spi";
455 reg = <0x01c6b000 0x1000>;
456 interrupts = <0 68 4>;
457 clocks = <&ahb1_gates 23>, <&spi3_clk>;
458 clock-names = "ahb", "mod";
459 resets = <&ahb1_rst 23>;
460 status = "disabled";
461 };
462
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463 gic: interrupt-controller@01c81000 {
464 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
465 reg = <0x01c81000 0x1000>,
466 <0x01c82000 0x1000>,
467 <0x01c84000 0x2000>,
468 <0x01c86000 0x2000>;
469 interrupt-controller;
470 #interrupt-cells = <3>;
471 interrupts = <1 9 0xf04>;
472 };
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473
474 cpucfg@01f01c00 {
475 compatible = "allwinner,sun6i-a31-cpuconfig";
476 reg = <0x01f01c00 0x300>;
477 };
478
479 prcm@01f01c00 {
480 compatible = "allwinner,sun6i-a31-prcm";
481 reg = <0x01f01400 0x200>;
482 };
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483 };
484};
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